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Verilog Report

The document contains Verilog code for a binary full adder, a full subtractor, and a Johnson counter, along with their respective test benches. Each module includes logic for operations like sum, carry-out, difference, and counter progression, with test benches that monitor and display results for all possible input combinations. The document also includes waveform sections indicating the expected behavior of the circuits.

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03abhi09
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2 views8 pages

Verilog Report

The document contains Verilog code for a binary full adder, a full subtractor, and a Johnson counter, along with their respective test benches. Each module includes logic for operations like sum, carry-out, difference, and counter progression, with test benches that monitor and display results for all possible input combinations. The document also includes waveform sections indicating the expected behavior of the circuits.

Uploaded by

03abhi09
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Report on Verilog

Ques 1 Binary full adder

Code :
module full_adder (

input A,

input B,

input Cin,

output Sum,

output Cout

);

// Logic for sum and carry-out

assign Sum = A ^ B ^ Cin;

assign Cout = (A & B) | (B & Cin) | (A & Cin);

endmodule

Test bench :

module test_full_adder;

reg A, B, Cin;
wire Sum, Cout;

fulladderuut (

. A(A),

. B(B),

. Cin (Cin),

. Sum (Sum),

. Cout (Cout)

);

initial begin

// Display the results

$monitor ("A = %b, B = %b, Cin = %b | Sum = %b, Cout = %b", A, B, Cin,

Sum, Cout);

// Test all possible combinations of A, B, Cin

A = 0; B = 0; Cin = 0; #10;

A = 0; B = 0; Cin = 1; #10;

A = 0; B = 1; Cin = 0; #10;

A = 0; B = 1; Cin = 1; #10;

A = 1; B = 0; Cin = 0; #10;

A = 1; B = 0; Cin = 1; #10;

A = 1; B = 1; Cin = 0; #10;

A = 1; B = 1; Cin = 1; #10;

// End simulation

$finish;

end
endmodule

Waveform :

Ques 2 Full subtractor

Code:
module full_subtractor (

input A,

input B,

input Bin,

output Diff,

output Bout

);

assign Diff = A ^ B ^ Bin; // Difference is A XOR B XOR Bin

assign Bout = (~A & B) | ((~A | B) & Bin);

endmodule
test bench :
module test_full_subtractor;

// Declare inputs as registers and outputs as wires

reg A, B, Bin;

wire Diff, Bout;

full_subtractor uut (

.A(A),

.B(B),

.Bin(Bin),

.Diff(Diff),

.Bout(Bout)

);

initial begin

// Display the results

$monitor("A = %b, B = %b, Bin = %b | Diff = %b, Bout = %b", A, B, Bin, Diff,
Bout);

// Test all possible combinations of A, B, Bin

A = 0; B = 0; Bin = 0; #10;

A = 0; B = 0; Bin = 1; #10;

A = 0; B = 1; Bin = 0; #10;

A = 0; B = 1; Bin = 1; #10;

A = 1; B = 0; Bin = 0; #10;

A = 1; B = 0; Bin = 1; #10;

A = 1; B = 1; Bin = 0; #10;

A = 1; B = 1; Bin = 1; #10;
$finish;

end

endmodule

Waveform :

Ques 4 Johnson counter

Code :
module johnson_counter (

input clk,

input reset,

output reg [3:0] q

);

always @(posedge clk or posedge reset) begin

if (reset) begin
q <= 4'b0000; // Reset the counter to 0000

end else begin

// Shift the bits to the right, and invert the MSB to get the Johnson
counter sequence

q <= {q[2:0], ~q[3]};

end

end

endmodule

Test bench:
module test_johnson_counter;

reg clk;

reg reset;

wire [3:0] q;

johnson_counter uut (

.clk(clk),

.reset(reset),

.q(q)

);

always begin

#5 clk = ~clk; // Toggle clock every 5 time units

end

initial begin
// Initialize signals

clk = 0;

reset = 0;

$display("Test 1: Apply reset");

reset = 1;

#10;

reset = 0;

// Wait and observe the counter

$display("Test 2: Observe counter progression");

#10;

$finish;

end

// Monitor the output

initial begin

$monitor("Time = %0t, Reset = %b, Counter = %b", $time, reset, q);

end

endmodule

Waveform :

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