Data Sheet

ADF4368
Microwave Wideband Synthesizer with Integrated VCO

FEATURES GENERAL DESCRIPTION

► Output frequency range: 800 MHz to 12.8 GHz The ADF4368 is a high performance, ultra-low jitter, integer-N and
► Jitter < 30 fsRMS fOUT = 9.001 GHz, fREF = fPFD = 250 MHz, fractional-N phase-locked loop (PLL) with integrated VCO ideally
fractional mode suited for frequency conversion applications.
► Wideband phase noise floor: −160 dBc/Hz at 12.8 GHz The high performance PLL has a figure of merit of −239 dBc/Hz,
► PLL specifications very low 1/f noise of normalized −287 dBc/Hz and high PFD
► Normalized in-band phase noise floor frequency that can achieve ultra-low in-band noise and integrated
► −239 dBc/Hz: integer, −237 dBc/Hz: fractional mode jitter. The ADF4368 can generate any frequency from 800 MHz to
► Normalized 1/f phase noise floor 12.8 GHz without an internal doubler, which eliminates the need
for sub-harmonic filters. The Σ-Δ modulator includes a 25-bit fixed
► −287 dBc/Hz: normalized to 1 Hz
modulus that allows hertz frequency resolution and an additional
► −147 dBc/Hz: normalized to 1 GHz at 10 kHz 17-bit variable modulus, which allows even finer resolution and
► 625 MHz phase detector frequency integer mode flexibility for frequency planning. The 9 dBm output power at 12.8
► 250 MHz phase detector frequency fractional mode GHz in single-ended configuration with 16 step power adjust feature
► 25-bit fixed, 49-bit combined fractional modulus makes it very useful for any application.
► 4 GHz reference input frequency For multiple frequency conversion applications, such as phase
► Typical −95 dBc PFD spurs array radar or massive MIMO systems, the outputs of multiple
► Reference to output delay specifications ADF4368 can be aligned by using the SYNC input or EZSync™.
► Temperature coefficient: 0.06 ps/°C The EZSync method is used when it is difficult to distribute the
SYNC signal to all devices precisely. For applications that require
► Adjustment step size: <1 ps
deterministic delay or delay adjustment capability, a programmable
► Multichip output phase alignment reference to output delay with <1 ps resolution is provided. The
► Through SYNC pin or by EZSync method reference to output delay is guaranteed across multiple devices
► 3.3 V and 5 V power supplies and temperature, allowing for predictable and precise multichip
► ADIsimPLL™ loop filter design tool support alignment.
► Available in 48-lead, 7 mm × 7 mm LGA package The simplicity of the ADF4368 block diagram eases development
► −40°C to +125°C operating junction temperature time with a simplified serial-peripheral interface (SPI) register map,
external SYNC input, and repeatable multichip phase alignment
APPLICATIONS both in integer mode and fractional mode.
► Wireless infrastructure (MC-GSM, 5G) FUNCTIONAL BLOCK DIAGRAM
► Test and measurement
► Aerospace and defense

Figure 1. ADF4368 Block Diagram

Rev. 0
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Data Sheet ADF4368
TABLE OF CONTENTS

Features................................................................ 1 Introduction.......................................................16
Applications........................................................... 1 Output Frequency.............................................16
General Description...............................................1 Circuit Description............................................ 16
Functional Block Diagram......................................1 Applications Information...................................... 22
Specifications........................................................ 3 Loop Filter Design............................................ 22
Serial Interface Timing Characteristics...............7 Reference Source Considerations................... 22
Timing Diagrams................................................ 7 Output Phase Noise Characteristics................ 23
Absolute Maximum Ratings...................................8 Power-Up and Initialization Sequence............. 23
Transistor Count.................................................8 Power Supply and Bypassing...........................26
Thermal Resistance........................................... 8 Register Maps..................................................... 27
Electrostatic Discharge (ESD) Ratings...............8 Register Details................................................... 30
ESD Caution.......................................................8 Outline Dimensions............................................. 54
Pin Configuration and Function Descriptions........ 9 Ordering Guide.................................................54
Typical Performance Characteristics................... 11 Evaluation Boards............................................ 54
Theory of Operation.............................................16

REVISION HISTORY

3/2023—Revision 0: Initial Version

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Data Sheet ADF4368
SPECIFICATIONS

V3.3V_1 = V3.3V_2 = 3.15 V to 3.45 V, VV5_VCO = VV5_CP = VV5_CAL = 4.75 V to 5.25 V, all voltages are with respect to GND, TA = −40°C to 105°C
operating temperature range, unless otherwise noted.

Table 1. Electrical Specifications

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
REFERENCE INPUTS (REFP, REFN)
Input Frequency fREF 10 4000 MHz
Input Signal Level VREF 0.5 2.6 V p-p Differential
Min Input Slew Rate 100 V/μs
Input Duty Cycle 50 %
Self-Bias Voltage 1.85 V
Input Resistance 3 kΩ Differential
Input Capacitance 1 pF Differential
Input Current 2 μA
REFERENCE PEAK DETECTOR
Input Frequency 10 4000 MHz
Minimum Input Signal Detected (REF_OK = 1) 200 mVpp fREF = 100 MHz, single-ended sine wave
Maximum Input Signal Not Detected (REF_OK = 0) 160 mVpp fREF = 100 MHz, single-ended sine wave
SYNC INPUTS (SYNCP, SYNCN)
Input Signal Level VREF 0.41 2.61 V p-p LVDS mode, differential
VREF 0.51 2.61 V p-p CML mode, differential
Self-Bias Voltage 1.3 V LVDS mode
1.85 V CML mode
Input Resistance 3 kΩ Differential
Input Capacitance 1 pF Differential
Input Current 3 μA
REFERENCE DIVIDER (R)
R 1 63 All integers included
REFERENCE DOUBLER
Input Frequency fRDBL 10 250 MHz EN_RDBLR = 1
PHASE/FREQUENCY DETECTOR (PFD)
Input Frequency fPFD
31 625 MHz Integer mode
31 250 MHz Fractional mode sync or non-sync
applications
31 2501 MHz Fractional mode phase resync applications
when fOUT ≥ 3 GHz
751 2501 MHz Fractional mode phase resync applications
when fOUT < 3 GHz
CHARGE PUMP (CP)
Output Current Range ICP 0.79 to 11.1 mA Set by CP_I
Output Current Source/Sink Accuracy ±2 % All setting, = VCP = VV5_CP /2
Output Current Source/Sink Matching ±2 % All setting, VCP = VV5_CP /2
Output Current vs. Output Volt Sensitivity 0.2 %V/V 1.4 V < VV5_CP < VCP-5V – 1.6 V
Output Current vs. Temperature 400 ppm/C VCP = VV5_CP /2
Output High-Z Leakage Current −0.01 μA Minimum ICP, 1.4 V < VV5_CP < VCP-5V – 1.6 V
Output High-Z Leakage Current −0.3 μA Maximum ICP, 1.4 V < VV5_CP < VCP-5V – 1.6 V
VCO
Frequency Range fVCO 6.4 12.8 GHz
Tuning Sensitivity2, 3 KVCO 0.75 to 1.25 %Hz/V

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Data Sheet ADF4368
SPECIFICATIONS

Table 1. Electrical Specifications (Continued)

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DIV_RCLK VCO Calibration Frequency fDIV_RCLK 125 MHz Must set DCLK_MODE = 1, when fDIV_RCLK >
80 MHz
FEEDBACK (N) AND OUTPUT DIVIDER (O)
N 4 4095 Integer mode
19 4095 Fractional mode
O 1 8 1, 2, 4, 8
RF OUTPUTS (RFOUT1P/N, RFOUT2P/N) Differential termination = 100 Ω for all RF
output specifications, unless noted
Output Frequency fOUT 0.8 12.8 GHz
Output Single-Ended Power VOD 9 dBm CLK1_OPWR = CLK2_OPWR = 15, fOUT = 4
GHz to 12.8 GHz
5.5 dBm CLK1_OPWR = CLK2_OPWR = 10, fOUT = 4
GHz to 12.8 GHz
1.5 dBm CLK1_OPWR = CLK2_OPWR = 5, fOUT = 4
GHz to 12.8 GHz
−2 dBm CLK1_OPWR = CLK2_OPWR = 0, fOUT = 4
GHz to 12.8 GHz
Output Resistance 100 Ω Differential
Output Common Mode V3.3V_2 − V No pull-up inductor
VOD
V3.3V_2 V With pull-up inductor
Output Rise Time tR 18 ps 20%-80%, CLK1_OPWR = CLK2_OPWR =
10,
Output Fall Time tF 18 ps 80%-20%, CLK1_OPWR = CLK2_OPWR =
10,
Output Duty Cycle 50 %
Skew, RFOUT1 to RFOUT2 3±1 ps One ADF4368 device
3±1 ps Across multiple ADF4368 devices, TJ
within 10℃, same R_DIV, CLKOUT_DIV,
EN_RDBLR used
REFERENCE INPUT TO OUTPUT DELAY Device setup for all delay specifications,
unless noted, measure rising reference edge
at REFP input to rising edge at RFOUT1P
output
Propagation Delay tPD 190 ps REF_SEL = 0, R = 1, doubler = disabled
Propagation Delay Temperature Coefficient tPD 0.06 ps/°C REF_SEL = 0
LOGIC INPUTS (CSB, SCLK, SDIO, ENCLK1, ENCLK2)
Input High Voltage VINH 1.2 V
Input Low Voltage VINL 0.6 V
Input Current (High, Low) IIH/IIL ±1 µA
Input Capacitance CIN 2 pF
LOGIC INPUT (CE)
Input High Voltage VINH-3V 1.8 V
Input Low Voltage VINL-3V 0.8 V
Input Current (High, Low) IIH-3V/IIL-3V ±1 μA
Input Capacitance CIN-3V 1 pF
LOGIC OUTPUTS (SDIO, SDO, LKDET, MUXOUT)
Output High Voltage VOH 1.5 1.8 V IOH = 500 μA, 1.8 V output selected (default
setting)
Output High Voltage VOH-3V V3.3V − 0.4 IOH = 500 μA, 3.3 V output selected, set by
voltage on V_LDO pin

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Data Sheet ADF4368
SPECIFICATIONS

Table 1. Electrical Specifications (Continued)

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Output Low Voltage VOL 0.4 V IOL = 500 μA
SDO High-Z Leakage IZH/IZL ±1 μA
POWER SUPPLIES Device setup is default configuration for all
supply current specifications, unless noted
V5_VCO Supply Range VV5_VCO 4.75 5 5.25 V
V5_CAL Supply Range VV5_CAL 4.75 5 5.25 V
V5_CP Supply Range VV5_CP 4.75 5 5.25 V
V3.3V_1 Supply Range V3.3V_1 3.15 3.3 3.45 V Group 1: V3_LS, V3_LDO, V3_REF, V3_PFD,
V3_NDIV, V3_SYNC
V3.3V_2 Supply Range V3.3V_2 3.15 3.3 3.45 V Group 2: V3_RFOUT1, V3_RFOUT2,
V3_VCO, V3_CLKDIV
V5_VCO Supply Current IV5_VCO 98 mA fOUT = 12.8 GHz
173 220 mA fOUT = 6.4 GHz
V5_CAL Supply Current IV5_CAL 50 μA
8 mA During VCO calibration
V5_CP Supply Current IV5_CP 58 67 mA ICP = 11.1 mA, CP_I = 15
41 mA ICP = 0.79 mA, CP_I = 0
3.2 mA Additional current when EN_BLEED = 1,
BLEED_I = 8191
V3.3V_1 Supply Current I3.3V_1 185 210 mA fREF = 122.88 MHz, fPFD = 245.76 MHz,
fractional mode, CP_I = 15, PD_SYNC = 1
(sync disabled)
4 mA Additional current when PD_LD = 0
4 mA Additional current when PD_RDET = 1
V3_SYNC Supply Current IV3_SYNC 15 mA PD_SYNC = 0 (synchronization is enabled)
V3_RFOUTx Supply Current IV3_RFOUT 35 mA CLKx_OPWR = 0
47 mA CLKx_OPWR = 4
65 mA CLKx_OPWR = 8
90 mA CLKx_OPWR = 12
105 mA CLKx_OPWR = 15
V3_OUTDIV Supply Current IV3_OUTDIV 108 mA CLKOUT_DIV = 0 (divide by 1)
132 mA CLKOUT_DIV = 3 (divide by 8)
V3.3V_2 Supply Current I3.3V_2 149 mA ENRFOUT1 = low, CLK2_OPWR = 0
(minimum power), CLKOUT_DIV = 0, fOUT =
9.6 GHz
218 mA ENRFOUT1 = low, CLK2_OPWR = 15
(maximum power), CLKOUT_DIV = 0, fOUT =
9.6 GHz
172 mA ENRFOUT1 = low, CLK2_OPWR = 0
(minimum power), CLKOUT_DIV = 1, fOUT =
5.6 GHz
241 mA ENRFOUT1 = low, CLK2_OPWR = 15
(maximum power), CLKOUT_DIV = 1, fOUT =
5.6 GHz
Typical Power Dissipation PDIS 2.3 W ENRFOUT1 = low, CLK2_OPWR = 15
(maximum power), CLKOUT_DIV = 0, fOUT
= 9.6 GHz, SYNC block powered down,
fractional mode
2.1 W ENRFOUT1 = low, CLK2_OPWR = 15
(maximum power), CLKOUT_DIV = 1, fOUT

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Data Sheet ADF4368
SPECIFICATIONS

Table 1. Electrical Specifications (Continued)

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
= 5.6 GHz, SYNC block powered down,
fractional mode
Typical Power Down Current, 3.3 V 11 15 mA PD_ALL = 1, I3.3V_1 + I3.3V_2
Typical Power Down Current, 5 V Supplies 350 750 μA PD_ALL = 1, IV5_VCO + IV5_CAL + IV5_CP
Typical Disable Current, 3.3 V Supplies 100 1500 μA CE = low, I3.3V_1 + I3.3V_2
Typical Disable Current, 5 V Supplies 350 750 μA CE = low, IV5_VCO + IV5_CAL + IV5_CP
RF OUTPUT NOISE CHARACTERISTICS
12.8 GHz Output Frequency fREF = fPFD = 250 MHz, fractional mode, CP_I
= 15
Phase Noise Floor −160 dBc/Hz
RMS Jitter, 100 Hz to 100 MHz Integration 32 fsRMS
9.001 GHz Output Frequency fREF = fPFD = 250 MHz, fractional mode, CP_I
= 15
Phase Noise Floor −160 dBc/Hz
RMS Jitter, 100 Hz to 100 MHz Integration 29 fsRMS
7.6 GHz Output Frequency fREF = fPFD = 250 MHz, fractional mode, CP_I
= 15
Phase Noise Floor −160 dBc/Hz
RMS Jitter, 100 Hz to 100 MHz Integration 31 fsRMS
6.4 GHz Output Frequency fREF = fPFD = 250 MHz, fractional mode, CP_I
= 15
Phase Noise Floor −161 dBc/Hz
RMS Jitter, 100 Hz to 100 MHz Integration 30 fsRMS
5.025 GHz Output Frequency fREF = fPFD = 250 MHz, fractional mode, CP_I
= 15
Phase Noise Floor −163 dBc/Hz
RMS Jitter, 100 Hz to 100 MHz Integration 33 fsRMS
Normalized In-Band Phase Noise Floor4
LNORM-INT −239 dBc/Hz
LNORM-FRC −237 dBc/Hz
Normalized 1/f Phase Noise Floor4, 5
L1/f5 −287 dBc/Hz Normalized to 1 Hz
L1/f_1G_10k5 −147 dBc/Hz Normalized to 1 GHz at 10 kHz offset
Integer Boundary Spurs (Filtered) IBS −95 dBc Spur is out of the loop bandwidth
Integer Boundary Spurs (Unfiltered) IBS −60 dBc Measured at 5 kHz offset from integer channel
PFD Spur −95 dBc
TEMPERATURE SENSOR (ADC)
ADC Clock Frequency fADC_CLK 400 kHz ADC clock divider output
ADC Clock Divider Frequency fADC_CLKDIV 125 MHz ADC clock divider input
Resolution 8 Bits

1 Based on design and characterization.

2 Valid for 1.60 V ≤ VVTUNE ≤ 2.85 V with device calibrated after a power cycle or software power-on reset.
3 Based on characterization.
4 These numbers are modeled in ADIsimPLL.
5 Integration Range 1 kHz to fOUT.

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Data Sheet ADF4368
SPECIFICATIONS

SERIAL INTERFACE TIMING CHARACTERISTICS

V3.3V_1 = V3.3V_2 = 3.15 V to 3.45 V, VV5_VCO = VV5_CP = VV5_CAL = 4.75 V to 5.25 V, all voltages are with respect to GND, TA = −40°C to +105°C
operating temperature range, unless otherwise noted.

Table 2. Serial Interface Timing Characteristics

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SERIAL INTERFACE (CSB, SCLK, SDIO, SDO) See Figure 2, Figure 3, and Figure 4
SCLK Frequency fSCLK 65 MHz
SCLK Pulse Width High tHIGH 7.6 ns
SCLK Pulse Width Low tLOW 7.6 ns
SDIO Setup Time tDS 3 ns
SDIO Hold Time tDH 3 ns
SCLK Fall Edge to SDIO Valid Prop Delay tACCESS_SDIO 7.6 ns
SCLK Fall Edge to SDO Valid Prop Delay tACCESS_SDO 7.6 ns
CSB Rising Edge to SDIO High-Z tZ 7.6 ns
CSB Falling Edge to SCLK Rise Setup Time tS 3 ns
SCLK Rising Edge to CSB Rise Hold Time tH 3 ns

TIMING DIAGRAMS

Figure 2. Write Timing Diagram

Figure 3. 3-Wire Read Timing Diagram (SDO_ACTIVE = 0)

Figure 4. 4-Wire Read Timing Diagram (SDO_ACTIVE = 1)

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Data Sheet ADF4368
ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. ELECTROSTATIC DISCHARGE (ESD) RATINGS

Table 3. Absolute Maximum Ratings The following ESD information is provided for handling of ESD-sen-
Parameter Rating sitive devices in an ESD protected area only.
V3.3V_1 (V3_LS, V3_LDO, V3_REF, V3_PFD, −0.3 V to +3.6 V Human body model (HBM) per ANSI/ESDA/JEDDEC JS-001.
V3_NDIV) to GND
Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.
V3.3V_2 (V3_VCO, V3_OUTDIV, V3_RFOUT1, −0.3 V to +3.6 V
V3_FOUT2) to GND
ESD Ratings for ADF4368
V5V (V5_CAL, V5_VCO, V5_CP) to GND −0.3 V to +5.5 V
Voltage on CP Pin −0.3 V to V5_CP + 0.3 V Table 5. ESD Ratings for ADF4368
Digital Outputs (MUXOUT, LKDET, SDO, 5 mA ESD Model Withstand Threshold (V) Class
SDIO) HBM 4000 3A
RFOUT1P, RFOUT1N, RFOUT2P, RFOUT2N Maximum (GND − 0.3 V, V3.3V_2 − CDM 1000 C3
1.2 V) to V3.3V_2 + 0.3 V
REFP, REFN −0.65 V to V3.3V_1 + 0.65 V ESD CAUTION
Voltage on all Other Pins −0.3 V to V3.3V_1 + 0.3 V
ESD (electrostatic discharge) sensitive device. Charged devi-
REFP to REFN and SYNCP to SYNCN ±1.35 V
ces and circuit boards can discharge without detection. Although
Temperature this product features patented or proprietary protection circuitry,
Operating Junction Range1 −40°C to +125°C damage may occur on devices subjected to high energy ESD.
Storage Range −65°C to +125°C Therefore, proper ESD precautions should be taken to avoid
Maximum Junction 125°C performance degradation or loss of functionality.
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 30 sec
1 Device is guaranteed to meet the specified performance limits over the full
operating junction temperature range.

Stresses at or above those listed under Absolute Maximum Ratings

may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.
TRANSISTOR COUNT
The transistor count for the ADF4368 is 199076 (CMOS) and 3366
(bipolar).
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to PCB
thermal design is required.
θJA is the natural convection, junction-to-ambient thermal resistance
measured in a one cubic foot sealed enclosure. θJC is the junction-
to-case thermal resistance.
Table 4. Thermal Resistance
θJC-
Package Type θJA θJC-TOP BOTTOM θJB ΨJT ΨJB Unit
CC-48-131 22.38 16.86 5.1 8.33 1.35 7.89 °C/W
1 Test Condition 1: thermal impedance simulated values are based on use of a
4-layer PCB with the thermal impedance paddle soldered to a ground plane.

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Data Sheet ADF4368
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin Number Mnemonic Description
1, 2, 4, 10, 12, GND Negative Power Supply (Ground). These pins must be tied directly to the ground pad.
14, 16, 18, 19,
21, 23, 25, 26,
41, 48
3 V3_NDIV 3.15 V to 3.45 V Positive Power Supply Pin for the PLL Feedback Divider Circuitry. Short this pin to the other pins in 3.3 V power supply
group 1.
5 V3_VCO 3.15 V to 3.45 V Positive Power Supply Pin for the 3.3 V Portion of the VCO Circuitry. Short this pin to the other pins in 3.3 V power supply
group 2.
6 DCLBIAS Do not connect to this pin.
7 VTUNE VCO Tuning Input. This frequency control pin is normally connected to the external loop filter.
8 V5_CAL 4.75 V to 5.25 V Positive Power Supply Pin for VCO Calibration Circuitry. This pin can be shorted to the V5_VCO supply plane.
9 V5_VCO 4.75 V to 5.25 V Positive Power Supply Pin for the 5 V Portion of the VCO Circuitry.
11 V3_OUTDIV 3.15 V to 3.45 V Positive Power Supply Pin for the Output Divider Circuitry. Short this pin to the other pins in 3.3 V power supply group 2.
13 V3_RFOUT2 3.15 V to 3.45 V Positive Power Supply Pin for the RF Output 2 Buffer Circuitry. Short this pin to the other pins in 3.3 V power supply group
2.
15, 17 RFOUT2N, RF Output 2 Signal. The VCO output divider is buffered and presented differentially on these pins. The outputs have 50 Ω (typical) output
RFOUT2P resistance per side (100 Ω differential). The far end of the transmission line is typically terminated with 100 Ω connected across the
outputs. The output amplitude is programmable via the serial port.
20, 22 RFOUT1N, RF Output 1 Signal. The VCO Output Divider is buffered and presented differentially on these pins. The outputs have 50 Ω (typical)
RFOUT1P output resistance per side (100 Ω differential). The far end of the transmission line is typically terminated with 100 Ω connected across the
outputs. The output amplitude is programmable via the serial port.
24 V3_RFOUT1 3.15 V to 3.45 V Positive Power Supply Pin for the RF Output 1 Buffer Circuitry. Short this pin to the other pins in 3.3 V power supply group
2.
27 LKDET PLL Lock Detect. This output presents the lock status of the PLL. PLL is locked when LKDET is a logic high.
28 ENRFOUT2 Enable RF Output 2 Buffer. 3.3 V CMOS input. When ENRFOUT2 = high, the RFOUT2P and RFOUT2N output buffer is active. When
ENRFOUT2 = low, RFOUT2P and RFOUT2N are powered down.
29 ENRFOUT1 Enable RF Output 1 Buffer. 3.3 V CMOS input. When ENRFOUT1 = high, the RFOUT1P and RFOUT1N output buffer is active. When
ENRFOUT2 = low, RFOUT1P and RFOUT1N are powered down.
30 V3_LS 3.15 V to 3.45 V Positive Power Supply Pin for the Internal Level Shift Circuitry. Short this pin to the other pins in 3.3 V power supply group
1.
31 CE Chip-Enable. Does not support 1.8 V CMOS levels. This CMOS input enables the device when driven high. A logic low disables the
device, putting the device in a full power down state causing the register to reset. Conversely, the PD_ALL bit powers down the device, but
does not reset the registers.
32 CSB Serial Port Chip Select. 1.8 V and 3.3 V compatible CMOS input. This CMOS input initiates a serial port communication burst when driven
low, ending the burst when driven back high.
33 SDIO Serial Data Input/Output. 1.8 V and 3.3 V programmable CMOS input/output. When configured as an input, the serial port uses this CMOS
input for data. In 3-wire readback mode (default mode), this pin outputs data from the serial port during a read communication burst.

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Data Sheet ADF4368
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 6. Pin Function Descriptions (Continued)

Pin Number Mnemonic Description
34 SCLK Serial Port Clock. 1.8 V and 3.3 V compatible. This CMOS input clocks serial port input data on its rising edge.
35 SDO Optional Serial Data Output. 1.8 V and 3.3 V programmable CMOS output. In 3-wire mode (default mode), this three-state CMOS pin
remains in a high impedance state. In 4-wire readback mode, this pin presents data from the serial port during a read communication
burst. When the CSB is deasserted, SDO returns to a high impedance. Optionally, attach a resistor of >200 kΩ to prevent a floating output.
36 V3_LDO 3.15 V to 3.45 V Positive Power Supply Pin for the Internal LDO Circuitry. Short this pin to the other pins in 3.3 V power supply group 1.
37 MUXOUT Internal Device Mux Output. This output pin can be connected to multiple internal nodes for factory test and debug purposes.
38, 39 SYNCP, SYNCN Synchronization Input Signals. Both RF output signals are synchronized to an input signal at this pin. It is used for multichip phase
synchronization. This differential input can accept both high and low common mode input signals (based on a SPI bit setting).
40 V3_SYNC 3.15 V to 3.45 V Positive Power Supply for the Synchronization Circuitry. Short this pin to the other pins in 3.3 V power supply group 1.
42, 43 REFP, REFN Reference Input Signal. This differential input is buffered with a delay matched amplifier (DMA) for well controlled reference to output
propagation delays (default mode, REF_SEL = 0). For low slew rate reference input signals, an alternate low noise amplifier (LNA) can
be selected via the serial port (REF_SEL = 1). Reference inputs are self-biased and must be AC-coupled with 1 μF capacitors. Reference
inputs accept differential or single-ended inputs.
44 V3_REF 3.15 V to 3.45 V Positive Power Supply Pin for the PLL Reference Circuitry. Short this pin to the other pins in 3.3 V power supply group 1.
45 V3_PFD 3.15 V to 3.45 V Positive Power Supply Pin for PFD Circuitry. Short this pin to the other pins in 3.3 V power supply group 1.
46 V5_CP 4.75 V to 5.25 V Positive Power Supply Pin for Charge Pump Circuitry. Isolate this pin from the V5_VCO supply plane.
47 CP Charge Pump Output. This bidirectional current output is normally connected to the external loop filter.
Exposed Pad EP Exposed Pad. The LGA has an exposed paddle that must be connected to GND (Negative power supply). The exposed pad must
be soldered directly to the PCB land. The PCB land pattern must have multiple thermal vias to the ground plane for both low ground
inductance and also low thermal resistance.

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Data Sheet ADF4368
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 6. Open Loop VCO Phase Noise vs. Offset Frequency at Various Figure 9. 1 kHz to 100 MHz Integrated Jitter in Integer Mode fPFD = 500 MHz
Frequencies

Figure 10. Close Loop Phase Noise at Various Frequencies

Figure 7. 12 GHz Open Loop VCO Phase Noise vs. Offset Frequency at
Various Temperatures

Figure 11. LNORM-INT vs. Bleed Setting

Figure 8. 1 kHz to 100 MHz Integrated Jitter in Fractional Mode fPFD = 250 MHz

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Data Sheet ADF4368
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 12. L1/f vs. Bleed Setting Figure 15. Worst Case IBS measured at 5 kHz, 50 kHz, 200 kHz, 300 kHz, 400
kHz, 960 kHz, 10 MHz offsets, fPFD = 245.76 MHz

Figure 13. LNORM-FRC, fREF = 500 MHz, fPFD = 250 MHz, RFOut = 12,001 MHz vs.
Bleed Setting Figure 16. PFD Spurs vs. Output Frequency

Figure 14. LNORM-FRC vs. Bleed Setting Figure 17. De-Embedded Single-Ended Output Power at Various Output
Power Settings

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Data Sheet ADF4368
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 18. De-Embedded Single-Ended Output Power vs. Output Frequency Figure 21. LNA Reference Input Sensitivity vs. Temperature
over Temperature and Supply

Figure 22. KVCO vs. VCO Frequency at Various Temperatures

Figure 19. Output Harmonics vs. VCO Frequency

Figure 23. KVCO Sensitivity Percentage vs. VCO Frequency at Various

Figure 20. Minimum Input Signal for REF_OK = 1 for DMA Buffer Temperatures

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 24. VTUNE vs. Output Frequency when Part Locked at 25°C Figure 27. Propagation Delay vs. Bleed Setting

Figure 25. Skew Between Outputs Figure 28. Phase Shift vs. Phase Adjustment, RFOut = 12,775 MHz at Various
Temperatures

Figure 26. Propagation Delay

Figure 29. Phase Shift vs. Phase Adjustment at Various Frequencies

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Figure 30. Output Power When Buffer Is Powered Down (PD_CLKOUTx = 1)

Figure 31. VCO Current vs. VCO Frequency

Figure 32. Differential Output at 3 GHz

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Data Sheet ADF4368
THEORY OF OPERATION

INTRODUCTION
A PLL is a complex feedback system that may conceptually be
considered a frequency multiplier. The system multiplies the fre-
quency input at REFP and REFN and outputs a higher frequency
at RFOUT1P, RFOUT2P, RFOUT1N, and RFOUT2N. The PFD,
charge pump, output divider, feedback divider, VCO, and external
loop filter forms a feedback loop to accurately control the output
frequency (see Figure 33). The reference divider or reference
doubler is used to set the frequency resolution.

Figure 34. Reference Input Stage

A high quality signal must be applied to the REFP and REFN inputs
because they provide the frequency reference to the entire PLL. To
achieve the in-band phase noise performance of the device, apply
a continuous wave signal or a square wave with a slew rate of
at least 1000 V/µs. For more information on reference input signal
Figure 33. PLL Loop Diagram requirements and interfacing, see the Applications Information sec-
tion.
OUTPUT FREQUENCY
When the REF_SEL bit is set to 0, the DMA buffer is selected. The
When the loop is locked, the fVCO (in Hz) produced at the output of DMA is optimized for high slew rate signals, such as square waves
the VCO is determined by the reference frequency (fREF) and the O, or higher frequency and higher amplitude sine waves. The DMA
R, and N values given by the following equation. has a controlled propagation delay from the reference input to clock
D×N×O output, which eases time zero and over temperature multichip clock
fVCO = fREF × R (1) alignment.
Where N is given by: When the REF_SEL bit is set to 1, the LNA is selected. The LNA
is optimized for low slew rate signals, such as lower frequency or
FRAC1WORD + FRAC2WORD
N = NINT + MOD2WORD (2) lower amplitude sine waves.
MOD1WORD
The REF_SEL bit must be set correctly to optimize the in-band
Here, the PFD frequency (fPFD) produced is given by: phase noise performance and propagation delay. For recommend-
fREF × D ed settings, see Table 7.
fPFD = R
(3)
Table 7. REF_SEL Programming
fVCO may be alternatively expressed as: REF_SEL Sine Wave Slew Rate (V/µs) Square Wave Optimized tPD
fVCO = fPFD × N × O (4) 0 ≥1000 Preferred Yes
1 <1000 Not applicable Not applicable
The output frequency, fRFOUT, produced at the output of the output
divider is given by: To calculate the slew rate of sine wave:

fRFOUT =
fVCO
(5) Slew Rate = 2 × π × f × V (6)
O
Where:
CIRCUIT DESCRIPTION
f = sine wave frequency
Reference Input Buffer V = sine wave amplitude (in VPK)
The reference frequency of the PLL is applied differentially on the The FILT_REF bit controls the low-pass filter of the reference input
REFP and REFN pin. These high impedance inputs are self-biased LNA and must be set for sine wave signals based on fREF to limit
and must be AC-coupled with 1 µF capacitors (for a simplified the wideband noise of the reference. The FILT_REF bit must be set
schematic, see Figure 34). Alternatively, the inputs may be used correctly to reach the LNORM normalized in-band phase noise floor.
as single-ended by applying the reference frequency at REFP and For recommended settings, see Table 8. Square wave inputs have
bypassing REFN to GND with a 1 µF capacitor. FILT_REF set to 0.

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Data Sheet ADF4368
THEORY OF OPERATION

Table 8. FILT_REF Programming

FILT_REF Sine Wave fREF Square Wave fREF
0 ≥ 20 MHz All fREF
1 < 20 MHz Not applicable

The BST_REF bit must be set based on the input signal level
to prevent the LNA reference input buffer from saturating. The
BST_REF programming is the same whether the input is a sine
wave or a square wave. For recommended settings, see Table 9
and for programming examples, see the Applications Information
section.
Table 9. BST_REF Programming Figure 35. Simplified PFD Schematic
BST_REF Sine Wave fREF
Charge Pump
0 ≥ 1.6 VPP
1 < 1.6 VPP The charge pump, controlled by the PFD, forces sink (down) or
source (up) current pulses onto the CP pin, which must be connect-
Reference Peak Detector ed to an appropriate loop filter. For a simplified schematic of the
charge pump, see Figure 36.
A reference input peak detection circuit is provided on the REFP
and REFN inputs to detect the presence of a reference signal and
provides the REF_OK status flag available through serial port regis-
ter REG0058. The circuit has hysteresis to prevent the REF_OK
flag from chattering at the detection threshold.
The peak detector approximates an RMS detector. Therefore, sine
and square wave inputs give different detection thresholds by a
factor of 4/π. For REF_OK detection values, see Table 10.
Table 10. REF_OK Status Output vs. REF INPUT
Figure 36. Simplified Charge Pump Schematic
REF_OK Sine Wave fREF Square Wave fREF
1 ≥ 200 mVPP ≥ 155 mVPP The output current magnitude (ICP) may be set from 0.79 mA
0 < 180 mVPP < 140 mVPP to 11.1 mA using the CP_I bits found in REG001F. A larger ICP
can result in lower in-band noise due to the lower impedance of
Reference Divider (R) and Doubler (D) the loop filter components, and a smaller ICP can result in better
spurious performance. For programming specifics, see Table 11,
When the EN_RDBLR bit is set to 1, a frequency multiplier is and for information on designing a loop filter, see the Applications
used to double the frequency driven to the reference divider. A Information section.
6-bit divider, R_DIV, in series with the reference doubler is used
Table 11. CP Programming
to reduce the frequency seen at the PFD. The reference divide
ratio, R, may be set to any integer from 1 to 63. Use the R_DIV CP_I ICP
bits found in REG0020 to directly program the R divide ratio. For 0 0.79 mA
the relationship between R, D, and the fREF, fPFD, fVCO, and fOUT 1 0.99 mA
frequencies, see the Output Frequency section. 2 1.19 mA
3 1.38 mA
Phase/Frequency Detector (PFD) 4 1.59 mA
The phase/frequency detector (PFD), with the charge pump, pro- 5 1.98 mA
duces source and sink current pulses proportional to the phase 6 2.39 mA
difference between the outputs of the reference divider or reference 7 2.79 mA
doubler and the feedback divider. This action provides the necessa- 8 3.18 mA
ry feedback to phase lock the loop, forcing a phase alignment at 9 3.97 mA
the inputs of the PFD. For a simplified schematic of the PFD, see 10 4.77 mA
Figure 35. 11 5.57 mA
12 6.33 mA

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Table 11. CP Programming (Continued) Table 13. tBLEED and BLEED_POL for fPFD <120 MHz
CP_I ICP N ≥ 35 N < 35
13 7.91 mA BLEED_ BLEED_
14 9.51 mA RF Frequency tBLEED POL tBLEED POL
15 11.1 mA fRFOUT ≥ 4.2 GHz 390 ps 0 390 ps 0
3.0 GHz ≤ fRFOUT < 4.2 1200 ps 1 900 ps 0
Charge Pump Functions GHz
1.8 GHz ≤ fRFOUT < 3.0 1200 ps 0 1200 ps 1
When the EN_CPTEST bit is set to 1, the CP_UP bit and GHz
CP_DOWN bit can be programmed to force a constant ICP source 1.2 GHz ≤ fRFOUT < 1.8 1400 ps 0 1400 ps 1
or sink current, respectively, on the CP pin. EN_CPTEST or CP_UP GHz
and CP_DOWN must be set to 0 to allow the loop to lock. These fRFOUT < 1.2 GHz 1400 ps 0 2000 ps 1
bits are commonly used as an aid to debug PLL related issues
during the hardware and software development phase of a project. Bleed current also changes the propagation delay from the REFP
For normal operation, set EN_CPTEST, CP_UP, and CP_DOWN to and REFN input pins to the RFOUTxP and RFOUTxN output pins.
0. In integer mode, bleed current can be used to shift the output in
both directions. If BLEED_POL = 0, the propagation delay from the
Charge Pump Bleed Current Optimization REFP and REFN input pins to the RFOUTxP and RFOUTxN output
pins increases.
A small programmable constant charge pump current, known as
bleed current (IBLEED), can be used to optimize the phase noise and In fractional mode, after setting the bleed current for the best per-
fractional spurious signals in fractional mode. To enable the bleed formance, the output can be shifted by using the PHASE_ADJUST-
current, set the EN_BLEED bit to 1. When the BLEED_POL bit is MENT bits in REG0024, which are effectively used in sigma-delta
set to 1, a small constant source current is forced onto the CP pin. modulator (SDM). Phase adjustment does not cause any phase
When the BLEED_POL bit is set to 0, a small constant sink current noise degradation.
is forced from the CP pin.
Lock Detector
The 13-bits bleed current setting consists of 4-bit MSB for coarse
setting and 9-bit LSB for fine setting. The coarse step is 180 µA and The lock detector uses internal signals from the PFD to measure
the fine setting step is 490 nA. phase coincidence between RCLK and NCLK. It is enabled by
setting both the EN_LOL bit and EN_LDWIN bit to 1 in REG002D
The optimized bleed current value for fractional mode is calculated and presents the lock detector output on the LKDET pin and the
based on the charge pump current (ICP), fPFD, and bleed delay LOCKED bit in REG0058. The lock detector output can also be
(tBLEED). The recommended tBLEED and BLEED_POL are shown in presented on the MUXOUT pin by programming the MUXOUT bits
Table 12 and Table 13. in REG002E.
Table 12. tBLEED and BLEED_POL for fPFD ≥ 120 MHz
The PFD phase difference must be less than the phase difference
Output Frequency tBLEED BLEED_POL lock window time (tLDWIN) for a set number of PFD cycles before
fRFOUT ≥ 4.2 GHz 390 ps 0 the lock detector output indicates that the PLL has locked. The
3.0 GHz ≤ fRFOUT < 4.2 GHz 900 ps 0 user sets the tLDWIN for a valid lock condition with the LDWIN_PW
1.8 GHz ≤ fRFOUT < 3.0 GHz 1200 ps 0 bits depending on the operation mode, fPFD, and fRFOUT. The
fRFOUT < 1.8 GHz 1400 ps 0 recommended settings for the LDWIN_PW bits are given in Table
14.
The bleed current and BLEED_I bit are calculated by the following
Table 14. LDWIN_PW Programming
equations:
LDWIN_PW Configuration
IBLEED = TBLEED × fPFD × ICP (7)
0 Integer PLL, tBLEED ≤ 85 ps
IBLEED 1 Integer PLL, 85 ps > tBLEED < 250 ps
CoarseBleed = INT 180μ
(8)
10 Fractional PLL, fPFD > 200 MHz and RF > 6.4 GHz
FineBleed = Round 512 × 11 Fractional PLL, fPFD > 200 MHz and RF > 5 GHz
IBLEED − 180μ × CoarseBleed
(9) 100 Fractional PLL, fPFD < 200 MHz
250μ 101 Fractional PLL, fPFD < 100 MHz
110 Fractional PLL, fPFD < 50 MHz
BLEED_I = 512 × CoarseBleed + FineBleed (10)
111 Fractional PLL, fPFD < 40 MHz

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Data Sheet ADF4368
THEORY OF OPERATION

The desired number of PFD cycles varies if a designer prioritizes

lock detect accuracy or speed. Five loop filter time constants can
be used as an initial estimate of the desired number of PFD cycles,
as shown in Equation 11. The desired number of PFD cycles is set
by the LD_COUNT bits in REG002C as with and the formula shown
in the Register Details section. The user sets the LD_COUNT such
that actual PFDcycles is greater than desired PFD cycles. For more
details, see Figure 37 and Table 16.
5
Desired PFD Cycles = 2 × π × LPBW (11) Figure 37. Lock Detector Timing, Bleed Current Disabled

Where LPBW is loop filter bandwidth. Table 16. Lock Detector Timing, Bleed Current Disabled
Absolute Phase Difference at
Table 15. LD_COUNT Programming
Region PFD Lock Detector State
LD_COUNT Actual PFD Cycles
1 > tLDWIN Low
0 27
2 < tLDWIN Low, counts PFD cycles
1 35
3 ~0
2 51
4 ~0 High, > desired PFD cycle count
3 67
5 < tLDWIN High
4 99
6 > tLDWIN Low (immediately)
5 131
6 195 When the charge pump bleed current is enabled, a phase offset is
7 259 applied to the PFD inputs. This phase offset (tIDEL) is proportional
8 387 to the amount of bleed current. Region 3 and Region 4 in Figure
9 515 37 and Figure 38 highlight the PFD phase difference that the
10 771 PLL settles to when the charge pump bleed current is disabled or
11 1027
enabled, respectively.
12 1539
13 2051
14 3075
15 4099
16 6147
17 8195
18 12291
19 16387
20 24579 Figure 38. Lock Detector Timing, Bleed Current Enabled
21 32771
22 49155 VCO
23 65539 The VCO core consists of four separate VCOs, each of which
24 98307 uses 256 overlapping bands, which allows the device to cover a
25 131075 wide frequency range without large VCO sensitivity (KV). The output
26 196611 frequency can be further extended by using the output divider.
27 262147
28 393219
29 524291
30 786435
31 1048579

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Data Sheet ADF4368
THEORY OF OPERATION

2. Calculate and set the minimum values for

the SYNTH_LOCK_TIMEOUT bit fields, Bits[14:0],
the VCO_ALC_TIMEOUT bit fields, Bits[14:0], and
VCO_BAND_DIV bits. Typical automatic VCO calibration times
are 3 ms to 9 ms when minimum values are chosen for these
parameters. Larger values produce longer VCO calibration
times.
SYNTH_LOCK_TIMEOUT ≥ Ceiling
(12)
200μs × fDIV_RCLK
Figure 39. VCO and Clock Output Divider VCO_ALC_TIMEOUT ≥ Ceiling
(13)
50μs × fDIV_RCLK
The correct register values for the VCO_CORE, VCO_BAND, and
VCO_BIAS settings are determined by performing a VCO calibra- VCO_BAND_DIV ≥ Ceiling
tion. After a VCO calibration is performed for a specific device and 15μs × fDIV_RCLK (14)
frequency, the VCO_CORE, VCO_BAND, and VCO_BIAS values 16 × 2DCLK_MODE
can be recorded. These recorded values may be programmed 3. Ensure that the ADC_CLK_DIV bits are set so that the desired
manually on subsequent power ups when the same device and ADC clock frequency is <400 kHz:
frequency are used, thereby avoiding the VCO calibration time.
ADC_CLK_DIV > Ceiling
fDIV_RCLK
VCO Calibration 400kHz − 2 (15)
4
A VCO calibration is required to select the correct VCO core, band,
and bias settings for a specific VCO frequency. This procedure
assumes that the device is powered up, the desired reference 4. Set the N_INT, CLKOUT_DIV bits, R_DIV bits, and the
frequency is present on the REFP and REFN pins, and all other EN_RDBLR bit by programming REG0010 last. Any write to
registers are programmed correctly. Figure 40 and Figure 41 show REG0010 starts the VCO autocalibration.
the visual aids for this procedure. 5. Monitor the ADC_BUSY bit and FSM_BUSY bit. The calibration
is finished when ADC_BUSY transitions from high to low, fol-
lowed with FSM_BUSY transitioning from high to low.
6. After the VCO calibration is complete, disable the calibra-
tion clocks to limit unwanted spurious content by setting
EN_DRCLK = EN_DNCLK = EN_ADC_CLK = 0.
7. This is an optional step. Read back and record the VCO_CORE
bits, VCO_BAND bits, and VCO_BIAS bits. These values can
be used to bypass calibration and manually program the
Figure 40. VCO Calibration Dividers M_VCO_CORE bits, M_VCO_BAND bits, and M_VCO_BIAS
bits for a given device and frequency.
Table 17. DCLK_DIV1 and DCLK_MODE Setup
fPFD (MHz) DCLK_DIV1 DCLK_MODE fDIV_RCLK (MHz)
≤160 0 1 fPFD/2
>160 and ≤320 1 1 fPFD/4
>320 2 1 fPFD/8

Clock Output Divider

Figure 41. VCO Calibration Block

A 2-bit divider, CLKOUT_DIV, is used to reduce the frequency seen
at the output buffer and feedback divider. Its divide ratio, O, may be
To perform a VCO calibration, set up several registers as outlined in set to 1, 2, 4, or 8. Use the CLKOUT_DIV bits found in REG0011 to
the following procedure: directly program the O divide ratio. CLKOUT_DIV is located inside
the PLL loop. Therefore, any change to CLKOUT_DIV results in the
1. Set DCLK_DIV1, , and DCLK_MODE to the values in Table 17. PLL losing lock for few loop time constants.
Record fDIV_RCLK for later use.

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THEORY OF OPERATION

Output Invert (INV_CLKOUT) is recommended. For more details on the evaluation board sche-
matic, refer to the EVAL-ADF4368 user guide.
The output invert (INV_CLKOUT) is used to shift the output signal
180°. INV_CLKOUT is located inside the PLL loop. Any change
to INV_CLKOUT results in the PLL losing lock for few loop time
constants. Use the INV_CLKOUT bit found in register REG0011 to
directly program the output phase.

Feedback Divider (N)

The feedback divider allows a division ratio in the PLL feed-
back path. Determine the division ratio by the N_INT bit fields,
Bits[11:0] (REG0011 and REG0010), the FRAC1WORD bit fields,
Bits[24:0] (REG0015, REG0014, REG0013, and REG0012), the
FRAC2WORD bit fields, Bits[23:0] (REG0019, REG0018, and
REG0017), and the MOD2WORD bit fields, Bits[23:0] (REG001C,
REG001B, and REG001A) values that this divider comprises to-
gether with the fixed modulus MOD1WORD, which is equal to 225.
The 24-bit variable MOD2WORD and the 25-bit fixed MOD1WORD
forms a 49-bit combined fractional modulus. For the relationship be-
tween the N_INT bit fields, Bits[11:0], the FRAC1WORD bit fields,
Bits[24:0], MOD1WORD, the FRAC2WORD bit fields, Bits[23:0],
the MOD2WORD bit fields, Bits[23:0], and the CLKOUT_DIV bits,
together with R, D, and the fREF, fPFD, fVCO, and fOUT frequencies,
see the Output Frequency section.

RF Output Buffer

Figure 42. Simplified RF Output Buffer Schematic

The low noise, differential output buffer in Figure 42 a differential

output voltage. The output amplitude level and common mode volt-
age are settable with the CLK1_OPWR bits and the CLK2_OPWR
bits. Each output can be either AC-coupled or DC-coupled and
terminated with 100 Ω differentially. If a single-ended output is
desired, each side of the output must be individually AC-coupled
and terminated with 50 Ω.
The lowest four CLKx_OPWR settings can be used without any
external pull-up inductor. External inductors are required to achieve
the higher output power. A 3.4 nH 0302 package or smaller inductor

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Data Sheet ADF4368
APPLICATIONS INFORMATION

LOOP FILTER DESIGN

A stable loop filter design requires care in selecting the loop filter
components of the ADF4368. It is recommended to download
and install ADIsimPLL™ for loop filter design and simulation. ADI-
simPLL™ has an integrated tutorial for first time users and a help
manual for more complex topics. There are also several ADIsimPLL
training videos available on www.analog.com. After a loop filter is
designed and simulated, it is recommended to verify the new loop
filter using the ADF4368 evaluation hardware. Figure 43. Single-Ended 50 Ω Source (VREF < 2.6 V p-p)
A full loop filter design tutorial is beyond the scope of this data
sheet. However, some best practices are shown in the following
lists. ADIsimPLL aids in defining and simulating these parameters.
Any significant change to these items requires a new loop filter
design.
A stable loop filter must meet the following criteria:
► Loop filter phase margin > 45°
► Loop filter bandwidth < fPFD ÷ 10
Figure 44. Single-Ended 50 Ω Source (VREF > 2.6 V p-p)
The desired loop filter bandwidth is determined by the following
features of the ADF4368:
► ICP
► KVCO
► PFD frequency
► Reference input phase noise (see the Reference Phase Noise
section)
► Trade-off between minimizing jitter or settling time (see the
Output Phase Noise Characteristics section and Equation 12,
respectively)
Figure 45. Single-Ended CMOS
The VTUNE pin has an internal 30 pf capacitor to GND that must
be included in the loop filter design. ADIsimPLL™ takes this internal
capacitance into account automatically.
REFERENCE SOURCE CONSIDERATIONS

Reference Input Network

The reference input buffer of the ADF4368, shown in Figure 34,
provides a flexible interface to either differential or single-ended
Figure 46. Differential LVPECL
frequency sources. Figure 43 to Figure 48 show recommended
interfaces for different reference signal types. All Z0 signal traces
are 50 Ω transmission lines in Figure 43, Figure 44, Figure 45,
Figure 46, Figure 47, and Figure 48.

Figure 47. Differential LVDS

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APPLICATIONS INFORMATION

500 MHz for integer mode, see Figure 49. The total phase noise is
the summation of LOUT and LOUT(1/f), calculated by Equation 20.
LOUT /10
LOUT TOTAL = 10 × log10 10
LOUT 1/f /10
(20)
+ 10

Figure 48. Differential CML

Reference Phase Noise

The ADF4368 achieves an in-band normalized phase noise floor of
LNORM = −239 dBc/Hz in integer mode and LNORM = −237 dBc/Hz
typical in fractional mode. To calculate the equivalent input phase
noise floor (LIN), use the following Equation 16.
LIN = LNORM + 10 × log10 fREF (16)
For example, a 100 MHz reference input frequency gives an LIN of
−157 dBc/Hz in fractional mode. The phase noise of the reference
frequency source must be at least 6 dB less than LIN to avoid
impacting and increasing the overall system phase noise.
Figure 49. Theoretical In-Band Phase Noise, fOUT = 10 GHz
To maintain typical LNORM performance, Table 7 provides criteria
for selecting the optimal REF_SEL setting based on the input POWER-UP AND INITIALIZATION SEQUENCE
reference signal type and amplitude.
OUTPUT PHASE NOISE CHARACTERISTICS

In-Band Output Phase Noise

The in-band phase noise floor (LOUT) produced at fOUT can be
calculated by Equation 17 and Equation 18.

LOUT = LNORM + 10 × log10 fPFD + 20 × log10

fOUT
(17)
fPFD

Or
LOUT = LNORM + 10 × log10 fPFD + 20 × log10
(18) Figure 50. Power-Up and Initialization Sequence
N
O
The following steps describe the recommended power-up and initi-
Output Phase Noise Due to 1/f Noise alization sequence of the ADF4368:

In-band phase noise at very low offset frequencies can be influ- 1. Apply specified voltages to the 5V, 3.3V_1, and 3.3V_2 power
enced by the 1/f noise of the ADF4368, depending on the fPFD. Use supply groups. The ADF4368 is in full power-down mode at this
the normalized in-band 1/f noise (L1/f) of −287 dBc/Hz with Equation point and SPI programming is not possible.
19 to approximate the output 1/f phase noise at a given frequency 2. Set the CE pin to a logic high. It is acceptable to connect the
offset (fOFFSET). CE pin to the V3_LDO pin via a pull-up resistor. Therefore, Step
1 and Step 2 are performed coincidentally.
LOUT 1/f = L1/f + 20 × log10 fOUT − 10 3. After waiting ≥200 μs for all SPI register bits to settle to their
(19)
× log10 fOFFSET power-on reset state (POR), begin programming the SPI to
configure the ADF4368 to a desired state. The following is the
Unlike the in-band noise floor (LOUT), the 1/f noise (LOUT(1/f)) does recommended SPI programming sequence:
not change with fPFD and is not constant over offset frequency. For
an example of in-band phase noise for fPFD equal to 100 MHz and

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Data Sheet ADF4368
APPLICATIONS INFORMATION

a. Set the SDO_ACTIVE and CMOS_OV bits to a desired 4. The PLL is locked when the lock detector sets the LKDET pin
state for future readback operations. and the LOCKED bit high.
b. Program all register addresses in descending order, 5. When changing the frequency, do the following steps:
REG0053 to REG0010. There are several required re-
served register field settings provided in Table 19 that are a. Program only the modified registers in the descending or-
required for proper device operation. der.
4. The ADF4368 remains in power-down mode until the PD_ALL b. Write REG0010 to start a new VCO autocalibration as the
bit is programmed to 0. After PD_ALL is disabled, wait at least final step whether it is modified or not.
10 μs for the VCO calibration circuitry and other circuit blocks to
settle before starting a VCO calibration. Fast Power-Up and Initialization, Manually
5. A write to REG0010 starts a VCO autocalibration. At this point, Programmed VCO Calibration Settings
the device is fully operational and new frequencies can be (Optional)
programmed as often as desired. The following steps are infor- The purpose of the fast power-up and initialization method is to
mation for PD_ALL and CE pin. avoid the automatic VCO calibration time, which is typically 3 ms
6. Setting PD_ALL to 1 power down the ADF4368, retaining the to 9 ms. For fixed clock frequency converter applications, automatic
latest programmed SPI settings and full SPI programming capa- VCO calibration times are typically acceptable. For fast frequency
bility. hopping applications, much shorter lock time is needed.
7. If only the state of PD_ALL was modified in Step 6, setting
PD_ALL to 0 returns the ADF4368 to the frequency program- The following list provides the steps to record the VCO calibration
med in Step 5. After a 10 μs wait, all circuit blocks are results on the initial power-up and then to manually program VCO
completely powered up internally. This 10 μs wait does not calibration settings on subsequent power ups:
include the frequency settling time associated with the loop filter 1. On initial power up, follow the procedure in the Standard Pow-
bandwidth. er-Up and Initialization Sequence, Automatic VCO Calibration
8. Toggling the CE pin level causes the ADF4368 to return to section.
full power-down mode and return the SPI registers to the POR 2. Record calibration results from the VCO_CORE, VCO_BAND,
state (see Step 2 and Step 3). and VCO_BIAS bit fields for each target frequency and store
the recorded results in memory. Note that each unique device
Programming Procedure and frequency combination generates different VCO_CORE,
VCO_BAND, and VCO_BIAS values.
There are two different methods to power up the ADF4368. The
most commonly used method provided in the Standard Power-Up 3. Subsequent power-up and initialization sequences (see the
and Initialization Sequence, Automatic VCO Calibration section is Power-Up and Initialization Sequence section) can bypass the
mandatory on the initial device power-up. automatic VCO calibration procedure by programming the over-
ride (O_VCO_CORE, O_VCO_BAND, and O_VCO_BIAS) and
The method provided in the Fast Power-Up and Initialization, Man- manual (M_VCO_CORE, M_VCO_BAND, and M_VCO_BIAS)
ually Programmed VCO Calibration Settings (Optional) section is an VCO bits with the register settings provided in Table 18. All
optional power-up procedure after the initial power-up. other bit fields are programmed as usual.
4. When changing the frequency, program only the modified regis-
Standard Power-Up and Initialization ters in descending order.
Sequence, Automatic VCO Calibration
Table 18. Manually Programmed VCO Calibration Settings
The following standard power-up and initialization sequence is the Bit Fields Value
recommended procedure to power up and program the ADF4368: EN_AUTOCAL 0x0
1. Follow Step 1 through Step 5 in the Power-Up and Initialization EN_DRCLK 0x0
Sequence section. EN_DNCLK 0x0
2. It is optional to monitor the status of the VCO calibration bits, EN_ADC_CLK 0x0
ADC_BUSY and FSM_BUSY. A VCO calibration is completed O_VCO_CORE 0x1
when ADC_BUSY transitions from high to low, followed by O_VCO_BAND 0x1
FSM_BUSY transitioning from high to low. Typical automatic O_VCO_BIAS 0x1
VCO calibration times range from 3 ms to 9 ms. M_VCO_CORE Program with recorded values
3. After the VCO calibration is complete, disable the VCO M_VCO_BAND Program with recorded values
calibration clocks by setting EN_DRCLK = EN_DNCLK = M_VCO_BIAS Program with recorded values
EN_ADC_CLK = 0. Disabling the VCO calibration clocks re-
duces unwanted spurious content.
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Data Sheet ADF4368
APPLICATIONS INFORMATION

Synchronizing Multiple ADF4368 Output Phase Resynchronization

Phases
In frequency hopping systems, another challenge is resynchroniz-
Multiple ADF4368 can be synchronized in two ways, timed sync ing the multiple devices after changing frequency. This causes
method through the SYNC pin and EZSync method through SPI a dead time in operation and also causes process load on the
programming, which eliminates the need for distributing the SYNC controller.
signal to all ADF4368 devices. The following sequence is the procedure for the Phase ReSync
The ADF4368 also supports a unique feature called phase resync. method:
After multiple devices are synchronized, any additional resyncing 1. Power up all ADF4368 devices
(for example, after a frequency change) is not needed because of
the phase resync feature of the device. When the phase resync 2. Program all ADF4368 devices to the same frequency
mode is enabled, the outputs are automatically synchronized when 3. Perform an initial synchronization (timed synchronization or
changing frequency (as long as R_DIV bits is unchanged). EZSync)
4. Enable phase resynchronization mode and perform the syn-
The synchronization relies on setting the output phase of the chronization once more
ADF4368 to a known phase relative to its reference input. There-
fore, any phase difference in the reference inputs of multiple From this point on, any frequency changes are automatically
ADF4368 devices is directly reflected to the output. This residual synchronized. No additional synchronization request is needed. The
phase difference can be compensated by using the phase adjust timing of this SPI command to change frequency is not critical.
feature. Therefore, the user can change the frequency of multiple devices at
different times.
Timed Synchronization Method When Phase ReSync method is enabled, the value of the
The traditional method by using the SYNC pin. A rising edge on the FRAC2WORD and MOD2WORD should be less than 217 (they
SYNC pin triggers the synchronization process and puts the device should be considered as 17 bit).
into a reset state. Then, with a falling edge on the SYNC pin, the
synchronization process starts. The output phase is aligned to a Phase Shift
known phase with respect to the reference input. The output phase of the ADF4368 can be shifted by the following
This method is straightforward, but requires an additional well two methods:
aligned synchronization signal. ► Shifting the phase on SDM block
► Bleed current
EZSync Method
The first method requires the SDM to be enabled and has a
The EZSync method is useful when synchronizing a huge number
very high accuracy and very fine step size, which makes it very
of ADF4368 devices, such as massive multiple-input multiple-output
useful when the device is in fractional mode. The amount of phase
(MIMO) or phase array applications. This method eliminates the
adjust is set by the PHASE_ADJUSTMENT bits (REG0024) and the
need for an additional synchronization signal.
output is shifted with this amount every time when PHASE_ADJ
The main concept of the EZSync method is sending a synchroniza- (REG001F) is written.
tion request through the SPI by writing to the SW_SYNC bit instead
When the ADF4368 is in integer mode, because SDM is disabled,
of the SYNC pin. The problems with sending the request over the
this method does not work. Bleed current can be used to shift in this
SPI are that the SPI is a very slow protocol and does not have any
mode (see the Charge Pump Bleed Current Optimization section).
time accuracy. Sending the request in the same reference period is
In fractional mode, bleed current is mainly used for phase noise and
also another challenge and even impossible for a huge number of
spur optimization.
ADF4368 devices used.
It is possible to enable the SDM and shift the output by using the
These problems are solved easily by stopping and starting the
first method. Note that this puts the device into fractional mode
reference signals so that they leave enough setup and hold time
although the output is an integer multiple of fPFD.
for sending the request over the SPI. The reference signals must
stop and start very accurately and without any glitch or without any
runt pulse. The clock generation/distribution devices from Analog
Devices, such as the LTC6953 or LTC6954, are recommended
when using EZSync.

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Data Sheet ADF4368
APPLICATIONS INFORMATION

POWER SUPPLY AND BYPASSING

The ADF4368 is a high performance, low noise device. Phase
noise and spurious performance may be degraded by noisy power
supplies. To achieve maximum performance and ensure that power
supply noise does not degrade the performance of the ADF4368,
it is recommended to use the Analog Devices low noise, high pow-
er supply rejection ratio (PSRR) regulators. Preferred regulators
include the LT3045, ADM7150, and the ADM7151. Additional exter-
nal supply bypass capacitors are also recommended. For more
details, refer to the EVAL-ADF4368 evaluation board design.

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Data Sheet ADF4368
REGISTER MAPS

The reset column refers to the initial register state on power up or after the SOFT_RESET bit is toggled. The bit columns provide bit names
or the required programmed state of write-able reserved registers for proper device operation. Register bit fields labeled RESERVED are read
only.
Table 19. ADF4368 Register Summary
Reg Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x00 SOFT_RESET_R LSB_FIRST_R ADDRESS_ASCE SDO_ACTIV SDO_ACTIV ADDRESS LSB_FIRS SOFT_RESET 0x00 R/W
NSION_R E_R E _ASCENSI T
ON
0x01 SINGLE_INSTRUCT REG01_RSV6 MAIN_READBACK REG01_RSV RESERVED REG01_RS REG01_R RESERVED 0x00 R/W
ION _CONTROL 4 V1 SV0
0x02 RESERVED CHIP_STATUS 0x00 R
0x03 RESERVED CHIP_TYPE 0x00 R
0x04 PRODUCT_ID[7:0] 0x00 R
0x05 PRODUCT_ID[15:8] 0x00 R
0x06 PRODUCT_GRADE DEVICE_REVISION 0x00 R
0x0A SCRATCHPAD 0x00 R/W
0x0B SPI_REVISION 0x00 R
0x0C VENDOR_ID[7:0] 0x56 R
0x0D VENDOR_ID[15:8] 0x04 R
0x0F RESERVED 0 0x00 R/W
0x10 N_INT[7:0] 0x80 R/W
0x11 CLKOUT_DIV INT_MODE INV_CLKOUT N_INT[11:8] 0x00 R/W
0x12 FRAC1WORD[7:0] 0x00 R/W
0x13 FRAC1WORD[15:8] 0x00 R/W
0x14 FRAC1WORD[23:16] 0x00 R/W
CMOS_O
0x15 M_VCO_CORE M_VCO_BIAS V FRAC1WORD[24] 0x00 R/W
0x16 M_VCO_BAND 0x00 R/W
0x17 FRAC2WORD[7:0] 0x00 R/W
0x18 FRAC2WORD[15:8] 0x00 R/W
0x19 FRAC2WORD[23:16] 0x00 R/W
0x1A MOD2WORD[7:0] 0x00 R/W
0x1B MOD2WORD[15:8] 0x00 R/W
0x1C MOD2WORD[23:16] 0x00 R/W
0x1D BLEED_I[7:0] 0x00 R/W
EN_PHASE_RESY
0x1E NC EN_REF_RST TIMED_SYNC BLEED_I[12:8] 0x00 R/W
0x1F SW_SYNC PHASE_ADJ BLEED_POL EN_BLEED CP_I 0x00 R/W
0x20 EN_AUTOCAL EN_RDBLR R_DIV 0x01 R/W
0x21 PHASE_WORD[7:0] 0x00 R/W
0x22 PHASE_WORD[15:8] 0x00 R/W
0x23 PHASE_WORD[23:16] 0x00 R/W
0x24 PHASE_ADJUSTMENT 0x00 R/W
0x25 RESYNC_WAIT[7:0] 0x00 R/W
0x26 RESYNC_WAIT[15:8] 0x00 R/W
0x27 RESYNC_WAIT[23:16] 0x00 R/W
0x28 0 LSB_P1 VAR_MOD_EN 0 0 0 0 0 0x00 R/W
0x29 CLK2_OPWR CLK1_OPWR 0x00 R/W
PHASE_ADJ_PO
0x2A 0 L 0 PD_SYNC 0 PD_RDET 0 0 0x04 R/W

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Data Sheet ADF4368
REGISTER MAPS

Table 19. ADF4368 Register Summary (Continued)

Reg Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
PD_CLKO
0x2B PD_ALL 0 0 0 PD_LD 0 UT1 PD_CLKOUT2 0x83 R/W
0x2C LDWIN_PW LD_COUNT 0x00 R/W
0x2D EN_DNCLK EN_DRCLK EN_LOL EN_LDWIN 0 RST_LD 0 1 0x00 R/W
EN_CPTE CP_DOW
0x2E MUXOUT 0 ST N CP_UP 0x00 R/W
0x2F BST_REF FILT_REF REF_SEL 0 0 1 1 1 0x00 R/W
0x30 MUTE_NCLK 0 DRCLK_DEL DNCLK_DEL 0x00 R/W
EN_ADC_CL
0x31 SYNC_DEL RST_SYS K 0 0 1 0x00 R/W
0x32 1 1 0 1 0 0 1 1 0x00 R/W
0x33 0 0 1 1 0 0 1 0 0x00 R/W
0x34 1 0 0 1 1 0 0 0 0x00 R/W
DCLK_MO
0x35 0 0 0 0 0 DE 0 0 0x00 R/W
0x36 CLKODIV_DB DCLK_DIV_DB 0 1 0 1 1 0 0x00 R/W
0x37 VCO_BAND_DIV 0x00 R/W
0x38 SYNTH_LOCK_TIMEOUT[7:0] 0x00 R/W
0x39 O_VCO_DB SYNTH_LOCK_TIMEOUT[14:8] 0x00 R/W
0x3A VCO_ALC_TIMEOUT[7:0] 0x00 R/W
0x3B DEL_CTRL_DB VCO_ALC_TIMEOUT[14:8] 0x00 R/W
0x3C 0 0 0 0 0 0 0 0 0x00 R/W
0x3D 1 1 0 0 0 0 0 0 0x00 R/W
0x3E ADC_CLK_DIV 0x00 R/W
0x3F EN_ADC_CNV 0 0 0 0 0 EN_ADC ADC_A_CONV 0x00 R/W
0x40 0 0 MUTE_CLKOUT2 MUTE_CLKOUT1 0x00 R/W
0x41 0 0 0 0 0 0 0 0 0x00 R/W
0x42 0 0 0 0 1 0 0 1 0x00 R/W
0x43 0 ADC_CLK_SEL 0 0 1 0 0 1 0x00 R/W
0x44 0 0 0 1 1 0 0 0 0x00 R/W
0x45 0 0 0 0 1 0 0 0 0x00 R/W
0x46 0 0 0 0 0 0 0 0 0x00 R/W
0x47 0 0 0 0 0 0 0 0 0x00 R/W
0x48 0 0 0 0 0 0 0 0 0x00 R/W
0x49 0 0 0 0 0 0 0 0 0x00 R
0x4A 0 0 0 0 0 0 0 0 0x00 R/W
0x4B 0 1 0 1 1 1 0 1 0x00 R/W
0x4C 0 0 1 0 1 0 1 1 0x00 R/W
0x4D 0 0 0 0 0 0 0 0 0x00 R/W
O_VCO_BAN O_VCO_C O_VCO_B
0x4E 0 0 DCLK_DIV1 D ORE IAS 0 0x00 R/W
0x4F 0 0 0 0 0 0 0 0 0x00 R/W
0x50 0 0 0 0 0 0 0 0 0x00 R/W
0x51 0 0 0 0 0 0 0 0 0x00 R/W
0x52 0 0 0 0 0 0 0 0 0x00 R/W
RST_SYNC_
0x53 0 PD_SYNC_MON SYNC_SEL MON 0 1 0 1 0x00 R/W
0x54 RESERVED ADC_ST_CNV 0x00 R/W

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Data Sheet ADF4368
REGISTER MAPS

Table 19. ADF4368 Register Summary (Continued)

Reg Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x55 0 0 0 0 0 0 0 0 0x00 R
0x56 0 0 0 0 0 0 0 0 0x00 R
0x57 0 0 0 0 0 0 0 0 0x00 R
ADC_BUS FSM_BUS
0x58 EN_CLK2 EN_CLK1 SYNC_OK 0 REF_OK Y Y LOCKED 0x00 R
0x59 0 0 0 0 0 0 0 0 0x00 R
0x5A RESERVED VCO_CORE 0x00 R
0x5B CHIP_TEMP[7:0] 0x00 R
0x5C RESERVED CHIP_TEMP[8] 0x00 R
0x5D 0 0 0 0 0 0 0 0 0x00 R
0x5E VCO_BAND 0x00 R
0x5F 0 0 0 0 0 0 0 0 0x00 R
0x60 RESERVED VCO_BIAS 0x00 R
0x61 RESERVED 0 0 0 0 0x00 R
0x62 RESERVED 0 0 0 0x00 R
0x63 VERSION 0x00 R

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Data Sheet ADF4368
REGISTER DETAILS

Address: 0x00, Reset: 0x00, Name: REG0000

Figure 51.

Table 20. Bit Descriptions for REG0000

Bits Bit Name Description Reset Access
7 SOFT_RESET_R Repeat of SOFT_RESET. 0x0 R/W
6 LSB_FIRST_R Repeat of LSB_FIRST. 0x0 R/W
5 ADDRESS_ASCENSION_R Repeat of ADDRESS_ASCENSION. 0x0 R/W
4 SDO_ACTIVE_R Repeat of SDO_ACTIVE. 0x0 R/W
3 SDO_ACTIVE Choose Between 3-Wire or 4-Wire Operation. 0x0 R/W
0: 3-wire
1: 4-wire SPI (enables SDO and SDIO becomes an input only)
2 ADDRESS_ASCENSION Address Ascension When Streaming. 0x0 R/W
0: address auto-decrements when streaming.
1: address auto-increments when streaming.
1 LSB_FIRST I/O Data Oriented LSB First. 0x0 R/W
0: MSB first.
1: LSB first.
0 SOFT_RESET Reset SPI Registers Except REG0000 to POR State. Self-clearing reset. 0x0 R/W
0: Normal operation.
1: Soft reset.

Address: 0x01, Reset: 0x00, Name: REG0001

Figure 52.

Table 21. Bit Descriptions for REG0001

Bits Bit Name Description Reset Access
7 SINGLE_INSTRUCTION Single Instruction. 0x0 R/W
0: SPI streaming enabled.
1: SPI streaming disabled.
6 REG01_RSV6 Reserved. 0x0 R/W

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Data Sheet ADF4368
REGISTER DETAILS

Table 21. Bit Descriptions for REG0001 (Continued)

Bits Bit Name Description Reset Access
5 MAIN_READBACK_CONTROL Main/Subordinate Readback Control. 0x0 R/W
0: double buffering, readback subordinate register.
1: double buffering, readback main register.
4 REG01_RSV4 Reserved. 0x0 R/W
3 RESERVED Reserved. 0x0 R
2 REG01_RSV1 Reserved. 0x0 R/W
1 REG01_RSV0 Reserved. 0x0 R/W
0 RESERVED Reserved. 0x0 R

Address: 0x02, Reset: 0x00, Name: REG0002

Figure 53.

Table 22. Bit Descriptions for REG0002

Bits Bit Name Description Reset Access
[7:4] RESERVED Reserved. 0x0 R
[3:0] CHIP_STATUS Not Used. 0x0 R

Address: 0x03, Reset: 0x00, Name: REG0003

Figure 54.

Table 23. Bit Descriptions for REG0003

Bits Bit Name Description Reset Access
[7:4] RESERVED Reserved. 0x0 R
[3:0] CHIP_TYPE Chip Type = 0x06. 0x0 R

Address: 0x04, Reset: 0x00, Name: REG0004

Figure 55.

Table 24. Bit Descriptions for REG0004

Bits Bit Name Description Reset Access
[7:0] PRODUCT_ID[7:0] Product ID = 0x0007. 0x0 R

Address: 0x05, Reset: 0x00, Name: REG0005

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Data Sheet ADF4368
REGISTER DETAILS

Figure 56.

Table 25. Bit Descriptions for REG0005

Bits Bit Name Description Reset Access
[7:0] PRODUCT_ID[15:8] Product ID = 0x0007. 0x0 R

Address: 0x06, Reset: 0x00, Name: REG0006

Figure 57.

Table 26. Bit Descriptions for REG0006

Bits Bit Name Description Reset Access
[7:4] PRODUCT_GRADE Product Grade = 0x0 (Not Used). 0x0 R
[3:0] DEVICE_REVISION Device Revision = 0x0 (Not Used). 0x0 R

Address: 0x0A, Reset: 0x00, Name: REG000A

Figure 58.

Table 27. Bit Descriptions for REG000A

Bits Bit Name Description Reset Access
[7:0] SCRATCHPAD SPI SCRATCHPAD. 0x0 R/W

Address: 0x0B, Reset: 0x00, Name: REG000B

Figure 59.

Table 28. Bit Descriptions for REG000B

Bits Bit Name Description Reset Access
[7:0] SPI_REVISION SPI Revision = 0x01. 0x0 R

Address: 0x0C, Reset: 0x56, Name: REG000C

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Data Sheet ADF4368
REGISTER DETAILS

Figure 60.

Table 29. Bit Descriptions for REG000C

Bits Bit Name Description Reset Access
[7:0] VENDOR_ID[7:0] Vendor ID = 0x0456. 0x56 R

Address: 0x0D, Reset: 0x04, Name: REG000D

Figure 61.

Table 30. Bit Descriptions for REG000D

Bits Bit Name Description Reset Access
[7:0] VENDOR_ID[15:8] Vendor ID = 0x0456. 0x4 R

Address: 0x0F, Reset: 0x00, Name: REG000F

Figure 62.

Table 31. Bit Descriptions for REG000F

Bits Bit Name Description Reset Access
[7:1] RESERVED Reserved. 0x0 R
0 REG0F_RSV0 Reserved. 0x0 R/W

Address: 0x10, Reset: 0x80, Name: REG0010

Figure 63.

Table 32. Bit Descriptions for REG0010

Bits Bit Name Description Reset Access
[7:0] N_INT[7:0] 12 Bit Integer Word. Writing to Reg10 triggers autocalibration when EN_AUTOCAL = 1 0x80 R/W

Address: 0x11, Reset: 0x00, Name: REG0011

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Data Sheet ADF4368
REGISTER DETAILS

Figure 64.

Table 33. Bit Descriptions for REG0011

Bits Bit Name Description Reset Access
[7:6] CLKOUT_DIV Clk Output Divider. 0x0 R/W
00: Divide by 1.
01: Divide by 2.
10: Divide by 4.
11: Divide by 8.
5 INT_MODE Integer Mode Enabler. 0x0 R/W
0: Fractional Mode.
1: Integer Mode.
4 INV_CLKOUT Invert CLK1, CLK2. 0x0 R/W
0: RFCLK1, RFCLK2 Not Inverted.
1: RFCLK1, RFCLK2 Inverted.
[3:0] N_INT[11:8] 12 Bit Integer Word. Writing to Reg10 triggers autocalibration when EN_AUTOCAL = 1 0x0 R/W

Address: 0x12, Reset: 0x00, Name: REG0012

Figure 65.

Table 34. Bit Descriptions for REG0012

Bits Bit Name Description Reset Access
[7:0] FRAC1WORD[7:0] 25 Bit Frac1 Word. 0x0 R/W

Address: 0x13, Reset: 0x00, Name: REG0013

Figure 66.

Table 35. Bit Descriptions for REG0013

Bits Bit Name Description Reset Access
[7:0] FRAC1WORD[15:8] 25 Bit Frac1 Word. 0x0 R/W

Address: 0x14, Reset: 0x00, Name: REG0014

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Data Sheet ADF4368
REGISTER DETAILS

Figure 67.

Table 36. Bit Descriptions for REG0014

Bits Bit Name Description Reset Access
[7:0] FRAC1WORD[23:16] 25 Bit Frac1 Word. 0x0 R/W

Address: 0x15, Reset: 0x00, Name: REG0015

Figure 68.

Table 37. Bit Descriptions for REG0015

Bits Bit Name Description Reset Access
[7:6] M_VCO_CORE Selects VCO Core When O_VCO_CORE = 1. 0x0 R/W
00: VCO 0 Lowest Frequency.
01: VCO 1.
10: VCO 2.
11: VCO 3 Highest Frequency.
[5:2] M_VCO_BIAS Sets VCO Bias When O_VCO_BIAS = 1. 0x0 R/W
0000: Bias = 0.
0001: Bias = 1.
0010: Bias = 2.
0011: Bias = 3.
0100: Bias = 4.
0101: Bias = 5.
0110: Bias = 6.
0111: Bias = 7.
1000: Bias = 8.
1001: Bias = 9.
1010: Bias = 10.
1011: Bias = 11.
1100: Bias = 12.
1101: Bias = 13.
1110: Bias = 14.
1111: Bias = 15.
1 CMOS_OV Logic High Voltage for MUXOUT, LKDET, SDO, SDIO. 0x0 R/W
0: 1.8 V Logic.
1: 3.3 V Logic.
0 FRAC1WORD[24] 25 Bit Frac1 Word. 0x0 R/W

Address: 0x16, Reset: 0x00, Name: REG0016

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Data Sheet ADF4368
REGISTER DETAILS

Figure 69.

Table 38. Bit Descriptions for REG0016

Bits Bit Name Description Reset Access
[7:0] M_VCO_BAND Selects Band Within Core When O_VCO_BAND = 1. 255 = lowest Frequency, 0 = highest Frequency 0x0 R/W

Address: 0x17, Reset: 0x00, Name: REG0017

Figure 70.

Table 39. Bit Descriptions for REG0017

Bits Bit Name Description Reset Access
[7:0] FRAC2WORD[7:0] 24 Bits Frac2 Word. 0x0 R/W

Address: 0x18, Reset: 0x00, Name: REG0018

Figure 71.

Table 40. Bit Descriptions for REG0018

Bits Bit Name Description Reset Access
[7:0] FRAC2WORD[15:8] 24 Bits Frac2 Word. 0x0 R/W

Address: 0x19, Reset: 0x00, Name: REG0019

Figure 72.

Table 41. Bit Descriptions for REG0019

Bits Bit Name Description Reset Access
[7:0] FRAC2WORD[23:16] 24 Bits Frac2 Word 0x0 R/W

Address: 0x1A, Reset: 0x00, Name: REG001A

Figure 73.

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Data Sheet ADF4368
REGISTER DETAILS

Table 42. Bit Descriptions for REG001A

Bits Bit Name Description Reset Access
[7:0] MOD2WORD[7:0] 24 Bits Mod2 Word. 0x0 R/W

Address: 0x1B, Reset: 0x00, Name: REG001B

Figure 74.

Table 43. Bit Descriptions for REG001B

Bits Bit Name Description Reset Access
[7:0] MOD2WORD[15:8] 24 Bits Mod2 Word. 0x0 R/W

Address: 0x1C, Reset: 0x00, Name: REG001C

Figure 75.

Table 44. Bit Descriptions for REG001C

Bits Bit Name Description Reset Access
[7:0] MOD2WORD[23:16] 24 Bits Mod2 Word 0x0 R/W

Address: 0x1D, Reset: 0x00, Name: REG001D

Figure 76.

Table 45. Bit Descriptions for REG001D

Bits Bit Name Description Reset Access
[7:0] BLEED_I[7:0] 13 Bit Bleed Current Setting. 4-bit MSB for coarse setting and 9-bit LSB for fine setting 0x0 R/W

Address: 0x1E, Reset: 0x00, Name: REG001E

Figure 77.

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Data Sheet ADF4368
REGISTER DETAILS

Table 46. Bit Descriptions for REG001E

Bits Bit Name Description Reset Access
7 EN_PHASE_RESYNC Enable the Phase ReSync Mode. 0x0 R/W
6 EN_REF_RST SW_SYNC or Pin Sync Resets the R_DIV. 0x0 R/W
5 TIMED_SYNC Retime the synchronization signal with reference input clock. 0x0 R/W
0: RDIV are Reset Asynchronously.
1: The synchronization signal is retimed with reference input clock.
[4:0] BLEED_I[12:8] 13 Bit Bleed Current Setting. 4-bit MSB for coarse setting and 9-bit LSB for fine setting 0x0 R/W

Address: 0x1F, Reset: 0x00, Name: REG001F

Figure 78.

Table 47. Bit Descriptions for REG001F

Bits Bit Name Description Reset Access
7 SW_SYNC Software SYNC Request. 0x0 R/W
6 PHASE_ADJ Apply the Phase Adjust. 0x0 R/W
5 BLEED_POL Bleed Polarity. 0x0 R/W
0: Current Sink.
1: Current Source.
4 EN_BLEED Enable Bleed Current. 0x0 R/W
0: Bleed Current Disabled.
1: Bleed Current Enabled.
[3:0] CP_I Charge Pump Current. For corresponding current values, see Table 11. 0x0 R/W

Address: 0x20, Reset: 0x01, Name: REG0020

Figure 79.

Table 48. Bit Descriptions for REG0020

Bits Bit Name Description Reset Access
7 EN_AUTOCAL Enable VCO Calibration. 0x0 R/W
0: VCO Calibration Disabled.
1: VCO Calibration Enabled.
6 EN_RDBLR Enable Reference Doubler. 0x0 R/W
0: Doubler Disabled.
1: Doubler Enabled.
[5:0] R_DIV 6 Bit R-Divider. 0x1 R/W

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Data Sheet ADF4368
REGISTER DETAILS

Address: 0x21, Reset: 0x00, Name: REG0021

Figure 80.

Table 49. Bit Descriptions for REG0021

Bits Bit Name Description Reset Access
[7:0] PHASE_WORD[7:0] 24 Bits Phase Word. 0x0 R/W

Address: 0x22, Reset: 0x00, Name: REG0022

Figure 81.

Table 50. Bit Descriptions for REG0022

Bits Bit Name Description Reset Access
[7:0] PHASE_WORD[15:8] 24 Bits Phase Word. 0x0 R/W

Address: 0x23, Reset: 0x00, Name: REG0023

Figure 82.

Table 51. Bit Descriptions for REG0023

Bits Bit Name Description Reset Access
[7:0] PHASE_WORD[23:16] 24 Bits Phase Word. 0x0 R/W

Address: 0x24, Reset: 0x00, Name: REG0024

Figure 83.

Table 52. Bit Descriptions for REG0024

Bits Bit Name Description Reset Access
[7:0] PHASE_ADJUSTMENT Determines the Amount of Phase Adjustment to Be Applied. PHASE_ADJUSTMENT = Phase(deg) × 0x0 R/W
212/360.

Address: 0x25, Reset: 0x00, Name: REG0025

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Data Sheet ADF4368
REGISTER DETAILS

Figure 84.

Table 53. Bit Descriptions for REG0025

Bits Bit Name Description Reset Access
[7:0] RESYNC_WAIT[7:0] Resynchronization Waiting Time. Sets the Waiting Time After the Write of the Register 10 to Apply the 0x0 R/W
Resynchronization (RESYNC_WAIT × PFD).

Address: 0x26, Reset: 0x00, Name: REG0026

Figure 85.

Table 54. Bit Descriptions for REG0026

Bits Bit Name Description Reset Access
[7:0] RESYNC_WAIT[15:8] Resynchronization Waiting Time. Sets the Waiting Time After the Write of the Register 10 to Apply the 0x0 R/W
Resynchronization (RESYNC_WAIT × PFD).

Address: 0x27, Reset: 0x00, Name: REG0027

Figure 86.

Table 55. Bit Descriptions for REG0027

Bits Bit Name Description Reset Access
[7:0] RESYNC_WAIT[23:16] Resynchronization Waiting Time. Sets the Waiting Time After the Write of the Register 10 to Apply the 0x0 R/W
Resynchronization (RESYNC_WAIT × PFD).

Address: 0x28, Reset: 0x00, Name: REG0028

Figure 87.

Table 56. Bit Descriptions for REG0028

Bits Bit Name Description Reset Access
7 REG28_RSV1 Reserved. 0x0 R/W
6 LSB_P1 Add +1 to SDM LSB Enable/Disable. 0x0 R/W
5 VAR_MOD_EN Enable Auxiliary SDM. 0x0 R/W

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Table 56. Bit Descriptions for REG0028 (Continued)

Bits Bit Name Description Reset Access
[4:2] REG28_RSV2 Reserved. 0x0 R/W
1 REG28_RSV3 Reserved. 0x0 R/W
0 REG28_RSV4 Reserved. 0x0 R/W

Address: 0x29, Reset: 0x00, Name: REG0029

Figure 88.

Table 57. Bit Descriptions for REG0029

Bits Bit Name Description Reset Access
[7:4] CLK2_OPWR Select CLK2 Output Amplitude. 0x0 R/W
0000: Min Power Setting.
1111: Max Power Setting.
[3:0] CLK1_OPWR Select CLK1 Output Amplitude. 0x0 R/W
0000: Min Power Setting.
1111: Max Power Setting.

Address: 0x2A, Reset: 0x04, Name: REG002A

Figure 89.

Table 58. Bit Descriptions for REG002A

Bits Bit Name Description Reset Access
7 REG2A_RSV5 Reserved. 0x0 R/W
6 PHASE_ADJ_POL Determines the Polarity of the Phase Adjustment. 0x0 R/W
0: Adds The Selected Phase Value.
1: Subtract The Selected Phase Value.
5 REG2A_RSV4 Reserved. 0x0 R/W
4 PD_SYNC Power Down the synchronization. 0x0 R/W
3 REG2A_RSV3 Reserved. 0x0 R/W
2 PD_RDET Power Down the Reference Detector. 0x1 R/W
0: Normal Operation.
1: Power Down the Reference Detector.
1 REG2A_RSV2 Reserved. 0x0 R/W
0 REG2A_RSV1 Reserved. 0x0 R/W

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Address: 0x2B, Reset: 0x83, Name: REG002B

Figure 90.

Table 59. Bit Descriptions for REG002B

Bits Bit Name Description Reset Access
7 PD_ALL Main Power Down. 0x1 R/W
0: Normal Operation.
1: Power Down.
6 REG2B_RSV4 Reserved. 0x0 R/W
5 REG2B_RSV3 Reserved. 0x0 R/W
4 REG2B_RSV2 Reserved. 0x0 R/W
3 PD_LD Power Down the Lock Detector. 0x0 R/W
0: Normal Operation.
1: Power Down the Lock Detector.
2 REG2B_RSV1 Reserved. 0x0 R/W
1 PD_CLKOUT1 Power Down CLK1 Output Buffer. 0x1 R/W
0: Normal Operation.
1: Power Down CLK1 Output.
0 PD_CLKOUT2 Power Down CLK2 Output Buffer. 0x1 R/W
0: Normal Operation.
1: Power Down CLK2 Output.

Address: 0x2C, Reset: 0x00, Name: REG002C

Figure 91.

Table 60. Bit Descriptions for REG002C

Bits Bit Name Description Reset Access
[7:5] LDWIN_PW Lock Detector Pulse Window Width. The details are given in Table 14. 0x0 R/W
[4:0] LD_COUNT Number of PFD Cycles Before LD Goes High. Cycles =
LD_COUNT
24 × 2 +3
if LD_COUNT is even
LD_COUNT − 1
32 × 2 +3
if LD_COUNT is odd 0x0 R/W

Address: 0x2D, Reset: 0x00, Name: REG002D

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Figure 92.

Table 61. Bit Descriptions for REG002D

Bits Bit Name Description Reset Access
7 EN_DNCLK Enable Div_Nclk to the Digital Block. 0x0 R/W
0: Div_Nclk off.
1: Div_Nclk on.
6 EN_DRCLK Enable Div_Rclk to the Digital Block. 0x0 R/W
0: DIv_Rclk off.
1: Div_Rclk on.
5 EN_LOL Enable Loss-of-Lock Detector. 0x0 R/W
0: Disable loss-of-lock detector.
1: Enable loss-of-lock detector.
4 EN_LDWIN Enable the Lock Detector Pulse Window. 0x0 R/W
0: Lock detector pulse window disabled.
1: Lock detector pulse window enabled.
3 REG2D_RSV2 Reserved. 0x0 R/W
2 RST_LD Reset Lock Detector to the Unlocked State. 0x0 R/W
0: Reset inactive.
1: Reset active.
[1:0] REG2D_RSV1 Reserved. 0x0 R/W

Address: 0x2E, Reset: 0x00, Name: REG002E

Figure 93.

Table 62. Bit Descriptions for REG002E

Bits Bit Name Description Reset Access
[7:4] MUXOUT Select Test Signal to MUXOUT. 0x0 R/W
0000: High-Z.
0001: LKDET.
0010: low.
0011: low.
0100: Div_Rclk/2.
0101: Div_Nclk/2.

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Table 62. Bit Descriptions for REG002E (Continued)

Bits Bit Name Description Reset Access
0110: reserved.
0111: low.
1000: high.
1001: reserved.
1010: reserved.
1011: low.
1100: low.
1101: low.
1110: reserved.
1111: reserved.
3 REG2E_RSV1 Reserved. 0x0 R/W
2 EN_CPTEST Enable Charge Pump Force Up/Down Test Mode. 0x0 R/W
0: charge-pump force up/down test mode off (normal operation).
1: charge-pump force up/down test mode on.
1 CP_DOWN Force Pump Down Charge Pump Test Mode. 0x0 R/W
0: force pump down off.
1: force pump down on.
0 CP_UP Force Pump Up Charge Pump Test Mode. 0x0 R/W
0: force pump up off.
1: force pump up on.

Address: 0x2F, Reset: 0x00, Name: REG002F

Figure 94.

Table 63. Bit Descriptions for REG002F

Bits Bit Name Description Reset Access
7 BST_REF Gain Boost for Low Amplitude Sine-Wave Reference Input (REF_SEL = 1). 0x0 R/W
0: use for large reference input signals > 1.6 V p-p when REF_SEL = 1.
1: use for large reference input signals < 1.6 V p-p when REF_SEL = 1.
6 FILT_REF Select Noise Filter for Sine-Wave Reference Input Buffer. 0x0 R/W
0: noise filter off.
1: noise filter on.
5 REF_SEL Select CML Reference Input or Sine Wave/Slow Slew Rate Reference Input. 0x0 R/W
0: DMA. Delay matched amplifier (DMA), for improved reference to clock output delay.
1: LNA. Low noise amplifier (LNA), for low slew rate signals/low frequency sine waves.
4 REG2F_RSV2 Reserved. 0x0 R/W
[3:0] REG2F_RSV1 Reserved. 0x0 R/W

Address: 0x30, Reset: 0x00, Name: REG0030

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Figure 95.

Table 64. Bit Descriptions for REG0030

Bits Bit Name Description Reset Access
7 MUTE_NCLK Mutes the N Divider Output to Digital Block. Set to 0 for normal operation. 0x0 R/W
6 REG30_RSV3 Reserved. 0x0 R/W
[5:3] DRCLK_DEL Reserved. 0x0 R/W
[2:0] DNCLK_DEL Reserved. 0x0 R/W

Address: 0x31, Reset: 0x00, Name: REG0031

Figure 96.

Table 65. Bit Descriptions for REG0031

Bits Bit Name Description Reset Access
[7:5] REG31_RSV4 Reserved. 0x0 R/W
4 RST_SYS Reset Digital Except SPI Interface and Registers to POR State. 0x0 R/W
0: reset inactive.
1: reset active.
3 EN_ADC_CLK Enable the ADC Clock. 0x0 R/W
0: disable ADC clock.
1: enable ADC clock.
2 REG31_RSV3 Reserved. 0x0 R/W
1 REG31_RSV2 Reserved. 0x0 R/W
0 REG31_RSV1 Reserved. 0x0 R/W

Address: 0x35, Reset: 0x00, Name: REG0035

Figure 97.

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Table 66. Bit Descriptions for REG0035

Bits Bit Name Description Reset Access
7 REG35_RSV4 Reserved. 0x0 R/W
[6:3] REG35_RSV3 Reserved. 0x0 R/W
2 DCLK_MODE Drop RCLK, NCLK Frequency by Factor of 2 During VCO Calibration. 0x0 R/W
0: disable frequency reduction.
1: enable frequency reduction.
1 REG35_RSV2 Reserved. 0x0 R/W
0 REG35_RSV1 Reserved. 0x0 R/W

Address: 0x36, Reset: 0x00, Name: REG0036

Figure 98.

Table 67. Bit Descriptions for REG0036

Bits Bit Name Description Reset Access
7 CLKODIV_DB CLKOUT_DIV Double Buffered. 0x0 R/W
0: CLKOUT_DIV not double buffered.
1: CLKOUT_DIV double buffered.
6 DCLK_DIV_DB DCLK_DIV1 Double Buffered. 0x0 R/W
0: not double buffered.
1: double buffered.
5 REG36_RSV3 Reserved. 0x0 R/W
4 REG36_RSV2 Reserved. 0x0 R/W
[3:0] REG36_RSV1 Reserved. 0x0 R/W

Address: 0x37, Reset: 0x00, Name: REG0037

Figure 99.

Table 68. Bit Descriptions for REG0037

Bits Bit Name Description Reset Access
[7:0] VCO_BAND_DIV Time for Each VCO Calibration Decision. VCO calibration time per Decision = 16 × VCO_BAND_DIV/(Div_Rclk
frequency) 0x0 R/W

Address: 0x38, Reset: 0x00, Name: REG0038

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Figure 100.

Table 69. Bit Descriptions for REG0038

Bits Bit Name Description Reset Access
[7:0] SYNTH_LOCK_TIMEOUT[7:0] Timeout for the Calibration DAC Settling Time During a VCO Calibration. Time = 0x0 R/W
SYNTH_LOCK_TIMEOUT/(fDIV_RCLK Frequency)

Address: 0x39, Reset: 0x00, Name: REG0039

Figure 101.

Table 70. Bit Descriptions for REG0039

Bits Bit Name Description Reset Access
7 O_VCO_DB M_VCO_CORE, M_VCO_BAND, M_VCO_BIAS Doubled Buffered. 0x0 R/W
0: core, bias, and band not double buffered.
1: core, bias, and band double buffered.
[6:0] SYNTH_LOCK_TIMEOUT[14:8] Timeout for the Calibration DAC Settling Time During a VCO Calibration. Time = 0x0 R/W
SYNTH_LOCK_TIMEOUT/(fDIV_RCLK Frequency)

Address: 0x3A, Reset: 0x00, Name: REG003A

Figure 102.

Table 71. Bit Descriptions for REG003A

Bits Bit Name Description Reset Access
[7:0] VCO_ALC_TIMEOUT[7:0] Timeout for Automatic Level Control (ALC) Algorithm During VCO Calibration. Time = 0x0 R/W
VCO_ALC_TIMEOUT[14:0]/(fDIV_RCLK Frequency)

Address: 0x3B, Reset: 0x00, Name: REG003B

Figure 103.

Table 72. Bit Descriptions for REG003B

Bits Bit Name Description Reset Access
7 DEL_CTRL_DB Delay Controls Double Buffered. INV_CLKOUT, BLEED_I, BLEED_POL double buffered. 0x0 R/W

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Table 72. Bit Descriptions for REG003B (Continued)

Bits Bit Name Description Reset Access
0: not double buffered.
1: double buffered.
[6:0] VCO_ALC_TIMEOUT[14:8] Timeout for Automatic Level Control (ALC) Algorithm During VCO Calibration. Time = 0x0 R/W
VCO_ALC_TIMEOUT[14:0]/(fDIV_RCLK Frequency)

Address: 0x3E, Reset: 0x00, Name: REG003E

Figure 104.

Table 73. Bit Descriptions for REG003E

Bits Bit Name Description Reset Access
[7:0] ADC_CLK_DIV ADC Clock Divider Value. Desired ADC clock frequency < 400 kHz. If ADC_CLK_DIV = round up (((fDIV_RCLK)/ 0x0 R/W
(Desired ADC Clock Frequency))−2)/4.

Address: 0x3F, Reset: 0x00, Name: REG003F

Figure 105.

Table 74. Bit Descriptions for REG003F

Bits Bit Name Description Reset Access
7 EN_ADC_CNV Enable ADC Conversion. 0x0 R/W
0: no ADC conversion.
1: enabled. Normal operation.
6 REG3F_RSV5 Reserved. 0x0 R/W
5 REG3F_RSV4 Reserved. 0x0 R/W
4 REG3F_RSV3 Reserved. 0x0 R/W
3 REG3F_RSV2 Reserved. 0x0 R/W
2 REG3F_RSV1 Reserved. 0x0 R/W
1 EN_ADC Enable ADC. 0x0 R/W
0: ADC Disabled.
1: ADC Enabled.
0 ADC_A_CONV Run an ADC Conversion at the Start of a VCO Calibration. 0x0 R/W
0: ADC conversion only possible with write to ADC_ST_CNV bit field.
1: enabled. Normal operation. Automatically begins ADC conversion at the start of a VCO calibration or with
write to ADC_ST_CNV bit field.

Address: 0x40, Reset: 0x00, Name: REG0040

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Figure 106.

Table 75. Bit Descriptions for REG0040

Bits Bit Name Description Reset Access
[7:6] REG40_RSV1 Reserved. 0x0 R/W
[5:3] MUTE_CLKOUT2 Mute Control for the Output Buffer 2. 0x0 R/W
[2:0] MUTE_CLKOUT1 Mute Control for the Output Buffer 1. 0x0 R/W

Address: 0x43, Reset: 0x00, Name: REG0043

Figure 107.

Table 76. Bit Descriptions for REG0043

Bits Bit Name Description Reset Access
7 REG43_RSV5 Reserved. 0x0 R/W
6 ADC_CLK_SEL Select ADC Clock Source. 0x0 R/W
0: Use Rclk as ADC Clock Source (normal Operation).
1: Use SPI SCLK as ADC Clock Source (test Mode).
5 REG43_RSV4 Reserved. 0x0 R/W
4 REG43_RSV3 Reserved. 0x0 R/W
3 REG43_RSV2 Reserved. 0x0 R/W
[2:0] REG43_RSV1 Reserved. 0x0 R/W

Address: 0x4E, Reset: 0x00, Name: REG004E

Figure 108.

Table 77. Bit Descriptions for REG004E

Bits Bit Name Description Reset Access
[7:6] REG4E_RSV2 Reserved. 0x0 R/W
[5:4] DCLK_DIV1 Controls Div_Rclk Div1 Div_Nclk Div1. 0x0 R/W

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Table 77. Bit Descriptions for REG004E (Continued)

Bits Bit Name Description Reset Access
00: Divide by 1.
01: Divide by 2.
10: Divide by 4.
11: Divide by 8.
3 O_VCO_BAND Override VCO Band with M_VCO_BAND. 0x0 R/W
0: VCO Band Code from VCO Calibration State-machine.
1: VCO Band Code from M_VCO_BAND.
2 O_VCO_CORE Override VCO Core with M_VCO_CORE. 0x0 R/W
0: VCO Core Select from VCO Calibration State-machine.
1: VCO Core Select from M_VCO_CORE.
1 O_VCO_BIAS Override VCO Bias with M_VCO_BIAS. 0x0 R/W
0: VCO Bias Code from VCO Calibration State-machine.
1: VCO Bias Code from M_VCO_VBIAS.
0 REG4E_RSV1 Reserved. 0x0 R/W

Address: 0x53, Reset: 0x00, Name: REG0053

Figure 109.

Table 78. Bit Descriptions for REG0053

Bits Bit Name Description Reset Access
7 REG53_RSV2 Reserved. 0x0 R/W
6 PD_SYNC_MON Power Down the SYSREF Setup/hold Monitor. 0x0 R/W
0: Normal Operation.
1: Power Down the SYSREF Setup/hold Monitor.
5 SYNC_SEL SYSREF CML/PECL Input or LVDS Input. 0x0 R/W
0: CML/PECL Input.
1: LVDS Input.
4 RST_SYNC_MON Clear the Output Latch of the Setup/hold Monitor. 0x0 R/W
0: Reset Inactive.
1: Reset Active.
[3:0] REG53_RSV1 Reserved. 0x0 R/W

Address: 0x54, Reset: 0x00, Name: REG0054

Figure 110.

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Table 79. Bit Descriptions for REG0054

Bits Bit Name Description Reset Access
[7:1] RESERVED Reserved. 0x0 R
0 ADC_ST_CNV Write This Bit to Start an ADC Conversion. 0x0 R/W

Address: 0x58, Reset: 0x00, Name: REG0058

Figure 111.

Table 80. Bit Descriptions for REG0058

Bits Bit Name Description Reset Access
7 EN_CLK2 Logic State on EN_CLK2 Input Pin. 0x0 R
6 EN_CLK1 Logic State on EN_CLK1 Input Pin. 0x0 R
5 SYNC_OK 1 = SYSREF is in Correct Setup/hold with respect to reference. 0x0 R
4 REG58_RSV1 Reserved. 0x0 R
3 REF_OK 1= Reference Input Amplitude Above Threshold. 0x0 R
2 ADC_BUSY 1 = ADC Conversion in Progress. 0x0 R
1 FSM_BUSY 1 = VCO Cal in Progress. 0x0 R
0 LOCKED Lock Detector Output. 0x0 R

Address: 0x5A, Reset: 0x00, Name: REG005A

Figure 112.

Table 81. Bit Descriptions for REG005A

Bits Bit Name Description Reset Access
[7:2] RESERVED Reserved. 0x0 R
[1:0] VCO_CORE VCO Core Readback Value. 0x0 R

Address: 0x5B, Reset: 0x00, Name: REG005B

Figure 113.

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Table 82. Bit Descriptions for REG005B

Bits Bit Name Description Reset Access
[7:0] CHIP_TEMP[7:0] Temperature Measured by the ADC. Bit[8] = Sign Bits[7:0] = Magnitude 0x0 R

Address: 0x5C, Reset: 0x00, Name: REG005C

Figure 114.

Table 83. Bit Descriptions for REG005C

Bits Bit Name Description Reset Access
[7:1] RESERVED Reserved. 0x0 R
0 CHIP_TEMP[8] Temperature Measured by the ADC. Bit[8] = Sign Bits[7:0] = Magnitude 0x0 R

Address: 0x5E, Reset: 0x00, Name: REG005E

Figure 115.

Table 84. Bit Descriptions for REG005E

Bits Bit Name Description Reset Access
[7:0] VCO_BAND VCO Band Readback Value. 0x0 R

Address: 0x60, Reset: 0x00, Name: REG0060

Figure 116.

Table 85. Bit Descriptions for REG0060

Bits Bit Name Description Reset Access
[7:4] RESERVED Reserved. 0x0 R
[3:0] VCO_BIAS VCO Bias Readback Value. 0x0 R

Address: 0x63, Reset: 0x00, Name: REG0063

Figure 117.

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Table 86. Bit Descriptions for REG0063

Bits Bit Name Description Reset Access
[7:0] VERSION Chip Version. 0x0 R

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Data Sheet ADF4368
OUTLINE DIMENSIONS

Figure 118. 48-Lead Land Grid Array Package [LGA]

7 mm × 7 mm Body
CC-48-13
Dimensions Shown in millimeters

Updated: March 17, 2023

ORDERING GUIDE
Model1 Temperature Range Package Description Packing Quantity Package Option
ADF4368BCCZ −40°C to +105°C 48-Terminal Land Grid Array [LGA] (7 mm x 7 mm) Tray, 260 CC-48-13
ADF4368BCCZ-RL7 −40°C to +105°C 48-Terminal Land Grid Array [LGA] (7 mm x 7 mm) Reel, 500 CC-48-13
1 Z = RoHS-Compliant Part.

EVALUATION BOARDS

Model1 Description
EV-ADF4368SD1Z Evaluation Board

1 Z = RoHS-Compliant Part.

©2023 Analog Devices, Inc. All rights reserved. Trademarks and Rev. 0 | 54 of 54
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.