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PDF_16MVE332

The document outlines the examination structure for a VLSI Testing elective course at R.V. College of Engineering, detailing the exam format, units, and specific questions related to fault testing and circuit design. It includes instructions for candidates, a breakdown of units with questions on topics like stuck-at faults, testing methodologies, and fault simulation. The examination is designed to assess knowledge in VLSI design and embedded systems over a three-hour period for a maximum of 100 marks.

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Bhargav Bhat
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9 views5 pages

PDF_16MVE332

The document outlines the examination structure for a VLSI Testing elective course at R.V. College of Engineering, detailing the exam format, units, and specific questions related to fault testing and circuit design. It includes instructions for candidates, a breakdown of units with questions on topics like stuck-at faults, testing methodologies, and fault simulation. The examination is designed to assess knowledge in VLSI design and embedded systems over a three-hour period for a maximum of 100 marks.

Uploaded by

Bhargav Bhat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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January-2019 PG Examinations

USN
16MVE332
R. V. COLLEGE OF ENGINEERING
(Autonomous Institution affiliated to VTU, Belagavi)
III Semester Master of Technology (VLSI Design and Embedded Systems)
VLSI TESTING (ELECTIVE)
Time: 03 Hours Maximum Marks: 100
Instructions to candidates:
1. Each unit consists of two questions of 20 marks each.
2. Answer FIVE full questions selecting one from each unit.

UNIT-1
1 a Draw a circuit for 3-input gate, then find a test
stuck-open and stuck-short fault for each single transistor. What are
the equivalent faults for above circuit at transistor level? 08
b Define fault equivalence and fault dominance. Show that the two
faults ( /0 and /1)are equivalent in the combinational circuit of
fig1b.

fig1b 06
c Find the minimum number of test vectors required to test for all
single stuck-at faults in the following circuits:
i) A 512-input exclusive- gate.
ii) A 512-input exclusive- gate.
iii) A 12-input gate. 06
OR

2 a Bring out the differences between functional testing and structural


testing of circuits with example. 06
b A chip manufacturer is to produce in a very large quantity.
Cost of design (amortized on each $ 5.00
Production cost of each $ 2.00
Test cost for each $ 3.00
Test as filter has the following properties based on the quality of test:
93% of the truly good devices will pass the test.
94% of the bad devices will fail the test.
Based on the technology used, it is known that the true yield of
being fabricated is 70%.
i) What percentage of good devices will fail the test?
ii) What percentage of bad devices will pass the test?
iii) Determine the Yield.
iv) Determine the Defect Level( ) in parts per million.
v) Determine the yield loss due to above testing.
Assuming that the manufacturer will have to pay $ 55.00 for every bad
device sold to a customer (because customer will return a bad ), at
what price should an be sold so that manufacturer breaks even. 08
c What is bridging fault? Show an example where a combinational logic
circuit will become a sequential circuit in the presence of a bridging
fault. Determine the output function of the circuit in Fig 2c for the
bridge fault between inputs and .
Fig 2c 06

UNIT-2

3 a Consider the circuits shown in fig 3a for computations. This


circuit is a part of a larger combinational circuit. In this circuit some
of the values, i.e the 0, 1 and values, are already
computed and shown in the circuit. Compute all the remaining
values.

Fig 3a 10
b For the circuit in Fig 3b, determine the test pattern for ‘5 ! " ! 0’
using - algorithm neatly indicating all the steps of - algorithm.

Fig 3b 08
c Write the primitive -cube for a 3-input gate, with output #/0. 02
OR

4 a For the circuit shown in Fig 4a, determine the set of all vectors that
can detect the following faults using Boolean difference:
i) $ !"!0
ii) $ !"!1

Fig 4a 08
b For the circuit shown in Fig 4b, compute the test pattern for detecting
the single stuck-at-fault using path sensitization method neatly
indicating all the steps.
i) A stuck-at-0
ii) stuck-at-1
iii) % stuck-at-1
iv) & stuck-at-0.
Fig 4b
06
c Explain the concept of time frame expansion method. For the circuit
shown in Fig 4c, find a test pattern to detect ! " ! 0 using time
frame expansion method. How many time frames are needed?

Fig 4c 06

UNIT-3

5 a What are the adhoc '( design practices? 04


b Show and explain the full scan structure implementation of the
sequential circuit shown in Fig 5b, and find the test pattern to detect
fault &) /1

Fig 5b
What are the scan design overheads? 10
c Assuming a four-bit machine word, demonstrate parallel fault
simulation of vector*1,0,1 for three single struck-at-1 faults on the
second primary input and its two fanouts, respectively, in the circuit
of fig 5c.

fig 5c. 06

OR

6 a For the circuit shown in fig 6a, use deductive fault simulation to
determine the faults detected by the of input patterns
*", +, , ,, , $ *1,1,0,1,1,1 and *1,1,0,1,1,0 .
fig 6a
07
b With neat diagram explain four mode of operation of Boundary scan
cell. 06
c Define and explain the 4 mandatory and 6 optional instruction set of
standard ... 1149.1. 07

UNIT-4

7 a Build a four flip-flop rule 150 cellular automation ( ), and compute


its pattern sequence. Seed the pattern generator with “0001”. What
is the period of the cellular automation? Compute the pattern
sequence of the four flip-flop ' with characteristics polynomial
)
,*/ 1 0 / . What is the ' ’ period? Is the better than the
' , and if so, then why? 10
b Using state diagram, define the following memory fault methods:
i) Transition fault
ii) Inversion coupling fault.
iii) Idempotent Coupling fault.
For 2&1 memory, prove that March -test detects all faults. 10

OR

8 a Consider a characteristic polynomial :/ 3 0 / 0 1.


i) Give an internal exclusive- (modular) realization of this
polynomial.
ii) A data sequence is to be fed to this ' . The data sequence
is 0 1 0 01 1 0 0 1, with written on the left and the bit
to the right. Write this sequence in the polynomial form.
iii) The sequence above is fed to a modular realization of
with the characteristic polynomial / 3 0 / 0 1. Determine the
signature(contents of ) of the circuit producing this
sequence as output. 08
b Memory testing
Consider the following March algorithm: 56 *70 ; 6 * 0, 71 ; 9 * 1 :
This algorithm is called ;<2018. You can refer to the three
march elements in this algorithm as 1, 2 and 3. This test is
applied to a 1 memory array consisting of 1024 > 1024 bits.
i) What is the length of this algorithm?
ii) Will this algorithm detect cell stuck-at faults in the memory
arrays?
iii) Consider a fault in which a writing a 1 to the memory
location 1522 causes the cell 248 to change from 1 to 0. Will
this test detect such a fault? If yes, when will the fault be
excited and when will it be detected. If no, explain.
iv) Consider a fault in which a writing a 0 to the memory
location 1522 causes the cell 248 to change from 1 to 0, will
this test detect such a fault? If yes, when will the fault be
excited and when will it be detected. If no, explain.
v) Consider a fault in which a writing a 1 to the memory
location 4006 causes the cell 428 to change from 0 to 1, will
this test detect such a fault? If yes, when will the fault be
excited and when will it be detected. If no, explain.
vi) Consider a fault in which a writing a 0 to the memory
location 4006 causes the 428 to change from 0 to 1, will this
test detect such a fault? If yes, when will the fault be excited
and when will it be detected. If no, explain. 12

UNIT-5

9 a Write advantages and disadvantages of on-line testing over off-line


testing. 06
b Explain with example diagnosis by ??( reduction technique. 08
c For the circuit shown in Fig 9c, generate the test to distinguish the
faults ! " ! 1 and ' ! " ! 0.

Fig 9c 06

OR

10 a What is fault dictionary ? Explain with an example. 06


b Design @/2@ checker. Prove that @/2@ checker designed is totally
self-checking for all single stuck faults. 08
c Prove that Berger code detects all unidirectional errors. 06

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