Electrical and Computer Engineering Department

Texas A&M University

ECEN 607

Advanced Analog Circuit Design

Homework 1

JESSE COULON

February 11, 2009

PROBLEM 1

Determination of the Order of the Amplifier

Typically, when a dc gain of close to 80 dB or more is required from a multistage amplifier with
simple, nancascode gain stages, people resort to using either 3 stage or 4 stage amplifiers. Any
more than that would make the design very complex since there will be so many variables to so
deal with. Even for the four stage amplifier, there is a relative difficulty because of the large
number of variables required to optimize the design. Previous results from published works on
NGCC amplifiers prove that both 3 and 4 stage amplifiers can attain very high dc gain with
enough phase margins and good settling time. The 3 stage is likely to consume less power but at
the cost of a very strict design to ensure that all the specifications are met, but makes stabilizing
the amplifier easier. The 4 – stage although a little more complex, provides a little more freedom,
relaxing a bit the design constraints for each stage while still achieving the desired specs. It is
more difficult to stabilize the amplifier in this case.
Determination of Slope Factor “n”

To obtain the slope factor, first we need to determine the normalizing current of the ACM model.
The circuit used is showing in the figure below.

(a) PMOS (b) NMOS

Schematic Setup for the Extraction of Is

The transistors are biased to be in the saturation region. A current with a small delta value is
applied to each transistor and the corresponding change in source voltage of the transistors is
measured. The normalization current (Is) is then computed as follows.

For NMOS:
2
𝛥𝛥𝛥𝛥
⎛ 𝐼𝐼 ⎞
𝐼𝐼𝑠𝑠 ≅ 𝐼𝐼 ∗ ⎜ ⎟ 𝛥𝛥𝛥𝛥 = 4µ𝐴𝐴
2𝛥𝛥𝛥𝛥𝑠𝑠
�𝜙𝜙
𝑡𝑡
⎝ ⎠
𝐼𝐼 = 40µ𝐴𝐴 𝜙𝜙𝑡𝑡 = 25.9𝑚𝑚𝑚𝑚

𝛥𝛥𝛥𝛥 = 0.5012 − 0.3529 = 0.01408

 𝐼𝐼𝑠𝑠 = 307.37𝑛𝑛

For PMOS

𝐼𝐼 = 40µ𝐴𝐴 𝜙𝜙𝑡𝑡 = 25.9𝑚𝑚𝑚𝑚

𝛥𝛥𝛥𝛥 = 252𝑚𝑚 − 230.2𝑚𝑚

𝐼𝐼𝑠𝑠 = 142.24 𝑛𝑛𝑛𝑛

Plot showing delta Vs used for Extraction of Is

Next, the Vp parameter has to also be determined. From the ACM model

𝑉𝑉𝑉𝑉 − 𝑉𝑉𝑉𝑉 = ∅𝑡𝑡�√1 + 𝑖𝑖𝑖𝑖� − 2 + 𝐼𝐼𝐼𝐼�√1 + 𝑖𝑖𝑖𝑖 − 1�

It is observed that with id = 3, Vp =Vs. Fig 2.4 is the setup for obtaining Vp and Fig 2.5 is the
result from the dc sweep of the setup. A current of 3Is is used.
 (a) PMOS (b) NMOS

Setup used for Obtaining Vp

With this parameter, the value of “n” can now be obtained. By ACM model definition, n is the
derivative of Vg with respect to Vp. From the previous simulation, Vp = Vs.

𝑑𝑑𝑑𝑑𝑑𝑑
𝑛𝑛 = � �
𝑑𝑑𝑑𝑑𝑑𝑑

Plot of n and VD for NMOS and PMOS

From the plot the value of n is extracted at Vg = 0 for NMOS and Vg = Vdd = 2 for PMOS be
obtained.

Transistor n
PMOS 1.222
NMOS 1.266

General Design Procedure

A new variable which depends on the relative location of the poles of the system to each other
will be used throughout the design. The general procedure for designing a 4th order system is
used here. The 3 stage is obtained by assuming f4 is at infinity. These are the ‘f’ variables. An N-
stage NGCC has N ‘f’ variables, as such the following 4 are used henceforth, f1, f2, f3 and f4.

The transfer function for the 4 stage NGCC can be represented by the following equation

𝐴𝐴𝑜𝑜
𝐻𝐻(𝑠𝑠) =
𝐴𝐴 𝑠𝑠 𝑠𝑠 2 𝑠𝑠 3
( 1 + 𝑓𝑓1𝑜𝑜 )(1 + 𝑓𝑓2 + 𝑓𝑓2𝑓𝑓3 + 𝑓𝑓2𝑓𝑓3𝑓𝑓4)

𝑤𝑤ℎ𝑒𝑒𝑒𝑒𝑒𝑒 𝐴𝐴𝑜𝑜 𝑖𝑖𝑖𝑖 𝑡𝑡ℎ𝑒𝑒 𝑑𝑑𝑑𝑑 𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔 𝑎𝑎𝑎𝑎𝑎𝑎 𝑓𝑓1, 𝑓𝑓2, 𝑓𝑓3 𝑎𝑎𝑎𝑎𝑎𝑎 𝑓𝑓4 𝑎𝑎𝑎𝑎𝑎𝑎 𝑡𝑡ℎ𝑒𝑒 𝑐𝑐𝑐𝑐𝑐𝑐 𝑜𝑜𝑜𝑜𝑜𝑜 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 𝑜𝑜𝑜𝑜 𝑒𝑒𝑒𝑒𝑒𝑒ℎ 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠

The stability criteria for this circuit can be fixed by using Routh-Hurwitz stability criterion on
the unity-feedback transfer function which is given by the below equation

1
𝐻𝐻𝐶𝐶𝐶𝐶(𝑠𝑠) =
𝑠𝑠 𝑠𝑠 2 𝑠𝑠 3 𝑠𝑠 4
+ 𝑓𝑓1𝑓𝑓2 + 𝑓𝑓1𝑓𝑓2𝑓𝑓3 + 𝑓𝑓1𝑓𝑓2𝑓𝑓3𝑓𝑓4
𝑓𝑓1

We obtain the following conditions for stability

𝑓𝑓4 > 𝑓𝑓2
𝑓𝑓2
𝑓𝑓4 >
𝑓𝑓1
1 − 𝑓𝑓3

Also phase margin can be approximated by the following equation if f3>f2 and f4>f2
ØM = 90 –arctan(GB/f2)
 • The cutoff of the first stage,f1 is set equal to the required GBW and f2 is obtained from
the approximate expression of the phase margin.

𝒇𝒇𝒇𝒇 = 𝑮𝑮𝑮𝑮𝑮𝑮 ≅ 𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑

𝐺𝐺𝐺𝐺𝐺𝐺
∅𝑚𝑚 = 90° − tan−1 � � = 70° , 𝐺𝐺𝐺𝐺𝐺𝐺 = 30𝑀𝑀𝑀𝑀𝑀𝑀,
𝑓𝑓2

𝑡𝑡ℎ𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒, 𝒇𝒇𝒇𝒇 ≅ 𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑 = 𝟗𝟗𝟗𝟗 𝑴𝑴𝑴𝑴𝑴𝑴

• f3 and f4 are determined from the settling time and power requirement of the amplifier. A
sweep of f3 and f4 can be done versus normalized power and settling power and the
values of f3 and f4 that produces the minimum power and settling time and also meet the
condition for phase margin >70deg is chosen. Using the full expression for the phase
margin of the system, a numerical analysis can be performed to find optimum values of
f3 and f4 such that settling time is minimized while the phase margin is not degraded.
This can be performed using MATLAB. The code used is shown in Appendix A.
• To do that we need to choose values for the miller capacitors that we will use in the
compensation. We require the ratios between the miller caps and the load cap to
determine the normalized power for the MATLAB plots. For this design we use a miller
caps of 2.5pF.

The phase margin is computed from the expression below:

𝑮𝑮𝑮𝑮𝑮𝑮 𝟏𝟏 − 𝑮𝑮𝑮𝑮𝑮𝑮𝟐𝟐 ⁄𝒇𝒇𝒇𝒇. 𝒇𝒇𝒇𝒇

∅𝒎𝒎 = 𝟗𝟗𝟗𝟗° − 𝐭𝐭𝐭𝐭𝐭𝐭−𝟏𝟏 � � ��
𝒇𝒇𝒇𝒇 𝟏𝟏 − 𝑮𝑮𝑮𝑮𝑮𝑮𝟐𝟐 ⁄𝒇𝒇𝒇𝒇. 𝒇𝒇𝒇𝒇

Settling time is obtained using the general transfer function of a 4th order NGCC, connecting it in
unity feedback and taking the step response. The details are shown in the MATLAB code in the
appendix. Fig 1.2 shows the results obtained.
 15 5

10 4

5 3

0 2
1 2 3 4 5 6 7 8
Normalized Settling Time (Ts*GBW)

f3 = 3*f2
15 5

10 4

Normalized Power
5 Settling Time 3

0 2
1 2 3 4 5 6 7 8

f3 = 3.5*f2
10 6

5 4

0 2
1 2 3 4 5 6 7 8
Normalized f4

From the plots, it is seen that when f3 = 2.5f1, which is the first plot above, the settling time and
power can be optimized. The power and settling time in the other two cases are quite higher
compared to the case when f3 =2.5f1. At that point the f4 is given by 3.5f1 and so we proceed
with the design with these parameters

Next we can determine the transconductance of each stage from the following equation:

𝑔𝑔𝑔𝑔𝑔𝑔
𝑓𝑓𝑓𝑓 = … … … … .1
2𝜋𝜋𝜋𝜋𝜋𝜋𝜋𝜋

𝒇𝒇𝒇𝒇 = 𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑, 𝒇𝒇𝒇𝒇 = 𝟗𝟗𝟗𝟗𝟗𝟗𝟗𝟗𝟗𝟗, 𝒇𝒇𝒇𝒇 = 𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐 𝒂𝒂𝒂𝒂𝒂𝒂 𝒇𝒇𝒇𝒇 = 𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑

𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 𝑡𝑡ℎ𝑒𝑒𝑒𝑒𝑒𝑒 𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣 𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 𝑒𝑒𝑒𝑒𝑒𝑒 1 𝑔𝑔𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 𝑡𝑡ℎ𝑒𝑒 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 𝑔𝑔𝑔𝑔𝑔𝑔.

 𝑤𝑤𝑤𝑤 𝑐𝑐ℎ𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 𝐶𝐶𝐶𝐶1 = 𝐶𝐶𝐶𝐶2 = 𝐶𝐶𝐶𝐶3 = 2.5pF

𝒈𝒈𝒈𝒈𝒈𝒈 = 𝟒𝟒𝟒𝟒𝟒𝟒𝟒𝟒𝟒𝟒 𝒈𝒈𝒈𝒈𝒈𝒈 = 𝟏𝟏. 𝟒𝟒𝟒𝟒𝟒𝟒𝟒𝟒 𝒈𝒈𝒈𝒈𝒈𝒈 = 𝟑𝟑. 𝟓𝟓𝟓𝟓𝟓𝟓 𝒈𝒈𝒈𝒈𝒈𝒈 = 𝟒𝟒. 𝟗𝟗𝟗𝟗𝟗𝟗

• The ACM model for the transistor is defined by the following equations.

1 + √1 + 𝑖𝑖𝑖𝑖
1. 𝐼𝐼𝐼𝐼 = 𝑔𝑔𝑔𝑔 ∗ 𝑛𝑛 ∗ ∅𝑡𝑡
2
𝑔𝑔𝑔𝑔 1
2. 𝑊𝑊�𝐿𝐿 = � �
𝜇𝜇𝐶𝐶𝑂𝑂𝑂𝑂 ∅𝑡𝑡 √1 + 𝑖𝑖𝑖𝑖 − 1

𝜇𝜇∅𝑡𝑡
3. 𝑓𝑓𝑇𝑇 = �2√1 + 𝑖𝑖𝑖𝑖 − 1�
2𝜋𝜋𝐿𝐿2
For this design, we choose an appropriate Vdsat for each stage and compute the
corresponding inversion level, then we can compute the respective W/L for each
transistor.

Using this value and the gmi computed above, the aspect ratios of the transistors all the
transistors can be obtained from the equation 2 above.

𝑊𝑊� = 𝑔𝑔𝑔𝑔 � 1
𝐿𝐿 𝜇𝜇𝐶𝐶𝑂𝑂𝑂𝑂 ∅𝑡𝑡 √1 + 𝑖𝑖𝑖𝑖 − 1�

4th Stage – nmos input

�𝑾𝑾�𝑳𝑳�𝟒𝟒𝟒𝟒 = 𝟗𝟗𝟗𝟗

Hence,

�𝑾𝑾�𝑳𝑳�𝟒𝟒𝟒𝟒 = �𝑾𝑾�𝑳𝑳�𝟒𝟒𝟒𝟒 ∗ 𝟏𝟏/𝟑𝟑 = 𝟑𝟑𝟑𝟑

3rd Stage – nmos input

�𝑾𝑾�𝑳𝑳�𝟑𝟑𝟑𝟑 = 𝟕𝟕𝟕𝟕
 Hence,

�𝑾𝑾�𝑳𝑳�𝟑𝟑𝟑𝟑 = �𝑾𝑾�𝑳𝑳�𝟑𝟑𝟑𝟑 ∗ 𝟑𝟑 = 𝟐𝟐𝟐𝟐𝟐𝟐

2nd stage nmos input

�𝑾𝑾�𝑳𝑳�𝟐𝟐𝟐𝟐 = 𝟐𝟐𝟐𝟐

Hence,

�𝑾𝑾�𝑳𝑳�𝟐𝟐𝟐𝟐 = �𝑾𝑾�𝑳𝑳�𝟐𝟐𝟐𝟐 ∗ 𝟑𝟑 = 𝟔𝟔𝟔𝟔

1st Stage – pmos input

�𝑾𝑾�𝑳𝑳�𝟏𝟏𝟏𝟏 = 𝟏𝟏𝟏𝟏𝟏𝟏

Hence,

�𝑾𝑾�𝑳𝑳�𝟏𝟏𝟏𝟏 = �𝑾𝑾�𝑳𝑳�𝟏𝟏𝟏𝟏 ∗ 𝟏𝟏/𝟑𝟑 = 𝟒𝟒𝟒𝟒

These computed values are used for the first set of simulations of the amplifier, and are adjusted
as necessary to meet the required specifications.

Schematic for the Four -Stage NGCC

RESULTS

Magnitude and Phase Response, Gain = 76dB

DC Response showing offset, Input referred offset = 4.9mV

DC Response showing the Output swing and the Common mode Range

Output Swing = 1.61V and CMR = 1.6V

CMRR versus frequency, CMRR @dc = 68dB

PSRR– versus frequency, PSRR @ dc = 44.3dB

PSRR+ versus frequency, PSRR @ dc = 60dB

Transient response showing the settling time, Settling time = 1.155us

Negative Slew Rate, SR+ = 1.94V/us

Positive Slew Rate, SR+ = 1.58V/us

Current consumption in the design

Fully Differential Version

We implement two of the NGCC stages above together with a common mode feedback circuit to
obtain the fully differential version of the four stage NGCC.

Schematic of the Fully Differential Block

Implementation of the Fully Differential Four Stage NGCC Opamp

Results

Magnitude and Phase Response, Gain = 80.9dB GBW = 55MHz PM = 47deg

CMRR versus frequency, CMRR@dc = 117.2dB

PSRR- versus frequency, PSRR-@dc = 89dB

PSRR+ versus frequency, PSRR+@dc = 97dB

Transient Response, Settling time = 1.43u

Negative Slew Rate = -1.3V/us

 Positive Slew Rate = 5.12V/us

Specification Required Single output version Fully Differential

Power Supply 2V 2V 2V
Load 5pF 5pF 5pF
GBW 29MhZ 29MHz 55MHz
DC Gain 75dB 76dB 80.9dB
Phase Margin 70deg 69.6deg 47deg
Settling time minimum 1.155us 1.43us
Power Consumption minimum 1.38mW 2.59mW
Slew Rate (+/-) 10V/us -1.5/1.94 V/us -1.3/5.12 V/us
CMRR @DC - 68dB 117.2dB
PSRR(+/-)@DC - 60/44.3 dB 97/89 dB
COMMENTS

From the results shown in the table above, it is observed that with the implementation of the fully
differential version of the opamp, we boosted the GBW of the opamp and as well the DC gain
shot up by about 6dB which is consistent with theoretical deductions. However, the phase margin
is very bad for the fully differential version resulting in a longer settling time. It is also clear
from the table how CMRR and PSRR are generally far better for the differential opamp than for
the single ended. The fully differential is ideally balanced inherently so rejects all common mode
inputs. But the cost of that is about a double pay in power consumption.
PROBLEM 2: DESIGN OF DAMPING FACTOR CONTROLLED FREQUENCY
COMPENSATION AMPLIFIER (DFCFC1)

Topology of DFCFC1 Amplifier

General Design Procedure

The circuit has three gain stages with an extra two feed forward paths. The transconductances of
each stage are obtained as follows. DFCFC1 is defined by the following main conditions

𝟏𝟏. 𝒈𝒈𝒈𝒈𝒈𝒈𝒈𝒈 = 𝒈𝒈𝒈𝒈𝒈𝒈

𝒈𝒈𝒈𝒈𝒈𝒈
𝟐𝟐. 𝑪𝑪𝑪𝑪𝑪𝑪 = �𝟒𝟒�𝜷𝜷� . � �𝒈𝒈𝒈𝒈𝒈𝒈�

𝟑𝟑. 𝑪𝑪𝑪𝑪 𝑪𝑪𝑪𝑪𝑪𝑪 ≥ 𝑪𝑪𝑪𝑪𝑪𝑪 > 𝐶𝐶𝐶𝐶

𝑪𝑪𝑪𝑪
𝟒𝟒. 𝒈𝒈𝒈𝒈𝒈𝒈 = 𝜷𝜷. � � . 𝒈𝒈𝒈𝒈𝒈𝒈
𝑪𝑪𝑪𝑪

𝟓𝟓. 𝜷𝜷 = �𝟏𝟏 + 𝟐𝟐(𝑪𝑪𝑪𝑪⁄𝑪𝑪𝑪𝑪). (𝒈𝒈𝒈𝒈𝒈𝒈⁄𝒈𝒈𝒈𝒈𝒈𝒈)

 𝜷𝜷 𝑔𝑔𝑔𝑔3� 𝑔𝑔𝑔𝑔1�
• 𝐺𝐺𝐺𝐺𝐺𝐺 = � �4� . � 𝐶𝐶𝐶𝐶 � = 𝐶𝐶1 ≈ 29𝑀𝑀𝑀𝑀𝑀𝑀 𝐿𝐿𝐿𝐿𝐿𝐿 𝐶𝐶𝐶𝐶1 = 5𝑝𝑝𝑝𝑝,

𝑡𝑡ℎ𝑒𝑒𝑒𝑒 𝒈𝒈𝒈𝒈𝒈𝒈 = 𝟗𝟗𝟗𝟗𝟗𝟗𝟗𝟗𝟗𝟗 &

𝜷𝜷. 𝒈𝒈𝒈𝒈𝒈𝒈 = 𝟎𝟎. 𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎 … … … 𝟏𝟏

• 𝜷𝜷 is a constant that depends on the capacitive load and the output parasitic capacitance.
Assuming parasitic capacitance, Cp = 100fF, then

𝜷𝜷 = �𝟏𝟏 + 𝟐𝟐(𝑪𝑪𝑪𝑪⁄𝑪𝑪𝑪𝑪). (𝒈𝒈𝒈𝒈𝒈𝒈⁄𝒈𝒈𝒈𝒈𝒈𝒈) 𝑪𝑪𝑪𝑪 = 𝟓𝟓𝟓𝟓𝟓𝟓, 𝑪𝑪𝑪𝑪 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏

𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 𝑔𝑔𝑔𝑔1 = 𝑔𝑔𝑔𝑔2 𝑎𝑎𝑎𝑎𝑎𝑎 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓ℎ𝑒𝑒𝑒𝑒 𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔

𝟎𝟎. 𝟐𝟐
𝜷𝜷𝟐𝟐 = 𝟏𝟏 + … … … … 𝟐𝟐
𝒈𝒈𝒈𝒈𝒈𝒈

• Equations 1 & 2 are solved simultaneously to give

𝒈𝒈𝒈𝒈𝒈𝒈 = 𝟔𝟔𝟔𝟔𝟔𝟔𝟔𝟔 𝜷𝜷 = 𝟓𝟓𝟓𝟓

• 𝑔𝑔𝑔𝑔4 𝑖𝑖𝑖𝑖 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 𝑡𝑡ℎ𝑒𝑒 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒

𝑪𝑪𝑪𝑪
𝒈𝒈𝒈𝒈𝒈𝒈 = 𝒌𝒌. � � . 𝒈𝒈𝒈𝒈𝒈𝒈, 𝒈𝒈𝒈𝒈𝒈𝒈 = 𝟔𝟔𝟔𝟔𝟔𝟔𝟔𝟔 𝑪𝑪𝑪𝑪 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 𝑪𝑪𝑪𝑪 = 𝟓𝟓𝟓𝟓𝟓𝟓
𝑪𝑪𝑪𝑪

𝑡𝑡ℎ𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 𝒈𝒈𝒈𝒈𝒈𝒈 = 𝟕𝟕𝟕𝟕. 𝟓𝟓𝟓𝟓𝑺𝑺

For this design, we choose an appropriate Vdsat for each stage and compute the corresponding
inversion level, then we can compute the respective W/L for each transistor.
For the various stages and the gms associated with them, we can obtain the W/L for each
transistor.

For the 3rd Stage – nmos input

�𝑾𝑾�𝑳𝑳�𝟑𝟑𝟑𝟑 = 𝟑𝟑𝟑𝟑

Hence,

�𝑾𝑾�𝑳𝑳�𝟑𝟑𝟑𝟑 = �𝑾𝑾�𝑳𝑳�𝟑𝟑𝟑𝟑 ∗ 𝟑𝟑 = 𝟏𝟏𝟏𝟏𝟏𝟏

2nd stage nmos input

�𝑾𝑾�𝑳𝑳�𝟐𝟐𝟐𝟐 = 𝟑𝟑𝟑𝟑

Hence,

�𝑾𝑾�𝑳𝑳�𝟐𝟐𝟐𝟐 = �𝑾𝑾�𝑳𝑳�𝟐𝟐𝟐𝟐 ∗ 𝟑𝟑 = 𝟗𝟗𝟗𝟗

1st Stage – pmos input

�𝑾𝑾�𝑳𝑳�𝟏𝟏𝟏𝟏 = 𝟏𝟏𝟏𝟏𝟏𝟏

Hence,

𝟏𝟏
�𝑾𝑾�𝑳𝑳�𝟏𝟏𝟏𝟏 = �𝑾𝑾�𝑳𝑳�𝟏𝟏𝟏𝟏 ∗ = 𝟑𝟑𝟑𝟑
𝟑𝟑

The design was done based on these aspect ratios obtained but a little fine tuning was done to
meet the required specifications
Schematic of the DFCFC Opamp

Magnitude and Phase Response, Gain = 101.3dB

DC Response: Output swing = 1.65V, ICMR = 1.61V

DC Response, Input referred offset = 1.94mV

CMRR versus frequency, CMRR@ dc = 60dB

PSRR- versus frequency, PSRR- @ dc = 80dB

PSRR+ versus frequency, PSRR+ @ dc = 83dB

Transient Response, Settling time = 619ns

Negative Slew Rate = -4.9V/us

Positive Slew Rate = -3.3V/us

 Current consumption

PARAMETER SPECIFICATION SIMULATION

Avo 75 dB 101.3 dB
GBW 29 MHz 29 MHz
Phase Margin 70 deg 69 deg
Slew Rate 10 V/µs -4.9 V/µs (-ve)
3.3 V/µs (+ve)
Settling Time Minimum 619ns
CL 5 pF 5 pF
PSRR+ - 83 dB
PSRR- - 80 dB
CMRR (0) - 60 dB
Power Consumption Minimum 0.914 mW
Total Compensation
- 8pF
Capacitance
COMPARISON OF RESULTS – 3 STAGE DFCFC1 & 4 STAGE NGCC

PARAMETER SPECIFICATION DFCFC1 NGCC

Avo 75 dB 101.3 dB 76 dB
GBW 29 MHz 29 MHz 29 MHz
Phase Margin 70 deg 69 deg 69.6 deg
Slew Rate 10 V/µs -4.9 V/µs (-ve) 1.94 V/us (+ve)
3.3 V/µs (+ve) 1.5 V/us (-ve)
Settling Time Minimum 619 ns 1.155u
CL 5 pF 5 pF 5 pF
PSRR+ - 83 dB 60 dB
PSRR- - 80 dB 44.3 dB
CMRR (0) - 60 dB 68 dB
Power Consumption Minimum 0.914 mW 1.38 mW
Total Compensation 19 pF
- 8pF
Capacitance
CMR - 1.61 1.60
Output Swing - 1.65 1.61
Input referred offset - 4.9mV 1.94mV

COMMENTS

It can be observed from the table the differences between the two schemes of compensation.with
the three stage DFCFC we were able to achieve a gain of 101dB and about the same GBW and
phase margin as the four NGCC which has a gain of 76dB. The two have comparable DC
response but the input referred ioffset of the NGCC is better than that of the DFCFC. The
DFCFC o n the other hand uses much less compensation caps than the NGCC and much less
power ( about 40% less in this case) as well. But the main issue with this scheme is the
relatively bad rejection to common mode signals.
PROBLEM 3

Design of a three Stage NGCC based on the Settling Time Optimization techniques.

The closed loop transfer function of a three stage NGCC operational amplifier is given by :

Block Diagram of a three stage NGCC

𝐻𝐻(𝑠𝑠)
𝑔𝑔𝑚𝑚𝑚𝑚 2 − 𝑔𝑔𝑚𝑚2 𝐶𝐶𝑐𝑐2 𝑔𝑔𝑚𝑚𝑚𝑚 1 − 𝑔𝑔𝑚𝑚1 𝐶𝐶𝑐𝑐1 𝐶𝐶𝑐𝑐2 2
1+ 𝑠𝑠 +
𝑔𝑔𝑚𝑚3 𝑔𝑔𝑚𝑚2 𝑔𝑔𝑚𝑚1 𝑔𝑔𝑚𝑚3 𝑔𝑔𝑚𝑚2 𝑠𝑠
= 𝐻𝐻𝑜𝑜
𝐶𝐶 𝑔𝑔𝑚𝑚𝑚𝑚 2 − 𝑔𝑔𝑚𝑚2 𝐶𝐶𝑐𝑐2 𝑔𝑔𝑚𝑚3 + 𝑔𝑔𝑚𝑚𝑚𝑚 2 − 𝑔𝑔𝑚𝑚2 + 𝑓𝑓𝑔𝑔𝑚𝑚1 𝐶𝐶𝑐𝑐1 𝐶𝐶𝑐𝑐2 2 𝐶𝐶 𝐶𝐶 𝐶𝐶
1 + �𝑓𝑓𝑔𝑔𝑐𝑐1 + � 𝑠𝑠 + 𝑠𝑠 + 𝑓𝑓𝑔𝑔 𝑐𝑐1𝑔𝑔𝑐𝑐2 𝑔𝑔𝐿𝐿 𝑠𝑠 3
𝑚𝑚1 𝑔𝑔𝑚𝑚2 𝑔𝑔𝑚𝑚3 𝑓𝑓𝑔𝑔𝑚𝑚1 𝑔𝑔 𝑔𝑔
𝑚𝑚3 𝑚𝑚2 𝑚𝑚1 𝑚𝑚3 𝑚𝑚2

As per the compensation network design rules;

𝑔𝑔𝑚𝑚1 2
𝐶𝐶𝑐𝑐1 = 𝑓𝑓 �1 + � (1 + 2𝜌𝜌𝜁𝜁2 )𝐶𝐶𝐿𝐿
𝑔𝑔𝑚𝑚3 𝜌𝜌

𝑔𝑔𝑚𝑚2 2 (𝜌𝜌 + 2)2

𝑎𝑎𝑎𝑎𝑎𝑎 𝐶𝐶𝑐𝑐2 = 𝜁𝜁 𝐶𝐶
𝑔𝑔𝑚𝑚3 1 + 2𝜌𝜌𝜁𝜁2 𝐿𝐿
𝑝𝑝1
𝑤𝑤ℎ𝑒𝑒𝑒𝑒𝑒𝑒 𝜌𝜌 =
(𝜁𝜁𝜔𝜔𝑛𝑛 )

Where 𝜌𝜌 𝑎𝑎𝑎𝑎𝑎𝑎 𝜁𝜁 𝑎𝑎𝑎𝑎𝑎𝑎 𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 𝑡𝑡ℎ𝑎𝑎𝑎𝑎 𝑤𝑤𝑤𝑤𝑤𝑤𝑤𝑤 𝑏𝑏𝑏𝑏 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 𝑡𝑡𝑡𝑡 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡.

For the optimization of the settling time for a third order system,
 𝑠𝑠 𝑠𝑠
𝐺𝐺𝑜𝑜 �1 +� �1 +
𝑧𝑧1 𝑧𝑧2 �
𝐺𝐺𝐼𝐼𝐼𝐼𝐼𝐼 (𝑠𝑠) =
𝑠𝑠 𝜁𝜁 𝑠𝑠 2
�1 + 𝑝𝑝 � �1 + 2 𝜔𝜔 𝑠𝑠 + 2 �
1 𝑛𝑛 𝜔𝜔𝑛𝑛

To deal with the minimization problem systematically, it is instead convenient to consider the
following normalized system.
𝑠𝑠 𝑠𝑠
𝐺𝐺𝑜𝑜 �1 +
𝑋𝑋1 � �1 + 𝑋𝑋2 �
𝐺𝐺𝐼𝐼𝐼𝐼𝐼𝐼 (𝑠𝑠) = 𝑠𝑠
�1 + 𝜌𝜌� (1 + 2𝜁𝜁2 𝑠𝑠 + +𝜁𝜁2 𝑠𝑠 2 )

𝑝𝑝1 𝑧𝑧1 𝑧𝑧2

𝑤𝑤ℎ𝑒𝑒𝑒𝑒𝑒𝑒 𝜌𝜌 = 𝑎𝑎𝑎𝑎𝑎𝑎 𝑋𝑋1 = 𝑎𝑎𝑎𝑎𝑎𝑎 𝑋𝑋2 =
(𝜁𝜁𝜔𝜔𝑛𝑛 ) (𝜁𝜁𝜔𝜔𝑛𝑛 ) (𝜁𝜁𝜔𝜔𝑛𝑛 )

represent the relative real pole and zero locations with respect to the real part of the complex
poles 𝜁𝜁𝜔𝜔𝑛𝑛 , which is the normalizing factor.

From the above, it can be shown that the minimization problem to find the minimum settling
time for the third order system can be reduced to finding optimal values for ζ and ρ.

The absolute denormalized minimum settling time (MST) can be derived from the following:

𝑇𝑇𝑇𝑇𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼
𝑡𝑡𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 =
𝜁𝜁𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 𝜔𝜔𝑛𝑛

To obtain the parameters; 𝜌𝜌𝑜𝑜𝑜𝑜𝑜𝑜 𝑎𝑎𝑎𝑎𝑎𝑎 𝜁𝜁𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 𝑎𝑎𝑎𝑎𝑎𝑎 ℎ𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 𝑡𝑡𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 we need to do some sweep to
obtain these values based on the level of accuracy we want.

Based on these values we can obtain the required miller caps need to compensate the circuit to
achieve minimum settling time as shown in the equations Cc1 and Cc2 above.. This was done
and the results are shown below.

The miller caps obtained are used on the design of the three stage NGCC and the result shows a
better settling time than the previous one designed.
Schematic of the three stage NGCC

RESULTS

DC Response: Output swing = 1.58V, ICMR = 1.57V

 Dc Response: Input referred offset = 5.1mV

Magnitude and Phase Response, Gain = 72dB, GBW = 27.5M Hz, PM = 74deg
 CMRR versus frequency; CMRR@dc = 57dB

Transient showing setlling time; Settling time = 140ns

 With Settling Time
Specification Required Conventional Minimization
Technique
Power Supply 2V 2V 2V
Load 5pF 5pF 5pF
GBW 29MhZ 29MHz 27.5MHz
DC Gain 75dB 76dB 72dB
Phase Margin 70deg 69.6deg 74deg
Settling time minimum 1.155us 140ns
Power Consumption minimum 1.38mW 1.13mW
Slew Rate 10V/us 1.94V/us 4.9V/us

COMMENTS

With the design using the settling time minimization techniques, it is very obvious the difference
between the two settling times. While all other specs are comparable, the main difference
between the two is that the settling time of the conventional is about 10 times that of the new
technique and it consumes less power than the conventional. This certainly makes this a good
choice in the design of such amplifiers.
PROBLEM 4 : DESIGN USING THE 65nm CMOS TECHNOLOGY`

General Design Procedure

A new variable which depends on the relative location of the poles of the system to each other
will be used throughout the design. The general procedure for designing a 4th order system is
used here. The 3 stage is obtained by assuming f4 is at infinity. These are the ‘f’ variables. An N-
stage NGCC has N ‘f’ variables, as such the following 4 are used henceforth, f1, f2, f3 and f4.

The transfer function for the 4 stage NGCC can be represented by the following equation

𝐴𝐴𝑜𝑜
𝐻𝐻(𝑠𝑠) =
𝐴𝐴 𝑠𝑠 𝑠𝑠 2 𝑠𝑠 3
( 1 + 𝑓𝑓1𝑜𝑜 )(1 + 𝑓𝑓2 + 𝑓𝑓2𝑓𝑓3 + 𝑓𝑓2𝑓𝑓3𝑓𝑓4)

𝑤𝑤ℎ𝑒𝑒𝑒𝑒𝑒𝑒 𝐴𝐴𝑜𝑜 𝑖𝑖𝑖𝑖 𝑡𝑡ℎ𝑒𝑒 𝑑𝑑𝑑𝑑 𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔 𝑎𝑎𝑎𝑎𝑎𝑎 𝑓𝑓1, 𝑓𝑓2, 𝑓𝑓3 𝑎𝑎𝑎𝑎𝑎𝑎 𝑓𝑓4 𝑎𝑎𝑎𝑎𝑎𝑎 𝑡𝑡ℎ𝑒𝑒 𝑐𝑐𝑐𝑐𝑐𝑐 𝑜𝑜𝑜𝑜𝑜𝑜 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 𝑜𝑜𝑜𝑜 𝑒𝑒𝑒𝑒𝑒𝑒ℎ 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠

The stability criteria for this circuit can be fixed by using Routh-Hurwitz stability criterion on
the unity-feedback transfer function which is given by the below equation

1
𝐻𝐻𝐶𝐶𝐶𝐶(𝑠𝑠) =
𝑠𝑠 𝑠𝑠 2
𝑠𝑠 3 𝑠𝑠 4
+ + +
𝑓𝑓1 𝑓𝑓1𝑓𝑓2 𝑓𝑓1𝑓𝑓2𝑓𝑓3 𝑓𝑓1𝑓𝑓2𝑓𝑓3𝑓𝑓4

We obtain the following conditions for stability

𝑓𝑓4 > 𝑓𝑓2
𝑓𝑓2
𝑓𝑓4 >
𝑓𝑓1
1 − 𝑓𝑓3

Also phase margin can be approximated by the following equation if f3>f2 and f4>f2
ØM = 90 –arctan(GB/f2)

• The cutoff of the first stage,f1 is set equal to the required GBW and f2 is obtained from
the approximate expression of the phase margin.

𝒇𝒇𝒇𝒇 = 𝑮𝑮𝑮𝑮𝑮𝑮 ≅ 𝟕𝟕𝟕𝟕𝟕𝟕𝟕𝟕𝟕𝟕

 𝐺𝐺𝐺𝐺𝐺𝐺
∅𝑚𝑚 = 90° − tan−1 � � = 70° , 𝐺𝐺𝐺𝐺𝐺𝐺 = 30𝑀𝑀𝑀𝑀𝑀𝑀,
𝑓𝑓2

𝑡𝑡ℎ𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒, 𝒇𝒇𝒇𝒇 ≅ 𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑 = 𝟐𝟐𝟐𝟐𝟐𝟐 𝑴𝑴𝑴𝑴𝑴𝑴

• f3 and f4 are determined from the settling time and power requirement of the amplifier. A
sweep of f3 and f4 can be done versus normalized power and settling power and the
values of f3 and f4 that produces the minimum power and settling time and also meet the
condition for phase margin >70deg is chosen. Using the full expression for the phase
margin of the system, a numerical analysis can be performed to find optimum values of
f3 and f4 such that settling time is minimized while the phase margin is not degraded.
This can be performed using MATLAB. The code used is shown in Appendix A.
• To do that we need to choose values for the miller capacitors that we will use in the
compensation. We require the ratios between the miller caps and the load cap to
determine the normalized power for the MATLAB plots. For this design we use a miller
caps of 2.5pF.
• The phase margin is computed from the expression below
𝑮𝑮𝑮𝑮𝑮𝑮 𝟏𝟏 − 𝑮𝑮𝑮𝑮𝑮𝑮𝟐𝟐 ⁄𝒇𝒇𝒇𝒇. 𝒇𝒇𝒇𝒇
∅𝒎𝒎 = 𝟗𝟗𝟗𝟗° − 𝐭𝐭𝐭𝐭𝐭𝐭−𝟏𝟏 � � ��
𝒇𝒇𝒇𝒇 𝟏𝟏 − 𝑮𝑮𝑮𝑮𝑮𝑮𝟐𝟐 ⁄𝒇𝒇𝒇𝒇. 𝒇𝒇𝒇𝒇

Settling time is obtained using the general transfer function of a 4th order NGCC, connecting it in
unity feedback and taking the step response.
 f3 = 2.5*f2
15 5

10 4

5 3

0 2
1 2 3 4 5 6 7 8

f3 = 3*f2
15 5
Normalized Settling Time

10 4
Normalized Power
Settling Time
5 3

0 2
1 2 3 4 5 6 7 8

f3 = 3.5*f2
10 6

5 4

0 2
1 2 3 4 5 6 7 8
Normalized f4

Matlab Plot of variation of settling time and power versus f3 and f4

From the plots, we again choose f3 = 2.5*f2 and f4 = 3.5f2 since this choice optimizes both
settling time and power

Next we can determine the transconductance of each stage from the following equation:

𝑔𝑔𝑚𝑚𝑖𝑖
𝑓𝑓𝑓𝑓 = … … … … .1
2𝜋𝜋𝜋𝜋𝑚𝑚𝑖𝑖

𝒇𝒇𝒇𝒇 = 𝟕𝟕𝟕𝟕𝟕𝟕𝟕𝟕𝟕𝟕, 𝒇𝒇𝒇𝒇 = 𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐, 𝒇𝒇𝒇𝒇 = 𝟓𝟓𝟓𝟓𝟓𝟓𝟓𝟓𝟓𝟓𝟓𝟓 𝒂𝒂𝒂𝒂𝒂𝒂 𝒇𝒇𝒇𝒇 = 𝟕𝟕𝟕𝟕𝟕𝟕𝟕𝟕𝟕𝟕𝟕𝟕

𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 𝑡𝑡ℎ𝑒𝑒𝑒𝑒𝑒𝑒 𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣 𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 𝑒𝑒𝑒𝑒𝑒𝑒 1 𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔 𝑡𝑡ℎ𝑒𝑒 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 𝑔𝑔𝑔𝑔𝑔𝑔. 𝑎𝑎𝑎𝑎𝑎𝑎 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 𝐶𝐶𝐶𝐶1
= 𝐶𝐶𝐶𝐶2 = 𝐶𝐶𝐶𝐶3 = 1𝑝𝑝
 𝒈𝒈𝒈𝒈𝒈𝒈 = 𝟒𝟒𝟒𝟒𝟒𝟒𝟒𝟒𝟒𝟒 𝒈𝒈𝒈𝒈𝒈𝒈 = 𝟏𝟏. 𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑 𝒈𝒈𝒈𝒈𝒈𝒈 = 𝟑𝟑. 𝟑𝟑𝟑𝟑𝟑𝟑 𝒂𝒂𝒂𝒂𝒂𝒂 𝒈𝒈𝒈𝒈𝒈𝒈 = 𝟒𝟒. 𝟔𝟔𝟔𝟔𝟔𝟔

• The ACM model for the transistor is defined by the following equations.

1 + √1 + 𝑖𝑖𝑖𝑖
1. 𝐼𝐼𝐼𝐼 = 𝑔𝑔𝑔𝑔 ∗ 𝑛𝑛 ∗ ∅𝑡𝑡
2
𝑔𝑔𝑔𝑔 1
2. 𝑊𝑊�𝐿𝐿 = � �
𝜇𝜇𝐶𝐶𝑂𝑂𝑂𝑂 ∅𝑡𝑡 √1 + 𝑖𝑖𝑖𝑖 − 1

𝜇𝜇∅𝑡𝑡
3. 𝑓𝑓𝑇𝑇 = �2√1 + 𝑖𝑖𝑖𝑖 − 1�
2𝜋𝜋𝐿𝐿2
For this design, we choose an appropriate Vdsat for each stage and compute the
corresponding inversion level, then we can compute the respective W/L for each
transistor.

𝑊𝑊� = 𝑔𝑔𝑔𝑔 � 1
𝐿𝐿 𝜇𝜇𝐶𝐶𝑂𝑂𝑂𝑂 ∅𝑡𝑡 √1 + 𝑖𝑖𝑖𝑖 − 1�

The values for 𝜇𝜇𝐶𝐶𝑂𝑂𝑂𝑂 for nmos and pmos for the 65nm technology is extracted from
Cadence and the results found to be:

Kn = 540µ & Kp = 120µ

This is used in computing the aspect ratios for the various transistors in a similar manner
as was done in Problem 1

4th Stage – nmos input

�𝑾𝑾�𝑳𝑳�𝟒𝟒𝟒𝟒 = 𝟒𝟒𝟒𝟒

Hence,

�𝑾𝑾�𝑳𝑳�𝟒𝟒𝟒𝟒 = �𝑾𝑾�𝑳𝑳�𝟒𝟒𝟒𝟒 ∗ 𝟑𝟑 = 𝟏𝟏𝟏𝟏𝟏𝟏

3rd Stage – nmos input

 �𝑾𝑾�𝑳𝑳�𝟑𝟑𝟑𝟑 = 𝟑𝟑𝟑𝟑

Hence,

�𝑾𝑾�𝑳𝑳�𝟑𝟑𝟑𝟑 = �𝑾𝑾�𝑳𝑳�𝟑𝟑𝟑𝟑 ∗ 𝟑𝟑 = 𝟏𝟏𝟏𝟏𝟏𝟏

2nd stage nmos input

�𝑾𝑾�𝑳𝑳�𝟐𝟐𝟐𝟐 = 𝟏𝟏𝟏𝟏

Hence,

�𝑾𝑾�𝑳𝑳�𝟐𝟐𝟐𝟐 = �𝑾𝑾�𝑳𝑳�𝟐𝟐𝟐𝟐 ∗ 𝟑𝟑 = 𝟑𝟑𝟑𝟑

1st Stage – pmos input

�𝑾𝑾�𝑳𝑳�𝟏𝟏𝟏𝟏 = 𝟏𝟏𝟏𝟏𝟏𝟏

Hence,

�𝑾𝑾�𝑳𝑳�𝟏𝟏𝟏𝟏 = �𝑾𝑾�𝑳𝑳�𝟏𝟏𝟏𝟏 ∗ 𝟏𝟏/𝟑𝟑 = 𝟑𝟑𝟑𝟑

These computed values are used for the first set of simulations of the amplifier, and are adjusted
as necessary to meet the required specifications.
The schematic of the opamp is shown below

DC Response, Output Swing = 908mV and ICMR = 872mV

 DC Response, Input referred offset = 3.12mV

Magnitude ad Phase Response, Gain = 66dB GBW = 70.6MHz PM = 70 deg.

CMRR versus frequency, CMRR@dc = 53dB

PSRR- versus frequency, PSRR- @dc = 46dB

 PSRR+ versus frequency, PSRR+ @dc = 54dB

Transient Response showing settling behavior, settling time = 185ns

Transient Response, Negative Slew Rate = -7V/us

Transient Response, Negative Slew Rate = 5.2 V/us

Comparing Open Loop Response for a sinusoidal signal, with different DC levels.

For DC = -0.3V, 0 and 0.3 respectively from top to sown on the plot.

Current consumption
 SUMMARY OF RESULTS

Specification Required Single output version

Power Supply 1V 1V
Load 5pF 5pF
GBW 70MhZ 70.6MHz
DC Gain 55dB 66dB
Phase Margin 70deg 70deg
Settling time minimum 185ns
Power Consumption minimum 1.2mW
Slew Rate (+/-) 10V/us 5.2/-7 V/us
CMRR @DC - 53dB
PSRR(+/-)@DC - 54/46 dB
CMR - 872mV
Output Swing - 908mV
Input referred offset - 3.12mV

COMMENTS

We observe from the results here that almost all the specifications for the design were met except
for the slew rate specification. This is due to the very small amount of current used in the tail. To
increase the SR, more current should be pumped and that is also expensive. We realize that with
this small sized technologies, it is much easier to achieve very frequencies than with the long
channel technologies. But it comes at the cost of extra power.
REFERENCES

1. Edgar Sanchez-Sinencio, ECEN 607 Lecture 2: Nested Gm-C Amplifiers

2. K.N. Leung and P.K.T. Mok, “Analysis of Multistage Amplifier-Frequency Compensation”,

IEEE Trans. on Circuits and Systems I, Vol. 48, pp. 1041-1056

3. G. Palumbo and S. Pennisi, “Design Guidelines for Optimized Nested Miller Compensation”,
Southwest Symposium on Mixed Signal Design, 2000 SSMSC, pp. 97-102.

4. X. Fan, C. Mishra, and E. Sánchez-Sinencio, " Single Miller Capacitor Frequency

Compensation Technique for Low-Power Multistage Amplifiers” IEEE Journal of Solid-State
Circuits, Volume: 40 Issue: 3 , March 2005, Page(s): 584 -592.

5. Andrea Pugliese, Francesco Antonio Amoroso, Gregorio Cappuccino, Senior Member, IEEE, and
Giuseppe Cocorullo, Member, IEEESettling “Time Optimization for Three-Stage CMOS Amplifier
Topologies” IEEE Transactions On Circuits And Systems—I: Regular Papers, Vol. 56, No. 12,
December 2009

6. G. Xu, S. H. Embabi , P. Hao , E. Sanchez-Sinencio “A Low Voltage Fully Differential

Nested G,,Capacitance Compensation Amplifier: Analysis And Design”