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Experiment 5

The document outlines Experiment 5 for the Logic Design Lab, focusing on the implementation of a full adder. It explains the differences between a half-adder and a full-adder, detailing the inputs, outputs, and truth table for the full adder. Additionally, it describes how to construct the full adder using two half adders and provides tasks for determining Boolean expressions and implementing the circuit.

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4 views

Experiment 5

The document outlines Experiment 5 for the Logic Design Lab, focusing on the implementation of a full adder. It explains the differences between a half-adder and a full-adder, detailing the inputs, outputs, and truth table for the full adder. Additionally, it describes how to construct the full adder using two half adders and provides tasks for determining Boolean expressions and implementing the circuit.

Uploaded by

mrblowu998
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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University of Tabuk

Faculty of Computers & Information Technology


Semester I (1443 H – 2021/2022)
Subject Name and Code: Logic Design Lab (CEN 211)
Dr.Okba Omar Taouali

Student Name Student ID

Experiment 5: Implementation of Full Adder


This type of adder is a little more difficult to implement than a half-adder. The main difference
between a half-adder and a full-adder is that the full-adder has three inputs and two outputs. The first
two inputs are A and B and the third input is an input carry designated as CIN. When a full adder logic
is designed we will be able to string eight of them together to create a byte-wide adder and cascade the
carry bit from one adder to the next.
The output carry is designated as C and the normal output is designated as S. Take a look at the truth-
table.

A B CIN S C

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

From the above truth-table, the full adder logic can be implemented. We can see that the output S is
an EXOR between the input A and the half-adder SUM output with B and CIN inputs. We must also
note that the C will only be true if any of the two inputs out of the three are HIGH.

Thus, we can implement a full adder circuit with the help of two half adder circuits. The first will
half adder will be used to add A and B to produce a partial Sum. The second half adder logic can be
used to add CIN to the Sum produced by the first half adder to get the final S output. If any of the
half adder logic produces a carry, there will be an output carry. Thus, C will be an OR function of
the half-adder Carry outputs. Take a look at the implementation of the full adder circuit shown below.

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1- Determine the Boolean expression of the output S and C

2- Implement the circuit shown above and fill the following table:

A B CIN S (Sum) C (Carry)

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