2023-24 Odd Semester - ECL 303 Laboratory 3

Binary Code Decimal, Hexadecimal Number Representation

Name(s): Milan kumar Student number(s): Lab Section: A-1
BT21ECE015
1) Introduction
In this lab the seven segment display (SSD) will be used to output the results of a 4-bit binary word
in hexadecimal and then binary coded decimal output. A binary-coded-decimal (BCD) or a
hexadecimal to SSD converter display is simply a combinational circuit with 4 binary inputs and 7
outputs. The 4-bit input is the BCD representation of digits 0-9 and the hexadecimal representation
of digits 0-F and the. The 7-bit output is the state of each of SSD segments as shown in see in the
figure below. Note the representation of some digits like 1, 6, and 9 might be different from one
decoder to another.

Seven-segment displays (SSD) are commonly found on computers, watches, VCRs, and other
electronic devices to display numbers and characters. The seven-segment displays in the lab consist
of seven Light Emitting Diodes (LEDs) in the configuration of a number “8”. Different segments can
be illuminated to display different numbers and letters. The segments of a seven-segment display are
illustrated in the figure below. The SSDs, in general, come in packages with either a common anode
a A 1

B 2 a
f b
g C 3
f b
D 4
e c
E 5
g
d F 6 Comm on
Anode
e c
Vcc
G 7
d
Common-anode SSD
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 or a common cathode. The SSDs on the DE10 board are common-anode. In this format the LED turns
on with negative logic – i.e. low.

2) Instructions
Take a 4 bit input from the switches SW[3], SW[2], SW[1], and SW[0]. Display the binary number as
a BCD number on right most seven segment display HEX[0]. If the binary input number is greater
than 9, the letter E should be displayed.
a) Create a truth table and Karnaugh maps for the BCD-seven segment display

Decim BCD – input switches Segment

al
s3 s2 s1 s0 a b c d e f g

0 0 0 0 0 0 0 0 0 0 0 1

1 0 0 0 1 1 0 0 1 1 1 1

2 0 0 1 0 0 0 1 0 0 1 0

3 0 0 1 1 0 0 0 0 1 1 0

4 0 1 0 0 1 0 0 1 1 0 0

5 0 1 0 1 0 1 0 0 1 0 0

6 0 1 1 0 0 1 0 0 0 0 0

7 0 1 1 1 0 0 0 1 1 1 1

8 1 0 0 0 0 0 0 0 0 0 0

9 1 0 0 1 0 0 0 0 1 0 0

10 1 0 1 0 0 1 1 0 0 0 0

11 1 0 1 1 0 1 1 0 0 0 0

12 1 1 0 0 0 1 1 0 0 0 0

13 1 1 0 1 0 1 1 0 0 0 0

14 1 1 1 0 0 1 1 0 0 0 0

15 1 1 1 1 0 1 1 0 0 0 0

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a s1 s0 b s1 s0

s3 s2 00 01 11 10 s3 s2 00 01 11 10

00
0 1 0 0 00
0 0 0 0
1 0 0 0 0 1 0 1
01 01
0 0 0 0 1 1 1 1
11 11
0 0 0 0 0 0 1 1
10 10

𝑎= 𝑏=

0 0 0 1
1 0 0 0
1 1 1 1
0 0 1 1

0 1 0 0
1 0 1 0
0 0 0 0
0 0 0 0
c s1 s0 d s1 s0
s3 s2 00 01 11 10 s3 s2 00 01 11 10

10 𝑐= 10 𝑑=
e s1 s0 f s1 s0

s3 s2 00 00 01
01 11 10 s3 s2 11 10
0 1 1 0 0 0 1 1 1
1 1 1 0 01 1 0 1 0
0 0 0 0 11 0 0 0 0

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 0 1 0 0 0 0 0 0
00 00
01 01
11 11

00
01
11
10 10
𝑒= 𝑓=
g s1 s0
00 01 11 10
s3 s2
00 1 1 0 0
01 1 0 1 0
11 0 0 0 0
10
0 0 0 0
𝑔=

Sign of Faculty
b) Create the VHDL code to perform this BCD function and output using
simple combinational logic using dataflow style of modeling (i.e. AND,
OR, NOT, etc.) Compile your code and download it to the DE-10 board.

library IEEE;
use IEEE.std_logic_1164.ALL;

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entity numberRepresentation is
port (
s3, s2, s1, s0: in std_logic;
a, b, c, d, e, f, g: out std_logic
);
end numberRepresentation;

architecture bcd_7segment of numberRepresentation is begin a <= (NOT s3 AND NOT s2 AND

NOT s1 AND s0) OR (NOT s3 AND s2 AND NOT s1 AND NOT s0); b <= (s3 AND s2) OR (s3 AND

s1) OR (s2 AND NOT s1 AND s0) OR (s2 AND s1 AND NOT s0); c <= (s3 AND s2) OR (s3 AND s1)

OR (NOT s2 AND s1 AND NOT s0);

d <= (NOT s3 AND s2 AND NOT s1 AND NOT s0) OR (NOT s3 AND NOT s2 AND NOT s1 AND s0) OR
(NOT s3 AND s2 AND s1 AND s0); e <= (NOT s3 AND s0) OR (NOT s2 AND NOT s1 AND s0) OR

(NOT s3 AND s2 AND NOT s1); f <= (NOT s3 AND s1 AND s0) OR (NOT s3 AND NOT s2 AND s0) OR

(NOT s3 AND NOT s2 AND s1); g <= (NOT s3 AND NOT s2 AND NOT s1) OR (NOT s3 AND s2 AND

s1 AND s0); end bcd_7segment;

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c) Re-write this code using a “case” statement. Compile your code and
download it to the DE-10 board.
library IEEE;
use IEEE.std_logic_1164.all; --

Entity declaration

entity gate is
port(
x : in std_logic_vector(3 downto 0);
z : out std_logic_vector(6 downto 0)
);
end gate;

-- Architecture definition

architecture seven_segment of gate is

begin process(x)
begin
case x is
when "0000" =>z <="0000001"; when
"0001" =>z <="1001111"; when "0010" =>z
<="0010010"; when "0011" =>z
<="0000110"; when "0100" =>z
<="1001100"; when "0101" =>z
<="0100100"; when "0110" =>z
<="0100000"; when "0111" =>z
<="0001111"; when "1000" =>z
<="0000000"; when "1001" =>z
<="0000100";
when others =>z <="0110000"; end
case; end process;
end seven_segment;

Sign of Faculty
 d) Again using a case statement, re-write the code to display the hexadecimal
representations of the input switches. Comment on the two VHDL implementations
(dataflow style and using case statement).

library IEEE;
use IEEE.std_logic_1164.all;

-- Entity declaration

entity gate is
port(
x : in std_logic_vector(3 downto 0);
z : out std_logic_vector(6 downto 0)
);
end gate;

-- Architecture definition

architecture seven_segment of gate is

begin process(x)
begin
case x is
when "0000" =>z <="0000001"; when
"0001" =>z <="1001111"; when "0010" =>z
<="0010010"; when "0011" =>z <="0000110";
when "0100" =>z <="1001100"; when "0101"
=>z <="0100100"; when "0110" =>z
<="0100000"; when "0111" =>z <="0001111";
when "1000" =>z <="0000000"; when "1001"
=>z <="0000100"; when "1010" =>z
<="0000010"; when "1011" =>z <="1100000";
when "1100" =>z <="1100001"; when "1101"
=>z <="1000010"; when "1110" =>z
<="0110000"; when "1111" =>z <="0111100";

end case; end process;

end seven_segment;
Sign of Faculty
6 04-09-2023 Dr. M. B. Thacker
f) Using the push button KEY[0] to create an automatic/emergency shutoff for the circuit above. When the button is
depressed, the output (i.e. motor power) should be set to zero. The corresponding LEDs should reflect this change.
Use LED[5] to show the last state of the pushbutton (i.e. if the KEY[0] is pushed LED[5] should be on). Once the
button is released, the power should remain off until the button is pressed for the second time. The 2nd push will
allow the circuit to restart and operate again based on the input switches. Program the DE10-lite board and show
the working circuit to the faculty. The bush buttons are defined by “negative” logic: when pushed the value of
KEY[0] goes from high to low and vice versa. Therefore the sensitivity ist of the always block used to detect the
change in the level.

library IEEE; use

IEEE.std_logic_1164.all;

ENTITY washingmachine IS
PORT(W_POWER,X_DOOR,Y_WATER,Z_OVERFLOW:IN STD_LOGIC;
EM_BTN:IN STD_LOGIC;
F_MOTOR:OUT STD_LOGIC);
END washingmachine;

architecture BEHAV OF washingmachine IS

SIGNAL RES:STD_LOGIC;
BEGIN
RES<=W_POWER AND X_DOOR AND Y_WATER AND NOT Z_OVERFLOW;
TOGGLEING: PROCESS (EM_BTN)
VARIABLE T:BIT;
BEGIN
IF FALLING_EDGE(EM_BTN) THEN
T:= NOT T;
END IF;
IF T='0' THEN
F_MOTOR<=RES;
ELSE
F_MOTOR<='Z';
END IF;
END PROCESS;

END BEHAV;
1

Amplitude Shift Key (ASK) using 555 timer-IC

1). 1KHz pulse using first 555 IC

2). Ask output of frequency 5.3 KHz