Synchronous Sequential Logic

Part II

Logic and Digital System Design - CS 303

1
 State Reduction and Assignment
• In the design process of sequential circuits, certain
techniques are useful in reducing the circuit complexity
– state reduction
– state assignment
• State reduction
– Fewer states  fewer number of flip-flops
– m flip-flops  2m states
– Example: m = 5  2m = 32
• If we reduce the number of states to 21 do we reduce the
number of flip-flops?

2
 Example: State Reduction
0/0

a
0/0
1/0 Note that we use
0/0 0/0
letters to designate
b c 0/0 the states for
1/0 the time being
1/0

1/1 0/0
g d e

1/1
1/1
0/0 f

1/1
3
State Reduction Technique 1/7 0/0
a
1/0
• Step 1: get a state table b

present state next state Output

x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c c f 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1 5
 State Reduction Technique 2/7
• Step 2: Inspect the state table for equivalent states
– Equivalent states: Two states,
1. that produce exactly the same output
2. whose next states are identical
– for each input combination

6
 State Reduction Technique 3/7
present state next state Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c c f 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1

• States “e” and “g” are equivalent

• One of them can be removed 7
 State Reduction Technique 4/7
present state next state Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c c f 0 0
d e f 0 1
e a f 0 1
f e f 0 1

• We keep looking for equivalent states

8
 State Reduction Technique 5/7
present state next state Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c c d 0 0
d e d 0 1
e a d 0 1

• We keep looking for equivalent states

9
 State Reduction Technique 6/7

present state next state Output

x=0 x=1 x=0 x=1
a a b 0 0
b b d 0 0
d e d 0 1
e a d 0 1

• We stop when there are no equivalent states

10
 State Reduction Technique 7/7
0/0 present next state Output
state x=0 x=1 x=0 x=1
a
a a b 0 0
0/0 0/0
1/0 b b d 0 0
d e d 0 1
0/0 b e a d 0 1

1/0
1/0
0/0
d e

1/1 We need two flip-flops

1/1

state a a b b d e d d e a a
input 0 1 0 1 0 1 1 0 0 0 0
11
output 0 0 0 0 0 1 1 0 0 0
 State Assignments 1/4
• We have to assign binary values to each state
• If we have m states, then we need a code with
minimum n bits, where n = log2m
• There are different ways of encoding
• Example: Eight states: S0, S1, S2, S3, S4, S5, S6, S7
State Binary Gray One-hot
S0 000 000 00000001
S1 001 001 00000010
S2 010 011 00000100
S3 011 010 00001000
S4 100 110 00010000
S5 101 111 00100000
S6 111 101 01000000
S7 111 100 10000000 12
 State Assignments 2/4
• The circuit complexity depends on the state encoding
(assignment) scheme
• Previous example: binary state encoding

present state next state Output

x=0 x=1 x=0 x=1
(a) 00 00 01 0 0
(b) 01 01 10 0 0
(d) 10 11 10 0 1
(e) 11 00 10 0 1

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 0/0
State Assignments 3/4 a
0/0 0/0
1/0
• Gray encoding
0/0 b
1/0
1/0 0/0
d e
1/1

present state next state Output

x=0 x=1 x=0 x=1
(a) 00 00 01 0 0
(b) 01 01 11 0 0
(d) 11 10 11 0 1
(e) 10 00 11 0 1
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State Assignments 4/4

• One-hot encoding

present state next state Output

x=0 x=1 x=0 x=1
(a) 0001 0001 0010 0 0
(b) 0010 0010 0100 0 0
(d) 0100 1000 0100 0 1
(e) 1000 0001 0100 0 1
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 Designing Sequential Circuits
• Combinational circuits
– can be designed given a truth table
• Sequential circuits
– We need,
• state diagram or
• state table
– Two parts
• flip-flops: number of flip-flops is determined by the number
of states
• combinational part:
– output equations
– flip-flop input equations
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 Design Process
• Once we know the number of flip-flops, design process
is reduced to design process of combinational circuits
• Therefore, we can apply the techniques of
combinational circuit design
• The design steps
1. Given a verbal description of desired operation, derive
state diagram
2. Reduce the number of states if necessary and possible
3. State assignment

17
 Design Steps (cont.)
4. Obtain the encoded state table
5. Derive the simplified flip-flop input equations
6. Derive the simplified output equations
7. Draw the logic diagram
• Example: Verbal description
– “we want a (sequential) circuit that detects three or more
consecutive 1’s in a string of bits”
– Input: string of bits of any length
– Output:
• “1” if the circuit detects the pattern in the string
• “0” otherwise
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 Example: State Diagram
• Step 1: Derive the state diagram
0
1

S0 /0 S1/0

0 1 Moore Machine
0

S3/1 S2/0
1

1
19
 Synthesis with D Flip-Flops 1/5
• The number of flip-flops
– Four states
0
– 2 or 4 flip-flops 1

• State reduction S0 /0 S1/0

0
– not possible in this case
0 1
• State Assignment 0

– Use binary encoding S3/1 S2/0

1
• S0  00
1
• S1  01
• S2  10
• S3  11 20
 Synthesis with D Flip-Flops 2/5
• Step 4: Obtain the state table

0
1

Present state Input Next state Output

S0 /0 S1/0
A B x A B y
0
0 0 0 0 0 0
0 0 1 0 1 0 0 1
0
0 1 0 0 0 0
0 1 1 1 0 0 S3/1 S2/0
1
1 0 0 0 0 0
1 0 1 1 1 0 1
1 1 0 0 0 1
1 1 1 1 1 1

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 Synthesis with D Flip-Flops 3/5
• Step 5: Choose the flip-flops
– D flip-flops
• Step 6: Derive the simplified flip-flop input equations
– Boolean expressions for DA and DB

Present state Input Next state Output

A B x A B y Bx
0 0 0 0 0 0 A 00 01 11 10
0 0 1 0 1 0
0 0 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0 1 0 1 1 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
DA = Ax + Bx
1 1 1 1 1 1 22
 Synthesis with D Flip-Flops 3/5
Present state Input Next state Output Bx
A B x A B y
A 00 01 11 10
0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 0 0
0 1 0 0 0 0 1 0 1 1 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
DB = Ax + B’x
1 1 0 0 0 1
1 1 1 1 1 1

Bx
• Step 7: Derive the simplified A 00 01 11 10
output equations 0 0 0 0 0
– Boolean expressions for y. 1 0 0 1 1
y = AB 23
 Synthesis with D Flip-Flops 5/5
• Step 8: Draw the logic diagram
DA = Ax + Bx DB = Ax + B’x y = AB

x DA A
D Q

C
R

y
DB B
D Q

C
R

clock reset 24
 Sequential Circuit Timing 1/3
• It is important to analyze the timing behavior of a
sequential circuit
– Ultimate goal is to determine the maximum clock frequency

clk
D Q
ts th
C
R
D

tp, FF 38
 Sequential Circuit Timing 2/3
tp

clk

tp,FF tp,COMB ts

Combinational Circuit tp tp,FF + tp,COMB + ts

inputs outputs
tp,COMB

current
state Flip-Flop
Flip-Flops inputs
Q D
tp,FF
ts
clock C 39
 Sequential Circuit Timing 2/3
tp

clk

tp,FF tp,COMB ts

Combinational Circuit tp,FF + tp,COMB >> th

inputs outputs
tp,COMB

current
state Flip-flop
Flip-flops inputs
Q D
tp,FF

clock C 40
 Sequential Circuit Timing 3/3
• Minimum clock period (or maximum clock frequency)

tp

clk

tp,FF tp,COMB ts

tp

clk

tp,FF tp,COMB ts
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 Example
Binary encoding

S0 S3
D Q x1
C

S1 S2

tp,XOR = 2.0 ns D Q x0
C
tp,FF = 2.0 ns x0’
ts = 1.0 ns

tp = tp,FF + tp,XOR + ts = 2.0 + 2.0 + 1.0 = 5.0 ns

fmax = 1/tp = 1/(5.0×10-9) 200 MHz 42

 Example: One-Hot-Encoding
S0  0001 a0
D Q X0
S1  0010
C
S2  0100
S3  1000
a1
D Q
C
tp,FF = 2.0 ns
ts = 1.0 ns a2
D Q
C
tp = tp,FF + ts = 2.0 + 1.0 = 3.0 ns
a3 X1
fmax = 1/tp = 1/(3.0×10-9) 333 MHz D Q
C

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 State-Diagram Based HDL Models
• always @ () statement
– For clocked sequential circuits we use “always @ ()” statement
– Inside we have signals such as “clock” and “reset”
– always @ () statement may have a number of “edge events”
• Examples:
// D flip-flop
module DFF(output reg Q, input D, clk, reset);
always @(posedge clk, posedge reset)
if (reset == 1) Q <= 1’b0;
else Q <= D;
endmodule
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 State-Diagram Based HDL Models
// T flip-flop
module TFF(output reg Q, input T, clk, reset);
always @(posedge clk, negedge reset)
if (reset == 0) Q <= 1’b0;
else Q <= T ^ Q;
endmodule
module T (output reg Q, input T, input C);
always @(C or T)
if (C == 1)
Q <= T ^ Q;
endmodule

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 Sequential Circuit Design with Verilog
• Zero detector circuit
– The circuit detects a 0 following a sequence of 1s in a serial bit
stream.
– For instance,
• …10  1,
• …110  1,
• …00  0
• …01  ? 1/0

0/0 LBZ LBO 1/0

0/1 51
 Zero Detector Circuit
module zero_detector(output reg y, input x, clk, reset);
reg state, next_state;
parameter LBZ = 1’b0, LBO = 1’b1; 1/0
0/0 1/0
always @(posedge clk, negedge reset)
if (reset == 0) state <= LBZ; LBZ LBO
Sequential
else state <= next_state; Part
0/1
always @(state, x)
case(state) inputs outputs

LBZ: if(~x) next_state = LBZ; else next_state = LBO; Combinational

LBO: if(~x) next_state = LBZ; else next_state = LBO;
endcase state
Q D
always @(state, x)
clock Sequential FF
case(state) C inputs
LBZ: y = 0; LBO: y = ~x;
endcase Combinational Part
endmodule 52
 Zero Detector Circuit (Moore Model)
Mealy Model
1/0
0/0 1/0
LBZ LBO

0/1

0 1
ZAZ/0 LBO/0
1

0
OAZ/1 0

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 Zero Detector Circuit (Moore Model)
module zero_detector(output reg y, input x, clk, reset);
reg[1:0] state;
parameter ZAZ = 2’b00, LBO = 2’b01, OAZ = 2’b10;
1
always @(posedge clk, negedge reset) 0 1
if (~reset) state <= ZAZ;
ZAZ/0 LBO/0
else case(state) 1
ZAZ: if(~x) state <= ZAZ; else state <= LBO;
LBO: if(~x) state <= OAZ; else state <= LBO;
0 OAZ/1 0
OAZ: if(~x) state <= ZAZ; else state <= LBO;
endcase
always @(state)
case(state)
ZAZ, LBO: y = 0;
OAZ: y = 1;
endcase
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endmodule