DECADE OF

EXCELLENCE
IN
VLSI TRAINING

4000+

HANDS-ON LEARNING WITH INDUSTRY STANDARD EDA TOOLS

ADVANCED VLSI PHYSICAL DESIGN

AND VERIFICATION COURSE
MAVEN SILICON
Evolved in VLSI Technologies, Maven Silicon is a VLSI Training company that offers a wide range of corporate and professional training services. Maven Silicon is
the only training company in India that offers SystemVerilog and UVM based advanced verification courses and holds the credit of training 500+ engineers per
year. With shrinking process technologies, ever-growing design sizes, and increasing integration of IP to a single chip, verification has become an extremely
complex and critical part of any SoC design today. As chip verification consumes 60% of the design cycle, most of the VLSI companies hire fresh VLSI engineers
who have extensively been trained on ASIC verification methodologies and technologies and have dedicated themselves only to chip verification.

Usually, 70% of the engineers in any product or services company dedicated only to functional verification, and the remaining 30% of the engineers work on
RTL design, STA and Analog, etc. So there are plenty of job opportunities for fresh VLSI engineers who are highly skilled in ASIC verification. We at Maven Silicon
have designed the courses keeping this fact in our mind. You can leverage our expertise and be a part of a world-class training infrastructure to learn the VLSI
technologies and then get a job into the best semiconductor companies.

Our CEO, Sivakumar P R, has 22+ years of experience in the engineering and semiconductor industries. He has worked as a Verification Consultant in the top
EDA companies like Synopsys, Cadence, and Mentor Graphics. During this tenure, he worked very closely with various ASIC and FPGA design houses and helped
them to use the EDA solutions effectively for the successful tape-outs of multi-million gate designs.

To know more about our CEO, visit https://www.linkedin.com/in/sivapr/

FIVE REASONS TO MUSE ON MAVEN SILICON INCLUDES,

1. SystemVerilog and UVM based Advanced Verification
Maven Silicon, as the training centre, edifies engineers on the advanced ASIC Verification methodologies and SystemVerilog. In addition to these advanced
technologies, we also impart the basic VLSI technologies like Advanced Digital Design Methodology, Verilog, ASIC & FPGA's design flow, STA & CMOS
fundamentals.

2. Course Delivered by Industry Experts

As the courses are composed of advanced VLSI design and verification technologies, only experienced VLSI engineers can deliver and give an enriched learning
experience. At Maven Silicon, industry experts share their experience and guide you on enhancing your skills in VLSI Industries.

3. Superior Training Methodology

At Maven Silicon, the experienced engineers who work in the top semiconductor industries share their experiences with you and simulate their expertise to help
you learn via real-time scenarios. Only 30% of 900 hours of VLSI-RN course is dedicated to imparting concepts, and the remaining 70% for labs, mini-projects,
and final projects.

4. Excellent Placement Assistance

Maven Silicon offers placement support through a non-commercial placement cell, which regularly taps job opportunities in leading semiconductor companies.
We work closely with various VLSI product and services companies and identify the right opportunities for the students who successfully complete our training
program.
Most of our students have been successfully placed in renowned semiconductor companies. We're dedicated to the success of our trainees.

5. Excellent work environment

We provide an excellent work environment, which has adequate hardware and software infrastructure. Maven Silicon has chosen Mentor Graphics as its EDA
partner and provides great opportunities to engineers to work on verification platforms like Questa and explore the advanced ASIC verification technologies and
methodologies.

Maven Silicon has set the benchmark for VLSI Training by offering the best-curated package comprised of a holistic curriculum, standard
training methodologies, modern infrastructure, and excellent customer service.

EDA PARTNER - MENTOR GRAPHICS

Mentor Graphics is a leader in Electronic Design Automation. Its innovative products and solutions help engineers conquer design challenges in the seemingly
daunting world of board and chip design.
To know more about Mentor Graphics, please visit https://eda.sw.siemens.com/en-US

Delivered by Industry Experts Certification on completion Live Q&A sessions

WhatsApp Support Group 24/7 Lab Access

ADVANCED VLSI PHYSICAL DESIGN AND VERIFICATION COURSE
MODULE 1 [2] Data Types
Expression Coverage
Introduction to VLSI Type Concept
Path Coverage
Nets and registers
VLSI Design Flow Toggle Coverage
Non-hardware equivalent variables
ASIC Vs FPGA FSM - State, Transition and Sequence coverage
Arrays
RTL Design Methodologies
Introduction to ASIC Verification Methodologies [3] Verilog Operators
VLSI Design Flow Steps – Demo Logical operators MODULE 9
Bitwise and Reduction operators
Concatenation and conditional Verilog Mini Project RTL Coding and Synthesis
MODULE 2 Relational and arithmetic
Project Specification Analysis
Introduction to Linux Shift and Equality operators
Understanding the architecture
Operators precedence
Components of UNIX system Module level implementation and verification
Directory Structure [4] Assignments Building the top-level module
Utilities and Commands Type of assignments Implementing the design into the FPGA board
Vi Editor Continuous assignments
Timing references
Procedures MODULE 10
MODULE 3 Blocking and Non-Blocking assignments Design Automation using Scripts Perl
Advanced Digital Design Execution branching
Tasks and Functions Introduction to Perl
Introduction to Digital Electronics Functions and Statements
[5] Finite State Machine
Arithmetic Circuits Numbers, Strings, and Quotes
Basic FSM structure
Data processing Circuits Comments and Loops
Moore Vs Mealy
Universal Logic Elements
Common FSM coding styles
Combinational Circuits - Design and Analysis
Registered outputs
Latches and Flip flops MODULE 11
Shift Registers and Counters [6] Advanced Verilog for Verification
Sequential Circuits - Design and Analysis System Tasks Introduction to Physical Design
Memories and PLD Internal variable monitoring
Compiler directives [1] Introduction - Overview
Finite State Machine
File input and output [2] Digital Representation (Y-Chart)
Microcontroller Design
[3] VLSI Design Flow
[7] Synthesis Coding Style [4] Physical Design
MODULE 4 Registers in Verilog [5] Various Design Styles
Unwanted latches [6] Which Design style to use
Static Timing Analysis Operator synthesis [7] Description of Physical Design
Introduction to STA RTL Coding style Floorplan
Comparison with DTA Placement
Timing Path and Constraints Routing
Different types of clocks MODULE 7 Static Timing Analysis
Clock domain and Variations Signal Integrity and Cross Talk Issues
[1] PLD
Clock Distribution Networks Clock and Power Routing Issues
General Structure and Classification
How to fix timing failure Physical Verification & Design Signoff
CPLD Vs FPGA
[8] Partitioning
[2] Xilinx CPLD - Xc9500
MODULE 5 Block Diagram of CPLD
Detailed study of each block MODULE 12
CMOS Devices and Technology
Endurance limits
Floor Planning
Non Ideal characteristics Timing Model
BJT vs FET What is FLOOR PLANNING ?
[3] Xilinx FPGA
CMOS Characteristics Several criteria used to measure the quality of
FPGA Architecture
CMOS circuit design Floorplans
CLBs and Input/Output Blocks
Transistor sizing Floorplanning Algorithms
Luts, SLICE DFFs
Layout and Stick Diagrams Inputs required
Dedicated MUXes
CMOS Processing Steps How to qualify Import Design?
Programmable Interconnects
Fabrication What is required to come with a good
Architectural Resources
CMOS Technology - Current Trends floorplan?
Power Distribution and Configuration
Types of floorplan techniques used in Full Chip
[4] FPGA Architecture of Different Xilinx Families plan
MODULE 6
[5] Netlist and Timing simulation Floorplan Steps
Verilog HDL - RTL Coding and Synthesis How to qualify Floorplan?
Types of floorplan techniques used in Full Chip
[1] Introduction to Verlog HDL MODULE 8 plan
Applications of Verilog HDL
Verilog HDL language concept Code Coverage
Verilog language basics and constructs Statement coverage
Abstraction levels Branch Coverage
ADVANCED VLSI PHYSICAL DESIGN AND VERIFICATION COURSE
MODULE 13 MODULE 16 RTL coding in Verilog
Floor planning
[1] Placement Physical Verification & sign-off
Timing Analysis
Introduction Design Rule Check (DRC) Place & Route the netlist
Different criteria’s driving the placement Typical DRC rules Timing Simulation
process Layout versus Schematic (LVS) Physical Verification and Signoff
Different tasks in placement How LVS works
Goals of placement Commonly faced LVS issues
MODULE 20
Things to be checked before placement •R Drop Analysis
Pre-placement Electro Migration Business communication
Different Timing optimization techniques Methods to fix EM
Transition from College to Corporate
How to qualify placement
Interpersonal skills and Presentation Skills
How to qualify Floorplan? MODULE 17 Email Etiquette
Types of floorplan techniques used in Full Chip
Resume writing
plan RISC V Processor
Interview Skills: Group Discussion and HR
[2] Routing [1] RISC-V Instruction Set Architecture Round Preparation
The different tasks that are performed in the RISC-V processor overview Mockup Interviews Technical/HR
routing stage RISC-V ISA Overview
Goals of Routing RV32I – R and I Type Instruction
Routing Constraints RV32I – S and B Type Instructions INDUSTRY STANDARD PROJECTS
RV32I – J and U Type Instructions Systems: RISC-V SoC – Physical Design
RV32I – Assembly Programs
MODULE 14 Systems: ARM SoC - Physical Design
[2] RISC-V RV32I RTL Architecture Design Systems: RISC-V SoC – DFT Implementation
Clock Tree Synthesis
RISC-V Execution Stages and Flow Systems: ARM SoC – DFT Implementation
Sanity checks need to be done before CTS IPs: RISC-V, SPI, UART, I2C
RISC-V Register File and RV32I Instructions
Preparations
Format
Difference between High Fan-out Net Synthesis
RV32I – R and I Type ALU Datapath
(HFNS) & Clock Tree Synthesis
RV32I – S Type ALU Datapath - Load and Store
Why buffers/inverters are inserted?
What is the difference between clock buffer
RV32I – B and U Type ALU Datapath ELECTIVE MODULE
RV32I – J Type ALU Datapath – JAL and JALR
and normal buffer? Design for Testability - DFT
CTS Goals [3] RISC-V RV32I 5 Stage Pipelined RTL Design
Introduction to DFT
Clock Tree Design Rule Constraints CPU Performance and RISC-V 5 Stage Pipeline
Types of Testing
Clock Tree Exceptions Overview
Basic Testing Principles
RISC-V 5 Stage Pipeline – Data Hazards and
Fault Collapsing
MODULE 15 Design Approach
DFT Techniques - Ad-hoc Techniques
RISC-V 5 Stage Pipeline – Control Hazards and
Signal Integrity and Cross-Talk Issues Structured Techniques
Design Approach
BIST & boundary Scan
Signal Integrity
Introduction to Tessent Shell
Concerns addressed by signal integrity
MODULE 18 System Modes and TSDB
Factors effecting signal integrity
Cross Talk Noise
Signal Integrity and Cross-Talk Issues
Cross Talk Delay
Guest Lectures by Industry Experts EDA TOOLS
Noise Analysis and Layout Compaction
Layout Compaction Mentor Graphics
Xilinx
Features MODULE 19
Design Style Specific Issues Aldec
Assertion Based Verification - SVA
Compaction Algorithms
Design specification analysis
Creating the design architecture
Partitioning the design

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