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Lecture #03 - Characteristics of Timing Arc - Part #01 - Delay

The document provides an overview of Static Timing Analysis (STA) focusing on the characteristics of timing arcs, specifically delay, unateness, and slew. It details the components of delay, including cell delay and net delay, and explains how these are influenced by intrinsic delay, load, and input transition. Additionally, it mentions the use of wire-load models to calculate net delay and highlights the availability of timing information in liberty files.

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2 views

Lecture #03 - Characteristics of Timing Arc - Part #01 - Delay

The document provides an overview of Static Timing Analysis (STA) focusing on the characteristics of timing arcs, specifically delay, unateness, and slew. It details the components of delay, including cell delay and net delay, and explains how these are influenced by intrinsic delay, load, and input transition. Additionally, it mentions the use of wire-load models to calculate net delay and highlights the availability of timing information in liberty files.

Uploaded by

akumar14
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Static Timing Analysis (STA)

Lecture #03: Characteristics of Timing Arc (Part #01) - Delay

Video Lecture Link

13-01-2023 VLSI Design - Gyan Chand Dhaka 1


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Static Timing Analysis (STA) – Characteristics of Timing Arc

Characteristics of Timing Arc :


1) Delay
2) Unateness
3) Slew
Note : All the above information of timing arc are derived from Timing Library

13-01-2023 VLSI Design - Gyan Chand Dhaka 2


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Static Timing Analysis (STA) – Characteristics of Timing Arc

1) Delay:
A) Cell Delay
B) Net Delay

A) Cell Delay :
The delay through a cell is determined by -
i) The intrinsic delay
ii) The load that it is driving and
iii) The input transition, also known as input slew

13-01-2023 VLSI Design - Gyan Chand Dhaka 3


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Static Timing Analysis (STA) – Characteristics of Timing Arc


Lets have a look at below pictures for an inverter cell -

Timing Arc

Input(X) Output(Y)

Falling Edge Rising Edge

Cell Delay

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Static Timing Analysis (STA) – Characteristics of Timing Arc

Input Transition (H - L) Timing Arc

Input(X) Output(Y)

Load

Falling Edge Rising Edge


Intrinsic Delay

Cell Delay

Cell Delay = Transition Delay + Intrinsic Delay

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Static Timing Analysis (STA) – Characteristics of Timing Arc

Transition Delay : The time it takes for the pin to change state from LOW to HIGH or HIGH to LOW

Intrinsic Delay : Cell Delay when a signal with a zero transition time is applied to the input pin and the
output pin does not have any load

By default, STA tools measure the cell delay from 50% of the input signal to 50% of the output signal

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Static Timing Analysis (STA) – Characteristics of Timing Arc

B) Net Delay :
- It appears because of the resistance and the capacitance of inter-connect
- Wire-Load Models[WLM] are used to calculate the net delay
- The delay is calculated based on the block area specification in WL Model
- Next Lecture explains WLM Model with example

Note: Timing information for all the cells is available in liberty (.lib) files

13-01-2023 VLSI Design - Gyan Chand Dhaka 7


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Best Free VLSI Content

1. Verilog HDL Crash Course – Link


2. Static Timing Analysis (STA) – Theory Concepts – Link
3. Static Timing Analysis (STA) – Practice/Interview Questions – Link
4. Low Power VLSI Design – Theory Concepts – Link
5. Low Power VLSI Design (LPVLSI) – Practice/Interview Questions – Link
6. Digital ASIC Design Verilog Projects – Link

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