HCPL-2400, HCPL-2430

20 MBd High CMR Logic Gate Optocouplers

Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product

Description Features
The HCPL-2400 and HCPL-2430 high speed opto-cou- • High speed: 40 MBd typical data rate
plers combine an 820 nm AlGaAs light emitting diode • High common mode rejection:
with a high speed photodetector. This combina-tion re- HCPL-2400: 10 kV/µs at VCM = 300 V (typical)
sults in very high data rate capability and low input cur-
rent. The totem pole output (HCPL-2430) or three state • AC performance guaran­teed over temperature
output (HCPL-2400) eliminates the need for a pull up re- • High speed AlGaAs emitter
sistor and allows for direct drive of data buses. • Compatible with TTL, STTL, LSTTL, and HCMOS logic
The detector has optical receiver input stage with built- families
in Schmitt trigger to provide logic compatible wave- • Totem pole and tri state output (no pull up resistor
forms, eliminating the need for additional waveshaping. required)
The hysteresis provides differential mode noise immuni-
• Safety approval
ty and mini­mizes the potential for output signal chatter.
– UL recognized – 3750 V rms for 1 minute per
The electrical and switching characteristics of the HCPL- UL1577
2400 and HCPL-2430 are guaranteed over the tempera-
ture range of 0°C to 70°C. – IEC/EN/DIN EN 60747-5-2 approved with
VIORM = 630 V peak (Option 060) for HCPL-2400
Functional Diagram – CSA approved
HCPL-2400/11 HCPL-2430 • High power supply noise immunity
VCC
1 NC 8 ANODE 1 1 8 VCC • MIL-PRF-38534 hermetic version available
2 7 CATHODE 1 2 7 VO1
(HCPL-5400/1 and HCPL-5430/1)

3 6 CATHODE 2 3 6 VO2 Applications

4 NC 5 ANODE 2 4 5 GND
• Isolation of high speed logic systems
GND
• Computer-peripheral interfaces
TRUTH TABLE
(POSITIVE LOGIC)
• Switching power supplies
LED ENABLE OUTPUT TRUTH TABLE • Isolated bus driver (networking applications)
ON L L (POSITIVE LOGIC)
OFF L H LED OUTPUT • Ground loop elimination
ON H Z ON L
OFF H Z OFF H • High speed disk drive I/O
A 0.1 µF bypass capacitor must be connected between pins 5 and 8. • Digital isolation for A/D, D/A conversion
• Pulse transformer replacement
HCPL-2400 Functional Diagram

CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
These optocouplers are compatible with TTL, STTL, LSTTL, and HCMOS logic families. When Schottky type TTL devices
(STTL) are used, a data rate performance of 20 MBd over temperature is guaranteed when using the application cir-
cuit of Figure 13. Typical data rates are 40 MBd.

Selection Guide
     8-Pin DIP (300 Mil)    Minimum CMR
Single Dual Minimum Input Maximum
Channel Channel dV/dt VCM On Current Propagation Delay Hermetic
Package Package (V/µs) (V) (mA) (ns) Package
HCPL-2400 1000 300 4 60
HCPL-2430 1000 50 4 60
500 50 6 60 HCPL-540X*
500 50 6 60 HCPL-543X*
500 50 6 60 HCPL-643X*

*Technical data for the Hermetic HCPL-5400/01, HCPL-5430/31, and HCPL-6430/31 are on separate Avago publications.

Ordering Information
HCPL-2400 and HCPL-2430 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part RoHS Non RoHS Surface Gull Tape UL 5000 Vrms/1 IEC/EN/DIN EN
number Compliant Compliant Package Mount Wing & Reel Minute rating 60747-5-2 Quantity
-000E No option 50 per tube
-300E #300 X X 50 per tube
HCPL-2400 300mil
-500E #500 X X X 1000 per reel
DIP-8
-060E #060 X 50 per tube
-360E -360 X X X 50 per reel
-000E No option 50 per tube
-300E #300 X X 50 per tube
300mil
HCPL-2430 -500E #500 X X X 1000 per reel
DIP-8
-020E - X 50 per tube
-060E - X 50 per tube

To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-2430-500E to order product of Gull Wing Surface Mount package in Tape in RoHS compliant.
Example 2:
HCPl-2400 to order product of 8-Pin DIP package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE‘.


Schematic
ICC
VCC
8

IO
1 IF1
+ VO1
VF1 7
ICC 8
VCC –
2
IE 7
2 IF VE
ANODE IO 6
+ VO
VF
–
CATHODE
3 5 IO
GND 3
– VO2
VF2 6
+
4 IF2
5
GND
TRUTH TABLE SHIELD
(POSITIVE LOGIC)
LED ENABLE OUTPUT TRUTH TABLE
ON L L (POSITIVE LOGIC)
OFF L H LED OUTPUT
ON H Z ON L
OFF H Z OFF H

HCPL-2400 Schematic


Package Outline Drawings
8-Pin DIP Package (HCPL-2400, HCPL-2430)

9.65 ± 0.25 7.62 ± 0.25

(0.380 ± 0.010) (0.300 ± 0.010)

TYPE NUMBER 8 7 6 5 6.35 ± 0.25

OPTION CODE*
(0.250 ± 0.010)
A XXXXZ DATE CODE

YYWW RU
UL
1 2 3 4 RECOGNITION

1.78 (0.070) MAX.

1.19 (0.047) MAX.

+ 0.076
5° TYP. 0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
3.56 ± 0.13 4.70 (0.185) MAX.
(0.140 ± 0.005)

0.51 (0.020) MIN.

2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES).
*MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
1.080 ± 0.320 0.65 (0.025) MAX.
(0.043 ± 0.013) NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
2.54 ± 0.25
(0.100 ± 0.010)

8-Pin DIP Package with Gull Wing Surface Mount Option 300
(HCPL-2400, HCPL-2430)
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010) 1.016 (0.040)

8 7 6 5

6.350 ± 0.25
10.9 (0.430)
(0.250 ± 0.010)

1 2 3 4

2.0 (0.080)
1.27 (0.050)

1.780 9.65 ± 0.25

(0.070) (0.380 ± 0.010)
1.19 MAX.
(0.047) 7.62 ± 0.25
MAX. (0.300 ± 0.010)
+ 0.076
0.254 - 0.051
3.56 ± 0.13 + 0.003)
(0.140 ± 0.005) (0.010 - 0.002)

1.080 ± 0.320
(0.043 ± 0.013) 0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
2.54 0.635 ± 0.130
(0.100) (0.025 ± 0.005)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.


Solder Reflow Thermal Profile
300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK
PEAK
TEMP.
TEMP.
245°C
240°C
PEAK
TEMP.
230°C
TEMPERATURE (°C)

200
2.5°C ± 0.5°C/SEC.
SOLDERING
30 TIME
160°C
150°C SEC. 200°C
140°C
30
3°C + 1°C/–0.5°C SEC.

100
PREHEATING TIME
150°C, 90 + 30 SEC. 50 SEC.

TIGHT
ROOM TYPICAL
TEMPERATURE LOOSE

0
0 50 100 150 200 250

TIME (SECONDS)

Note: Non-halide flux should be used.

Recommended Pb-Free IR Profile

TIME WITHIN 5 °C of ACTUAL

PEAK TEMPERATURE
tp
20-40 SEC.
260 +0/-5 °C
Tp
217 °C
TL
RAMP-UP
TEMPERATURE

3 °C/SEC. MAX. RAMP-DOWN

150 - 200 °C 6 °C/SEC. MAX.
Tsmax
Tsmin
ts tL
PREHEAT 60 to 150 SEC.
60 to 180 SEC.

25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C

Note: Non-halide flux should be used.

Regulatory Information
The HCPL-24XX has been approved by the following organizations:

VDE IEC/EN/DIN EN 60747-5-2

Approved according to VDE 0884/06.92 (Option 060 Approved under:
only). IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
UL DIN EN 60747-5-2 (VDE 0884
Recognized under UL 1577, Component Recognition Teil 2):2003-01.
Program, File E55361. (Option 060 only)


Insulation and Safety Related Specifications
Parameter Symbol Value Units Conditions
Minimum External L(101) 7.1 mm Measured from input terminals to output
Air Gap (External terminals, shortest distance through air.
Clearance)
Minimum External L(102) 7.4 mm Measured from input terminals to output
Tracking (External terminals, shortest distance path along body.
Creepage)
Minimum Internal 0.08 mm Through insulation distance, conductor to
Plastic Gap conductor, usually the direct distance between the
(Internal Clearance) photoemitter and photodetector inside the
optocoupler cavity.
Tracking Resistance CTI 200 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative
Tracking Index)
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.

IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics

(HCPL-2400 Option 060 ONLY)
Description Symbol Characteristic Units
Installation classification per DIN VDE 0110/1.89, Table 1
  for rated mains voltage ≤300 V rms I-IV
  for rated mains voltage ≤450 V rms I-III
Climatic Classification 55/85/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 630 V peak
Input to Output Test Voltage, Method b*
  VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, VPR 1181 V peak
  Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
  VIORM x 1.5 = VPR, Type and sample test, VPR 945 V peak
  tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec) VIOTM 6000 V peak
Safety Limiting Values
  (Maximum values allowed in the event of a failure,
  also see Figure 12, Thermal Derating curve.)
   Case Temperature TS 175 °C
   Input Current IS,INPUT 230 mA
   Output Power PS,OUTPUT 600 mW
Insulation Resistance at TS, VIO = 500 V RS ≥109 Ω

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2 for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must ben ensured by protective circuits in applica-
tion.


Absolute Maximum Ratings
(No derating required up to 70°C)
Parameter Symbol Minimum Maximum Units Note
Storage Temperature TS -55 125 °C
Operating Temperature TA -40 85 °C
Average Forward Input Current IF(AVG) 10 mA
Peak Forward Input Current IFPK 20 mA 12
Reverse Input Voltage VR 2 V
Three State Enable Voltage VE -0.5 10 V
(HCPL-2400 Only)
Supply Voltage VCC 0 7 V
Average Output Collector Current IO -25 25 mA
Output Collector Voltage VO -0.5 10 V
Output Voltage VO -0.5 18 V
Output Collector Power Dissipation PO 40 mW
(Each Channel)
Total Package Power Dissipation PT 350 mW
(Each Channel)
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane
(for Through Hole Devices)
Reflow Temperature Profile   See Package Outline Drawings section
(Option #300)

Recommended Operating Conditions

Parameter Symbol Minimum Maximum Units
Power Supply Voltage VCC 4.75 5.25 V
Forward Input Current (ON) IF(ON) 4 8 mA
Forward Input Voltage (OFF) VF(OFF) 0.8 V
Fan Out N 5 TTL Loads
Enable Voltage (Low) VEL 0 0.8 V
HCPL-2400 Only)
Enable Voltage (High) VEH 2 VCC V
HCPL-2400 Only)
Operating Temperature TA 0 70 °C


Electrical Specifications
0°C ≤TA ≤70°C, 4.75 V ≤VCC ≤5.25 V, 4 mA ≤IF(ON) ≤8 mA, 0 V ≤VF(OFF) ≤0.8 V. All typicals at TA = 25°C, VCC = 5 V, IF(ON) = 6.0
mA, VF(OFF) = 0 V, except where noted. See Note 11.
Device
Parameter Symbol HCPL- Min. Typ.* Max. Units     Test Conditions Fig. Note
Logic Low Output Voltage VOL 0.5 V IOL = 8.0 mA (5 TTL Loads) 1
Logic High Output VOH 2.4 V IOH = -4.0 mA 2
Voltage 2.7 IOH = -0.4 mA
Output Leakage Current IOHH 100 µA VO = 5.25 V, VF = 0.8 V
Logic High Enable Current VEH 2400 2.0 V
Logic Low Enable Voltage VEL 2400 0.8 V
Logic High Enable IEH 2400 20 µA VE = 2.4 V
Current
100 VE = 5.25 V
Logic Low Enable Current IEL 2400 -0.28 -0.4 mA VE = 0.4 V
Logic Low Supply Current ICCL 2400 19 26 mA VCC = 5.25 V, VE = 0 V,
IO = Open
2430 34 46 VCC = 5.25 V, IO = Open
Logic High Supply ICCH 2400 17 26 mA VCC = 5.25 V, VE = 0 V,
Current IO = Open
2430 32 42 VCC = 5.25 V, IO = Open
High Impedance State ICCZ 2400 22 28 mA VCC = 5.25 V, VE = 5.25 V
Supply Current
High Impedance State IOZL 2400 20 µA VO = 0.4 V VE = 2 V
Output Current IOZH 20 µA VO = 2.4 V
IOZH 100 µA VO = 5.25 V
Logic Low Short Circuit IOSL 52 mA VO = VCC = 5.25 V, 2
Output Current IF = 8 mA
Logic High Short Circuit IOSH -45 mA VCC = 5.25 V, IF = 0 mA, 2
Output Current VO = GND
Input Current Hysteresis IHYS 0.25 mA VCC = 5 V 3
Input Forward Voltage VF 1.1 1.3 1.5 TA = 25°C IF = 8 mA
1.0 1.55 4
Input Reverse Breakdown BVR 3.0 5.0 V TA = 25°C IR = 10 µA
Voltage
2.0
Temperature ∆VF -1.44 mV/°C IF = 6 mA 4
Coefficient of ∆TA
Forward Voltage
Input Capacitance CIN 20 pF f = 1 MHz, VF = 0 V
*All typical values at TA = 25°C and VCC = 5 V, unless otherwise noted.


Switching Specifications
0°C ≤ TA ≤ 70°C, 4.75 V ≤ VCC ≤ 5.25 V, 4 mA ≤ IF(ON) ≤ 8 mA, 0 V ≤ VF(OFF) ≤ 0.8 V. All typicals at TA = 25°C, VCC = 5 V,
IF(ON) = 6.0 mA, VF(OFF) = 0 V, except where noted. See Note 11.

Device
Parameter Symbol HCPL- Min. Typ.* Max. Units   Test Conditions Figure Note

Propagation Delay tPHL 55 ns IF(ON) = 7 mA 5, 6, 7 1, 4,

Time to Logic Low 5, 6
Output Level 15 33 60

Propagation Delay tPLH 55 ns IF(ON) = 7 mA 5, 6, 7 1, 4,

Time to Logic High 5, 6
Output Level 15 30 60

Pulse Width |tPHL-tPLH| 2 15 ns IF(ON) = 7 mA 5, 8 6

Distortion
5 25

Propagation Delay tPSK 35 ns Per Notes & Text 15, 16 7

Skew

Output Rise Time tr 20 ns 5

Output Fall Time tf 10 ns 5

Output Enable Time tPZH 2400 15 ns 9, 10

to Logic High

Output Enable Time tPZL 2400 30 ns 9, 10

to Logic Low

Output Disable Time tPHZ 2400 20 ns 9, 10

from Logic High

Output Disable Time tPLZ 2400 15 ns 9, 10

from Logic Low

Logic High Common |CMH| 1000 10,000 V/µs VCM = 300 V, TA = 25°C, 11 9
Mode Transient IF = 0 mA
Immunity

Logic Low Common |CML| 1000 10,000 V/µs VCM = 300 V, TA = 25°C, 11 9
Mode Transient IF = 4 mA
Immunity

Power Supply Noise PSNI 0.5 Vp-p VCC = 5.0 V, 10

Immunity 48 Hz ≤ = FAC ≤50 MHz

*All typical values at TA = 25°C and VCC = 5 V, unless otherwise noted.


Package Characteristics
Parameter  Sym. Device Min. Typ.* Max.   Units Test Conditions Fig. Note
Input-Output VISO 3750 V rms RH ≤50%, 3, 13
Momentary t = 1 min.,
Withstand Voltage** TA = 25°C
Input-Output RI-O 1012 Ω VI-O = 500 Vdc 3
Resistance
Input-Output CI-O 0.6 pF f = 1 MHz
Capacitance VI-O = 0 Vdc
Input-Input II-I 2430 0.005 µA RH ≤45% 8
Insulation Leakage t = 5 s,
Current VI-I = 500 Vdc
Resistance RI-I 2430 1011 Ω VI-I = 500 Vdc 8
(Input-Input)
Capacitance CI-I 2430 0.25 pF f = 1 MHz 8
(Input-Input)

*All typical values are at TA = 25°C.

**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if applicable), your equipment lev-
el safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number 5963-2203E.

Notes:
1. Each channel.
2. Duration of output short circuit time not to exceed 10 ms.
3. Device considered a two terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
4. tPHL propagation delay is measured from the 50% level on the rising edge of the input current pulse to the 1.5 V level on the falling edge of the
output pulse. The tPLH propagation delay is measured from the 50% level on the falling edge of the input current pulse to the 1.5 V level on the
rising edge of the output pulse.
5. The typical data shown is indicative of what can be expected using the application circuit in Figure 13.
6. This specification simulates the worst case operating conditions of the HCPL-2400 over the recom­mended operating temperature and VCC range
with the suggested application circuit of Figure 13.
7. Propagation delay skew is discussed later in this data sheet.
8. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
9. Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dVCM /dt of the common mode pulse, VCM, to assure
that the output will remain in a Logic High state (i.e., VO > 2.0 V). Common mode transient immunity in a Logic Low level is the maximum toler-
able (negative) dVCM /dt of the common mode pulse, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V).
10. Power Supply Noise Immunity is the peak to peak amplitude of the ac ripple voltage on the VCC line that the device will withstand and still remain
in the desired logic state. For desired logic high state, VOH(MIN) > 2.0 V, and for desired logic low state, VOL(MAX) < 0.8 V.
11. Use of a 0.1 µF bypass capacitor connected between pins 8 and 5 adjacent to the device is required.
12. Peak Forward Input Current pulse width < 50 µs at 1 KHz maximum repetition rate.
13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V rms for one second (leakage detec-
tion current limit, II-O ≤ 5 µA). This test is performed before the 100% Produc­tion test shown in the IEC/EN/DIN EN 60747-5-2 Insulation Related
Characteristics Table, if applicable.

10
Figure 1. Typical logic low output voltage vs. logic low Figure 2. Typical logic high output voltage vs. logic Figure 3. Typical output voltage vs. input forward
output current. high output current. current.

Figure 4. Typical diode input forward current charac- Figure 5. Test circuit for tPLH, tPHL, tr, and tf.
teristic.

Figure 6. Typical propagation delay vs. ambient Figure 7. Typical propagation delay vs. input forward Figure 8. Typical pulse width distortion vs. ambient
temperature. current. temperature.

11
Figure 9. Test circuit for tPHZ, tPZH, tPLZ and tPZL. Figure 10. Typical enable propagation delay vs. ambi-
ent temperature.

HCPL-2400/11 VCC
VCC
1 NC 8
IF 0.1 µF *
B
2 7

3 6 OUTPUT VO
A MONITORING NODE
+
VFF †
– 4 NC 5
OUTPUT POWER – PS, INPUT CURRENT – IS

GND CL = 15 pF 800
VCM PS (mW)
+ – 700 IS (mA)
PULSE GENERATOR
600

500

400

300
HCPL-2400 fig 11a
200

100

0
0 25 50 75 100 125 150 175 200
TS – CASE TEMPERATURE – °C

Figure 11. Test diagram for common mode transient immunity and typical waveforms. Figure 12. Thermal derating curve, dependence of
safety limiting value with case temperature per
IEC/EN/DIN EN 60747-5-2.
HCPL-2400 fig 12

12
Applications

Figure 13. Recommended 20 MBd HCPL-2400/30 interface circuit. Figure 14. Alternative HCPL-2400/30 interface circuit.

DATA

IF 50%
INPUTS

CLOCK

VO 1.5 V

DATA
IF 50%

OUTPUTS t PSK
VO 1.5 V CLOCK

t PSK
t PSK

Figure 15. Illustration of propagation delay skew – tPSK. Figure 16. Parallel data transmission example.

HCPL-2400 fig 15

HCPL-2400 fig 16

Figure 17. Modulation code selections. Figure 18. Typical HCPL-2400/30 output schematic.

13
Propagation Delay, Pulse-Width Distortion and Propa- Propagation delay skew repre­sents the uncertainty of
gation Delay Skew where an edge might be after being sent through an
opto­coupler. Figure 16 shows that there will be uncer-
Propagation delay is a figure of merit which describes tainty in both the data and the clock lines. It is impor-
how quickly a logic signal propagates through a sys- tant that these two areas of uncertainty not overlap,
tem. The propa­ga­tion delay from low to high (tPLH) is the otherwise the clock signal might arrive before all of the
amount of time required for an input signal to propa- data outputs have settled, or some of the data outputs
gate to the output, causing the output to change from may start to change before the clock signal has arrived.
low to high. Similarly, the propagation delay from high From these consid­erations, the absolute minimum pulse
to low (tPHL) is the amount of time required for the input width that can be sent through optocouplers in a par-
signal to propagate to the output, causing the output to allel application is twice tPHZ. A cautious design should
change from high to low (see Figure 5). use a slightly longer pulse width to ensure that any addi-
Pulse-width distortion (PWD) results when tPLH and tPHL tional uncertainty in the rest of the circuit does not cause
differ in value. PWD is defined as the difference between a problem.
tPLH and tPHL and often determines the maximum data The HCPL-2400/30 optocouplers offer the advantages of
rate capabil­ity of a transmission system. PWD can be ex- guaran­teed specifications for propaga­tion delays, pulse-
pressed in percent by dividing the PWD (in ns) by the width distortion, and propagation delay skew over the
minimum pulse width (in ns) being transmitted. Typi- recom­mended temperature, input current, and power
cally, PWD on the order of 20-30% of the minimum pulse supply ranges.
width is tolerable; the exact figure depends on the par-
ticular application (RS232, RS422, T-1, etc.). Application Circuit

Propagation delay skew, tPSK, is an important param- A recommended LED drive circuit is shown in Figure 13.
eter to consider in parallel data appli­ca­tions where This circuit utilizes several techniques to minimize the
synchroniza­tion of signals on parallel data lines is a con- total pulse-width distortion at the output of the opto-
cern. If the parallel data is being sent through a group coupler. By using two inverting TTL gates connected in
of optocouplers, differ­ences in propagation delays will series, the inherent pulse-width distortion of each gate
cause the data to arrive at the outputs of the optocou- cancels the distortion of the other gate. For best results,
plers at different times. If this difference in propagation the two series-connected gates should be from the same
delays is large enough, it will determine the maximum package.
rate at which parallel data can be sent through the op- The circuit in Figure 13 also uses techniques known as
tocouplers. pre­bias and peaking to enhance the performance of the
Propagation delay skew is defined as the difference be- optocoupler LED. Prebias is a small forward voltage ap-
tween the minimum and maxi­mum propaga­tion delays, plied to the LED when the LED is off. This small prebias
either tPLH or tPHL, for any given group of optocouplers voltage partially charges the junction capacitance of the
which are operating under the same conditions (i.e., the LED, allowing the LED to turn on more quickly. The speed
same drive current, supply voltage, output load, and op- of the LED is further increased by applying momentary
erating tem­per­a­ture). As illustrated in Figure 15, if the in- current peaks to the LED during the turn-on and turn-off
puts of a group of optocouplers are switched either ON transitions of the drive current. These peak currents help
or OFF at the same time, tPSK is the difference between to charge and discharge the capacitances of the LED
the shortest propagation delay, either tPLH or tPHL, and the more quickly, shorten­ing the time required for the LED
longest pro-pagation delay, either tPLH or tPHL. to turn on and off.

As mentioned earlier, tPSK can determine the maximum

parallel data transmission rate. Figure 16 is the timing
diagram of a typical parallel data appli­ca­­tion with both
the clock and the data lines being sent through opto-
couplers. The figure shows data and clock signals at the
inputs and outputs of the optocouplers. To obtain the
maximum data transmission rate, both edges of the
clock signals are being used to clock the data; if only one
edge were used, the clock signal would need to be twice
as fast.
Switching performance of the HCPL-2400/30 optocou- the output of the optocoupler, but will not necessarily
plers is not sensitive to the TTL logic family used in the result in lower pulse-width distortion or propagation de-
recommended drive circuit. The typical and worst-case lay skew. This reduction in overall propagation delay is
switching parameters given in the data sheet can be due to shorter delays in the drive circuit, not to changes
met using common 74LS TTL invert­ing gates or buffers. in the propagation delays of the optocoupler; optocou-
Use of faster TTL families will slightly reduce the overall pler prop­agation delays are not affected by the speed of
propagation delays from the input of the drive circuit to the logic used in the drive circuit.

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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0563EN
AV02-0962EN - January 4, 2008