i

Department of Electronics & Communication Engineering

Digital Signal Processing Laboratory Manual

(Integrated Lab)
IV Semester (22EC43)

Staff in-charge:

Dr. Kumar P
Dr. Vinay N A
Prof. Kavitha S G
Prof. Shala Shoal
Lab Instructors: Mrs. Veena and Mrs. Gayathri

HOD: Dr. Shobha K R

Name of the Student :

Semester /Section :
USN :
Batch :

Dayananda Sagar College of Engineering

Shavige Malleshwara Hills, Kumaraswamy Layout,
Banashankari, Bangalore-560111, Karnataka
Tel : +91 80 26662226 26661104 Extn : 2731 Fax : +90 80 2666 0789
Web - http://www.dayanandasagar.edu Email : [email protected]
(An Autonomous Institute Affiliated to VTU, Approved by AICTE & ISO 9001:2008 Certified)
(Accredited by NBA, National Assessment & Accreditation Council (NAAC) with 'A' grade)

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iii
 About the College

The Dayananda Sagar College of Engineering was established in 1979 by Sri R. Dayananda Sagar.
Dayananda Sagar College of Engineering operates under the aegis of the Mahatma Gandhi Vidya
Peetha Trust is approved by All India Council for Technical Education (AICTE), Govt. of India and
affiliated to Visvesvaraya Technological University. It has the widest choice of engineering
branches having 20 Under Graduate courses & 6 Post Graduate courses. In addition, it has 20
Research Centres in different branches of Engineering catering to research scholars for obtaining
Ph.D under VTU. Various courses are accredited by NBA.
The Institute is spread over 23 acres of land with large infrastructure supported by laboratories
with state-of-the-art, Equipment & Machines. The Central Library with modern facilities and the
Digital Library provides the knowledge base for the students.
The campus is WI-FI equipped with large bandwidth internet facility. The College has good faculty
strength with highest professional integrity and committed to the academics with transparency
in their actions. Each faculty takes the responsibility of mentoring a certain number of students’
through personal attention paving the way for the students’ professional growth. The faculty are
research oriented having number of sponsored R & D projects from different agencies such as
Department of Science & Technology, Defense R & D organizations, Indian Space Research
Organization, AICTE etc..

About the Department

Department of Electronics and Communication Engineering is one of the oldest and biggest
department in the DSI group with 50 faculty members and 1200+ students. Most of our faculty
have pursued Ph.D. and others are in the process. The ECE department provides high-quality,
innovative technical education at the undergraduate, graduate, and research levels. At present,
the department offers an UG course (BE) with an intake of 240, a PG course in VLSI Design and
Embedded Systems with an intake of 18 students and Ph.D. The department has got an excellent
infrastructure with sophisticated labs, class rooms and R & D center. The department faculty and
support personnel are dedicated towards helping students achieve success in today's world by
offering them the knowledge and skills required. The department places a strong emphasis on
leading-edge research through its research centre and research forum. These factors together
enable our graduating students to create a big impact on the workforce from day one.
In addition to offering innovative courses, the department is more focused on improving
students' educational experiences by offering value-added courses, skill-development programs,
technical challenges and hackathons at state, national, and international arenas. Through its
professional societies and technical clubs, the department takes great satisfaction in exposing its
students to current industry developments and upcoming technologies. The dedicated staff at
the ECE department help students procure jobs in prestigious companies both domestically and
abroad.

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Vision of the College:
To impart quality technical education with a focus on Research and Innovation emphasizing on
Development of Sustainable and Inclusive Technology for the benefit of society.

Mission of the College:

❖ To provide an environment that enhances creativity and Innovation in pursuit of
Excellence.
❖ To nurture teamwork in order to transform individuals as responsible leaders and
entrepreneurs.
❖ To train the students to the changing technical scenario and make them to understand
the importance of Sustainable and Inclusive technologies.

Vision of the Department

To achieve continuous improvement in quality technical education for global competence with
focuson industry, societal needs, research and professional success.

Mission of the Department

❖ Offering quality education in Electronics and Communication Engineering with effective
teaching learning process in multidisciplinary environment.
❖ Training the students to take-up projects in emerging technologies and work with team
spirit.
❖ To imbibe professional ethics, development of skills and research culture for better
placement opportunities.

Program Educational Objectives [PEOs]

The Graduate students must be able to:
❖ PEO-1: Ready to apply the state-of-art technology in industry and meeting the societal needs
with Knowledge of Electronics and Communication Engineering due to strong academic
culture.
❖ PEO-2: Competent in technical and soft skills to be employed with capability of working in
Multidisciplinary domains.
❖ PEO-3: Professionals, capable of pursuing higher studies in technical, research or
management programs.

Programme Specific Outcomes [PSOs]

❖ PSO-1: Design, develop and integrate electronic circuits and systems using current practices
and Standards.
❖ PSO-2: Apply knowledge of hardware and software in designing Embedded and
Communication Systems.

Programme Outcomes [POs]

Engineering Graduates will be able to:

1. Engineering Knowledge: Apply the Knowledge of Mathematics, Science, Engineering

Fundamentals, and an Engineering specialization to the solution of complex Engineering
problems.

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2. Problem Analysis: Identify, Formulate, Review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of Mathematics,
natural sciences and engineering sciences.
3. Design/Development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
conditions.
4. Conduct investigations on complex problems: Use research based knowledge and research
methods including design of Experiments, analysis and interpretation of data, and synthesis of
Information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate technique, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with
an understanding of the limitations.
6. The Engineer and Society: Apply reasoning informed by the contextual knowledge to assess
society, health, safety, legal and cultural issues and the consequent responsibilities relevant to
the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions
in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s work, as a member and leader
in a team, to manage projects and in multidisciplinary environments.
12. Lifelong learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

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 DEPARTMENT of ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL SIGNAL PROCESSING(INTEGRATED) LABORATORY
Index Sheet

Sl.No Program Page.n

o.
Part A- MATLAB Simulation Program
1 Computation of Circular Convolution Using DFT and FFT 1-3
2 Verification of Parseval’s theorem 4-6
3 Verification of Time Shifting Property of DFT 7-8
4 Verification of Auto-correlation and Cross-correlation 9-10
5 Computation of Fast Fourier Transform 12-15
6 Design of IIR Filter using Butterworth technique 16-18
7 Design of FIR Filter using Hamming window 19-20
8 IEEE 32-bit floating point conversions 20-21
Part B- Hardware Integration using Code Composer Studio
Introduction to TMS320C6713 DSK 21-24
Introduction to Code Composer Studio 25-29
1 C-Program to compute Linear Convolution 30-31
2 C-Program to compute Circular Convolution 32-34
3 C-Program to compute N-point DFT 35-37
4 C-Program to find impulse response 38-39
Open ended Experiments
1 Compare frequency response of FIR Filter using various window function
in MTALAB-SIMULINK
2 Impulse response of an LTI system

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 DEPARTMENT of ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL SIGNAL PROCESSING(INTEGRATED) LABORATORY

Lab Assessment sheet

Signature Signature for

Conduction Record Viva Assignment
Experiment No. Title of the experiment for lab Assignment
(10) (05) (05) (10)
assessment assessment
1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

Signature of the HoD

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 Digital Signal Processing Lab

Experiment 1
Computation of Circular Convolution Using DFT and FFT
Aim: To study the computation of Circular Convolution with real time sequences.
Objective:
a. To study how Circular convolution using DFT and IDFT provides an efficient computational
approach compared to direct time-domain convolution, especially for long sequences.
b. To analyse how Circular convolution is suitable for handling periodic or circularly
extended signals.
Theory:
• Circular convolution is cyclic convolution of two sequences of same length.
• If the length of the sequences are unequal then required no.of zeros are padded.
• There are three ways to compute circular convolution:
(i). Using DFT and IDFT: Let x(n) and h(n) are the sequences, then
N−1

DFT{x(n)} = X(K) = ∑ x(n). ωN Kn

K=0
N−1

DFT{h(n)} = H(K) = ∑ h(n). ωN Kn

K=0

Y(K) = X(K) ∙ H(K)

N−1
1
IDFT{y(n)} = ∑ h(n). ωN −Kn
N
n=0

(ii). Direct method suing formula

N−1

y(n) = ∑ x(n) ∙ h(n − m)N

m=0

(iii). Graphical Method

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 Digital Signal Processing Lab

MATLAB code
clc;
clear all;
close all;

% Define two input sequences

x = [1, 2, 3, 4]; % First sequence
y = [2, 1, 2, 1]; % Second sequence

% Compute the length of the circular convolution

N = max(length(x), length(y));

% Zero-pad the sequences if necessary

x = [x, zeros(1, N - length(x))];
y = [y, zeros(1, N - length(y))];

% Compute DFT manually

X = zeros(1, N);
Y = zeros(1, N);
for k = 0:N-1
for n = 0:N-1
X(k+1) = X(k+1) + x(n+1) * exp(-1j * 2 * pi * k * n / N);
Y(k+1) = Y(k+1) + y(n+1) * exp(-1j * 2 * pi * k * n / N);
end
end

% Perform element-wise multiplication in the frequency domain

Z = X .* Y;

% Compute inverse DFT manually

z = zeros(1, N);
for n = 0:N-1
for k = 0:N-1
z(n+1) = z(n+1) + Z(k+1) * exp(1j * 2 * pi * k * n / N);
end
z(n+1) = z(n+1) / N;
end

% Display results
disp('Circular Convolution using DFT (without FFT):');
disp(z);

% Plot input sequences

figure;
subplot(4,1,1);
stem(x, 'filled');
title('Input Sequence x');
xlabel('Index');
ylabel('Amplitude');
grid on;

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subplot(4,1,2);
stem(y, 'filled');
title('Input Sequence y');
xlabel('Index');
ylabel('Amplitude');
grid on;

% Plot real and imaginary parts separately

subplot(4,1,3);
stem(real(z), 'filled');
title('Real Part of Circular Convolution');
xlabel('Index');
ylabel('Amplitude');
grid on;

subplot(4,1,4);
stem(imag(z), 'filled');
title('Imaginary Part of Circular Convolution');
xlabel('Index');
ylabel('Amplitude');
grid on;

Results:

Circular Convolution using DFT (without FFT):

14.0000 - 0.0000i 16.0000 + 0.0000i 14.0000 - 0.0000i 16.0000 - 0.0000i

Assignment
1. Write the MATLAB code to compute circular convolution of two sequence using fft
function.
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 Digital Signal Processing Lab

Experiment 2
Verification of Parseval’s theorem
Aim: Write MATLAB code to verify the Parseval’s theorem
Objectives:
• To establish energy conservation between the time domain and frequency domain
representations of a signal.
• To provide an equivalence between the power of a signal in the time domain and its power
spectral density in the frequency domain.
• To study how Parseval’s theorem used in signal reconstruction tasks, especially in
applications such as signal processing, data compression, and digital communications.
Theory:
Parseval's Theorem is a concept in Fourier analysis and signal processing, stating that the total
energy in a signal is equal to the sum of the square of its Fourier transform's magnitude.
∞ ∞
1
∑ x(n)x ∗ (n) = ∑ X(k)X ∗ (k)
N
n=−∞ n=−∞
∞
∗ (𝐭)
𝟏 ∞
∫ 𝐱(𝐭)𝐱 = ∫ 𝐗(𝛚)𝐗 ∗ (𝛚)
−∞ 𝟐𝛑 −∞
MATLAB Code:
clc;
clear all;
close all;

% Define input sequence

x = [1, 2, 3, 4]; % Example sequence
N = length(x);

% Compute DFT manually

X = zeros(1, N);
for k = 0:N-1
for n = 0:N-1
X(k+1) = X(k+1) + x(n+1) * exp(-1j * 2 * pi * k * n / N);
end
end

% Compute the time domain energy

energy_time = sum(abs(x).^2);

% Compute the frequency domain energy

energy_freq = sum(abs(X).^2) / N;

% Display results
disp('Verification of Parseval’s Theorem:');
disp(['Energy in Time Domain: ', num2str(energy_time)]);
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disp(['Energy in Frequency Domain: ', num2str(energy_freq)]);

% Plot input sequence

figure;
subplot(2,1,1);
stem(x, 'filled');
title('Input Sequence');
xlabel('Index');
ylabel('Amplitude');
grid on;

% Plot magnitude spectrum

subplot(2,1,2);
stem(abs(X), 'filled');
title('Magnitude Spectrum');
xlabel('Index');
ylabel('Magnitude');
grid on;

Results:
Verification of Parseval’s Theorem:
Energy in Time Domain: 30
Energy in Frequency Domain: 30

Assignment:

1. Write the MATLAB code to verify the Parseval’s theorem for a continuous time signal

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 Digital Signal Processing Lab

Experiment 3
Verification of Time Shifting Property of DFT
Aim: Write MATLAB code to verify the Time Shifting Property of DFT
Objectives:
• To validate the correctness of the time-shifting property of the DFT.
• To analyze the effects of time shifts on signals in the frequency domain and understanding
these effects is crucial for designing robust signal processing systems capable of handling
time-varying signals accurately and efficiently.
• By incorporating the time-shifting property into system design and analysis, engineers can
optimize signal processing algorithms and architectures to meet specific performance
requirements and constraints.
Theory:
The time-shifting property of discrete-time Fourier transform states that:
If DFT{x(n)} ↔ X(K), then

DFT{x(n − n0 )} ↔ e−j2πkn0 X(K)

MATLAB Code:
clc;
clear all;
close all;

% Define input sequence

x = [1, 2, 3, 4]; % Example sequence
N = length(x);
k_shift = 2; % Shift amount

% Compute DFT manually

X = zeros(1, N);
for k = 0:N-1
for n = 0:N-1
X(k+1) = X(k+1) + x(n+1) * exp(-1j * 2 * pi * k * n / N);
end
end

% Time shift the sequence

x_shifted = circshift(x, k_shift);

% Compute DFT of shifted sequence

X_shifted = zeros(1, N);
for k = 0:N-1
for n = 0:N-1
X_shifted(k+1) = X_shifted(k+1) + x_shifted(n+1) * exp(-1j * 2 * pi * k * n / N);
end
end

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 Digital Signal Processing Lab

% Compute phase shift in frequency domain

X_expected = X .* exp(-1j * 2 * pi * k_shift * (0:N-1) / N);

% Display results
disp('Verification of Time Shifting Property of DFT:');
disp('DFT of time-shifted sequence:');
disp(X_shifted);
disp('Expected DFT after applying phase shift:');
disp(X_expected);

% Plot input sequence

figure;
subplot(3,1,1);
stem(x, 'filled');
title('Original Input Sequence');
xlabel('Index');
ylabel('Amplitude');
grid on;

subplot(3,1,2);
stem(x_shifted, 'filled');
title('Time-Shifted Sequence');
xlabel('Index');
ylabel('Amplitude');
grid on;

% Plot magnitude spectrum

subplot(3,1,3);
stem(abs(X_shifted), 'filled');
title('Magnitude Spectrum of Time-Shifted Sequence');
xlabel('Index');
ylabel('Magnitude');
grid on;

Results

Verification of Time Shifting Property of DFT:

DFT of time-shifted sequence:

10.0000 + 0.0000i 2.0000 - 2.0000i -2.0000 - 0.0000i 2.0000 + 2.0000i

Expected DFT after applying phase shift:

10.0000 + 0.0000i 2.0000 - 2.0000i -2.0000 - 0.0000i 2.0000 + 2.0000i

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 Digital Signal Processing Lab

Assignment:
1. Write the MATLAB code to verify the time-shifting property of DFT by choosing n0 =
1 𝑎𝑛𝑑 3

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 Digital Signal Processing Lab

Experiment 4
Verification of Auto-correlation and Cross-correlation
Aim: Write the MATLAB code to verify the Auto-correlation and Cross-correlation of the given
signal/sequence.
Objectives:
• Autocorrelation is to analyse the similarity and periodicity within a signal and Cross
correlation is to analyse the alignment of signals in time or phase.
• Autocorrelation is used to estimate time delays between different parts of a signal. The
cross-correlation estimates the time delay between two signals.
• Autocorrelation is used in system identification to estimate the impulse response of a linear
time-invariant (LTI) system. In communication systems, cross-correlation is used for
channel estimation.
Theory:

The autocorrelation function is defined as the measure of similarity or coherence between a signal
and its time delayed version. Therefore, the autocorrelation is the correlation of a signal with itself.
∞
Autocorrelation{x(t)} = Y(τ) = ∫ x(t)x ∗ (t − τ)dτ
−∞

The cross-correlation between two different signals or functions or waveforms is defined as the
measure of similarity or coherence between one signal and the time-delayed version of another
signal. The cross-correlation between two different signals indicates the degree of relatedness
between one signal and the time-delayed version of another signal.
∞
Cross − correlation{x(t) ∗ h(t)} = Y(τ) = ∫ x(t)h∗ (t − τ)dτ
−∞

clc;
clear all;
close all;

% Define input sequences

x = [1, 2, 3, 4]; % Example sequence
y = [4, 3, 2, 1]; % Another sequence for cross-correlation
N = length(x);

% Compute Auto-correlation using DFT

X = fft(x, N);
Rxx = ifft(abs(X).^2, N);

% Compute Cross-correlation using DFT

Y = fft(y, N);
Rxy = ifft(X .* conj(Y), N);

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 Digital Signal Processing Lab

% Display results
disp('Verification of Auto-correlation and Cross-correlation:');
disp('Auto-correlation sequence:');
disp(Rxx);
disp('Cross-correlation sequence:');
disp(Rxy);

% Plot input sequences

figure;
subplot(3,1,1);
stem(x, 'filled');
title('Input Sequence x');
xlabel('Index');
ylabel('Amplitude');
grid on;

subplot(3,1,2);
stem(y, 'filled');
title('Input Sequence y');
xlabel('Index');
ylabel('Amplitude');
grid on;

% Plot correlation results

subplot(3,1,3);
stem(Rxx, 'filled');
title('Auto-correlation of x');
xlabel('Index');
ylabel('Amplitude');
grid on;

figure;
stem(Rxy, 'filled');
title('Cross-correlation of x and y');
xlabel('Index');
ylabel('Amplitude');
grid on;

Results:

Verification of Auto-correlation and Cross-correlation:

Auto-correlation sequence:

30 24 22 24

Cross-correlation sequence:

20 26 28 26

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Assignment:
1. Write the MATLAB code to compute the cross-correlation of two sequences.

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Experiment 5
Computation of Fast Fourier Transform
Aim: Write the MATLAB code to compute Fast Fourier Transform of the sequence and plot it
magnitude and phase response.
Objectives:
• To study how FFT is more efficient with respect to less computation time compare to DFT
technique.
• To analyse the magnitude and phase spectrum of the signal.
Theory:
The Fast Fourier Transform (FFT) stands as a seminal advancement in computational
mathematics, particularly within the domain of signal processing. Fundamentally, the FFT is an
algorithmic marvel devised to efficiently compute the Discrete Fourier Transform (DFT) of a
discrete sequence or signal.
N−1

FFT{x(n)} = X(K) = ∑ x(n). ωN Kn

K=0

The most commonly used version of the FFT is the Radix-2 FFT, where the size of the input
sequence N is a power of 2. In Radix-2 FFT, the sequence is recursively divided into two halves,
and the DFT of each half is computed independently. The computed DFTs are then combined using
twiddle factors (complex exponentials) to produce the final DFT of the entire sequence.
The FFT algorithm can be implemented using either decimation-in-time (DIT) or decimation-in-
frequency (DIF) approaches. In DIT FFT, the sequence is recursively divided into smaller
subproblems in the time domain. In DIF FFT, the sequence is recursively divided in the frequency
domain. Both approaches are mathematically equivalent but may have different computational
characteristics.
MATLAB Code to compute FFT using formula or direct method
clc;
clear all;
close all;

% Define input sequence

x = [1, 2, 3, 4]; % Example sequence
N = length(x);

% Compute FFT using direct method (DFT formula)

X = zeros(1, N);
for k = 0:N-1
for n = 0:N-1
X(k+1) = X(k+1) + x(n+1) * exp(-1j * 2 * pi * k * n / N);
end
end

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% Compute IFFT using direct method

x_reconstructed = zeros(1, N);
for n = 0:N-1
for k = 0:N-1
x_reconstructed(n+1) = x_reconstructed(n+1) + X(k+1) * exp(1j * 2 * pi * k * n / N);
end
x_reconstructed(n+1) = x_reconstructed(n+1) / N;
end

% Display results
disp('Computation of Fast Fourier Transform using Direct Method:');
disp('FFT of input sequence:');
disp(X);
disp('Reconstructed sequence using IFFT:');
disp(x_reconstructed);

% Plot input sequence

figure;
subplot(3,1,1);
stem(x, 'filled');
title('Input Sequence');
xlabel('Index');
ylabel('Amplitude');
grid on;

% Plot magnitude spectrum

subplot(3,1,2);
stem(abs(X), 'filled');
title('Magnitude Spectrum');
xlabel('Index');
ylabel('Magnitude');
grid on;

% Plot reconstructed sequence

subplot(3,1,3);
stem(real(x_reconstructed), 'filled');
title('Reconstructed Sequence using IFFT');
xlabel('Index');
ylabel('Amplitude');
grid on;

Results:

Computation of Fast Fourier Transform using Direct Method:

FFT of input sequence:

10.0000 + 0.0000i -2.0000 + 2.0000i -2.0000 - 0.0000i -2.0000 - 2.0000i

Reconstructed sequence using IFFT:

1.0000 - 0.0000i 2.0000 - 0.0000i 3.0000 - 0.0000i 4.0000 + 0.0000i

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DIT-FFT

clc;
clear all;
close all;

% Define input sequence

x = [1, 2, 3, 4]; % Example sequence
N = length(x);

% Bit-reversal permutation
num_stages = log2(N)
x_reordered = bitrevorder(x)

% Initialize FFT output

X = complex(x_reordered);

% Perform DIT-FFT with even-odd splitting

for stage = 1:num_stages
step = 2^stage;
half_step = step / 2;
W_N = exp(-1j * 2 * pi / step);
for k = 1:step:N
even_part = X(k:k+half_step-1);
odd_part = X(k+half_step:k+step-1);
for n = 0:half_step-1
twiddle = W_N^n * odd_part(n+1);
X(k+n) = even_part(n+1) + twiddle;
X(k+n+half_step) = even_part(n+1) - twiddle;
end

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end
end

% Compute IFFT using DIT method

X_conj = conj(X);
X_ifft = X_conj;
for stage = 1:num_stages
step = 2^stage;
half_step = step / 2;
W_N = exp(1j * 2 * pi / step);
for k = 1:step:N
even_part = X_ifft(k:k+half_step-1);
odd_part = X_ifft(k+half_step:k+step-1);
for n = 0:half_step-1
twiddle = W_N^n * odd_part(n+1);
X_ifft(k+n) = even_part(n+1) + twiddle;
X_ifft(k+n+half_step) = even_part(n+1) - twiddle;
end
end
end
x_reconstructed = conj(X_ifft) / N;

% Display results
disp('Computation of FFT using DIT-FFT with Even-Odd Splitting:');
disp('FFT of input sequence:');
disp(X);
disp('Reconstructed sequence using IFFT:');
disp(x_reconstructed);

% Plot input sequence

figure;
subplot(3,1,1);
stem(x, 'filled');
title('Input Sequence');
xlabel('Index');
ylabel('Amplitude');
grid on;

% Plot magnitude spectrum

subplot(3,1,2);
stem(abs(X), 'filled');
title('Magnitude Spectrum using DIT-FFT');
xlabel('Index');
ylabel('Magnitude');
grid on;

% Plot reconstructed sequence

subplot(3,1,3);
stem(real(x_reconstructed), 'filled');
title('Reconstructed Sequence using IFFT');
xlabel('Index');
ylabel('Amplitude');
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grid on;

Results:

num_stages = 2

x_reordered = [1 3 2 4]

Computation of FFT using DIT-FFT with Even-Odd Splitting:

FFT of input sequence:

10.0000 + 0.0000i -2.0000 + 2.0000i -2.0000 + 0.0000i -2.0000 - 2.0000i

DIF-FFT

clc;
clear all;
close all;

% Define input sequence

x = [1, 2, 3, 4]; % Example sequence
N = length(x);

% Perform DIF-FFT
X = complex(x)
num_stages = log2(N)

for stage = num_stages:-1:1

step = 2^stage;
half_step = step / 2;
W_N = exp(-1j * 2 * pi / step);
for k = 1:step:N

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for n = 0:half_step-1
pos = k + n;
temp = X(pos);
twiddle = W_N^n * X(pos + half_step);
X(pos) = temp + twiddle;
X(pos + half_step) = temp - twiddle;
end
end
end

% Bit-reversal permutation
X = bitrevorder(X);

% Compute IFFT using DIF method

X_ifft = X;
for stage = 1:num_stages
step = 2^stage;
half_step = step / 2;
W_N = exp(1j * 2 * pi / step);
for k = 1:step:N
for n = 0:half_step-1
pos = k + n;
temp = X_ifft(pos);
twiddle = W_N^n * X_ifft(pos + half_step);
X_ifft(pos) = temp + twiddle;
X_ifft(pos + half_step) = temp - twiddle;
end
end
end
x_reconstructed = X_ifft / N;

% Display results
disp('Computation of FFT using DIF-FFT:');
disp('FFT of input sequence:');
disp(X);
disp('Reconstructed sequence using IFFT:');
disp(x_reconstructed);

% Plot input sequence

figure;
subplot(3,1,1);
stem(x, 'filled');
title('Input Sequence');
xlabel('Index');
ylabel('Amplitude');
grid on;

% Plot magnitude spectrum

subplot(3,1,2);
stem(abs(X), 'filled');
title('Magnitude Spectrum using DIF-FFT');
xlabel('Index');
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ylabel('Magnitude');
grid on;

% Plot reconstructed sequence

subplot(3,1,3);
stem(real(x_reconstructed), 'filled');
title('Reconstructed Sequence using IFFT');
xlabel('Index');
ylabel('Amplitude');
grid on;

Results:

X = 1.0000 + 0.0000i 2.0000 + 0.0000i 3.0000 + 0.0000i 4.0000 + 0.0000i

num_stages = 2

Computation of FFT using DIF-FFT:

FFT of input sequence:

6.0000 - 4.0000i -0.0000 + 4.0000i 2.0000 + 4.0000i -4.0000 - 4.0000i

Assignment:

1. Write the MATLAB code to compute FFT of the sequence using inbuilt FFT function.

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Experiment 6
Design of IIR Filter
Aim: To design the IIR Butterworth approximation technique and to analyse the response of the
same
Objectives:
• The primary objectives of designing a Butterworth filter is to achieve a maximally flat
frequency response in the passband.
• Butterworth filters are designed to be stable and causal, ensuring that the output of the
filter does not grow indefinitely and is dependent only on past and present inputs.
• Another objective is to achieve a smooth roll-off in the stopband, where the attenuation of
frequencies outside the passband gradually increases.
• The design aims to minimize the width of the transition band, which is the frequency range
between the passband and stopband.
Theory:

The Butterworth filter is an analogue filter design which produces the best output response with
no ripple in the pass band or the stop band resulting in a maximally flat filter response but at the
expense of a relatively wide transition band.

MATLAB Code for IIR Butterworth Lowpass filter

clc;
clear all;
close all;

% Define filter specifications

passband_frequency = 500; % Passband frequency in Hz
stopband_frequency = 750; % Stopband frequency in Hz
passband_ripple = 3; % Passband ripple in dB
stopband_attenuation = 15; % Stopband attenuation in dB
fs = 2000; % Sampling frequency in Hz

omp=2*passband_frequency/fs;
oms=2*stopband_frequency/fs;
%to find cut off frequency & order of the filter
[N,Wn]=buttord(omp,oms,passband_ripple,stopband_attenuation)
disp('order of the filter n =');
disp(N);
disp('cut off frequency Wn= ');
disp(Wn);

%system function of the filter

[b,a]=butter(N,Wn,'low')
w=0:0.01:pi;
[h,om]=freqz(b,a,w,'whole');
m=abs(h);
an=angle(h);

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subplot(2,1,1);
plot(om/pi,20*log(m));
grid;
ylabel('gain in dB');
xlabel('normalized frequency');
subplot(2,1,2);
plot(om/pi,an);
grid;
ylabel('phase in radian');
xlabel('normalized frequency');
% to convert analog filter to digital filter
% using bilinear transformation
[bz,az]=bilinear(b,a,fs)

H_digital = tf(b,a, 1/fs)

disp('Transfer function (H(z)):');
disp(H_digital)

Output:

N=

Wn =

0.5083

order of the filter n =

2

cut off frequency Wn=

0.5083

b=

0.3005 0.6011 0.3005

a=

1.0000 0.0304 0.1717

bz =

0.3007 -0.6011 0.3004

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az =

1.0000 -2.0000 1.0000

H_digital =

0.3005 z^2 + 0.6011 z + 0.3005

------------------------------
z^2 + 0.03039 z + 0.1717

Assignment:
1. Write the MATLAB code to design IIR Butterworth high pass filter.

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Experiment 7
Design of FIR Filter using Hamming window
Aim: Write the MATLAB code to design the high pass FIR filter using Hamming and to analyse its
plot frequency response.
Objectives:
• The primary objective is to design the FIR filter to meet specific frequency response
requirements.
• The objective is to select a window function that minimizes mainlobe width while
simultaneously suppressing sidelobes to an acceptable level.
• The FIR filter design should be robust to variations in filter parameters, such as changes in
cutoff frequencies, passband ripple, or stopband attenuation.
• To achieve linear phase while meeting the frequency response specifications, ensuring
minimal phase distortion in the filtered output.
MATLAB Code using hamming window
clc;
wp=0.3*pi;
ws=0.45*pi;
ap=-3;
as=-50;
wt=ws-wp;
n1=ceil((8*pi)/wt);
wc=wp/pi;
N=n1+rem(n1-1,2);
disp(N);
wn=hamming(N);
disp(wn);
a=(N-1)/2;
h=fir1(N-1,wc,wn); % fir1 function will calculate both hd(n) and h(n)
disp(h);
figure;
freqz(h);
figure;
n=0:N-1;
stem(n,h);
xlabel('time axis');
ylabel('h(n)');
title('impulse response of FIR lowpass filter');
disp(wn)

Output

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Results and Inference: N =55

w(n) =>
0.0800, 0.0831, 0.0924, 0.1077, 0.1289, 0.1557, 0.1876, 0.2243, 0.2653,
0.3100, 0.3578,
0.4081, 0.4601, 0.5133, 0.5667, 0.6199, 0.6719, 0.7222, 0.7700, 0.8147,
0.8557, 0.8924,
0.9243, 0.9511, 0.9723, 0.9876, 0.9969, 1.0000, 0.9969, 0.9876, 0.9723,
0.9511, 0.9243,
0.8924, 0.8557, 0.8147, 0.7700, 0.7222, 0.6719, 0.6199, 0.5667, 0.5133,
0.4601, 0.4081,
0.3578, 0.3100, 0.2653, 0.2243, 0.1876, 0.1557, 0.1289, 0.1077, 0.0924,
0.0831, 0.0800

The Order of the filter have been designed and verified. Window function
coefficients are calculated and verified. Also, Filter response is obtained and
verified forsymmetry.

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Experiment 8
IEEE 32-bit floating point conversions

Given:
x=0.560123

1. Multiply by 215=327682

0.560123×32768=18364.94

2. Round to the nearest integer:

18365

3. Convert to binary (16-bit representation):

18365=01000111100011012

clc;
clear all;
close all;

% Given decimal number

x = -0.160123; % Change this number to test different values

% Q15 Scaling Factor

Q15_factor = 2^15;

% Signed Q15 Representation

Q15_signed = round(x * Q15_factor);

% Unsigned Q15 Representation (Assuming the range is [0,1] mapped to [0, 2^16-1])
Q15_unsigned = round((x + 1) * (2^15)); % Shift by +1 for unsigned range

% Convert to Binary (16-bit)

Q15_signed_binary = dec2bin(mod(Q15_signed, 2^16), 16); % Modulus to handle negatives correctly
Q15_unsigned_binary = dec2bin(Q15_unsigned, 16);

% Display results
disp(['Decimal: ', num2str(x)]);
disp(['Signed Q15 Representation (Decimal): ', num2str(Q15_signed)]);
disp(['Signed Q15 Representation (Binary): ', Q15_signed_binary]);
disp(['Unsigned Q15 Representation (Decimal): ', num2str(Q15_unsigned)]);
disp(['Unsigned Q15 Representation (Binary): ', Q15_unsigned_binary]);
Results:
Decimal: -0.16012
Signed Q15 Representation (Decimal): -5247
Signed Q15 Representation (Binary): 1110101110000001
Unsigned Q15 Representation (Decimal): 27521
Unsigned Q15 Representation (Binary): 0110101110000001

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Part B
Introduction to TMS320C6713 DSK
The C6713 DSK has a TMS320C6713 DSP onboard that allows full-speed
verification of codewith Code Composer Studio. The C6713 DSK provides:
• A USB Interface
• SDRAM and ROM
• An analog interface circuit for Data conversion (AIC)
• An I/O port
• Embedded JTAG emulation support

Connectors on the C6713 DSK provide DSP external memory interface (EMIF)
and peripheral signals that enable its functionality to be expanded with
custom or third party daughter boards.

The DSK provides a C6713 hardware reference design that can assist you in
the developmentof your own C6713-based products. In addition to providing
a reference for interfacing the DSP to various types of memories and
peripherals, the design also addresses power, clock, JTAG, and parallel
peripheral interfaces.
The C6713 DSK includes a stereo codec. This Analog Interface Circuit (AIC) has
the followingcharacteristics:

High-Performance Stereo Codec

• 90-dB SNR Multibit Sigma-Delta ADC (A-weighted at 48 kHz)
• 100-dB SNR Multibit Sigma-Delta DAC (A-weighted at 48 kHz)
• 1.42 V – 3.6 V Core Digital Supply: Compatible With TI
C54x DSP CoreVoltages
• 2.7 V – 3.6 V Buffer and Analog Supply: Compatible Both
TI C54x DSPBuffer Voltages
• 8-kHz – 96-kHz Sampling-Frequency Support

Software Control Via TI McBSP-Compatible Multiprotocol Serial Port

• I 2 C-Compatible and SPI-Compatible Serial-Port Protocols
• Glueless Interface to TI McBSPs
Audio-Data Input/output Via TI McBSP-Compatible Programmable Audio Interface
• I 2 S-Compatible Interface Requiring Only One McBSP for
both ADC andDAC
• Standard I 2 S, MSB, or LSB Justified-Data Transfers
• 16/20/24/32-Bit Word Lengths
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The C6713DSK has the following features:

The 6713 DSK is a low-cost standalone development platform that enables customers to
evaluate and develop applications for the TI C67XX DSP family. The DSK also serves as a
hardware reference design for the TMS320C6713 DSP. Schematics, logic equations and
application notes are available to ease hardware development and reduce time to market.
The DSK uses the 32-bit EMIF for the SDRAM (CE0) and daughter card expansion
interface (CE2 and CE3). The Flash is attached to CE1 of the EMIF in 8-bit mode.
An on-board AIC23 codec allows the DSP to transmit and receive analog signals. McBSP0
isused for the codec control interface and McBSP1 is used for data. Analog audio I/O is
done through four 3.5mm audio jacks that correspond to microphone input, line input,
line output and headphone output. The codec can select the microphone or the line input
as the active input. The analog output is driven to both the line out (fixed gain) and
headphone (adjustable gain) connectors. McBSP1 can be re-routed to the expansion
connectors in software.
A programmable logic device called a CPLD is used to implement glue logic that ties the
boardcomponents together. The CPLD has a register based user interface that lets the user
configurethe board by reading and writing to the CPLD registers. The registers reside at
the midpoint of CE1.

The DSK includes 4 LEDs and 4 DIP switches as a simple way to provide the user with
interactive feedback. Both are accessed by reading and writing to the CPLD registers.
An included 5V external power supply is used to power the board. On-board voltage
regulatorsprovide the 1.26V DSP core voltage, 3.3V digital and 3.3V analog voltages. A
voltage supervisor monitors the internally generated voltage, and will hold the board in
reset until the supplies are within operating specifications and the reset button is
released. If desired, JP1 andJP2 can be used as power test points for the core and I/O
power supplies.
Code Composer communicates with the DSK through an embedded JTAG emulator with
a USB host interface. The DSK can also be used with an external emulator through the
externalJTAG connector.

TMS320C6713 DSP Features

Highest-Performance Floating-Point Digital Signal Processor (DSP):

➢ Eight 32-Bit Instructions/Cycle
➢ 32/64-Bit Data Word
➢ 300-, 225-, 200-MHz (GDP), and 225-, 200-, 167-MHz (PYP) Clock Rates
➢ 3.3-, 4.4-, 5-, 6-Instruction Cycle Times
➢ 2400/1800, 1800/1350, 1600/1200, and 1336/1000 MIPS /MFLOPS
➢ Rich Peripheral Set, Optimized for Audio
➢ Highly Optimized C/C++ Compiler
➢ Extended Temperature Devices Available
➢ Advanced Very Long Instruction Word (VLIW) TMS320C67x™ DSP Core

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➢ Eight Independent Functional Units:

▪ Two ALUs (Fixed-Point)
▪ Four ALUs (Floating- and Fixed-Point)
▪ Two Multipliers (Floating- and Fixed-Point)
➢ Load-Store Architecture With 32 32-Bit General-Purpose Registers
➢ Instruction Packing Reduces Code Size
➢ All Instructions Conditional
Instruction Set Features
➢ Native Instructions for IEEE 754
▪ Single- and Double-Precision
➢ Byte-Addressable (8-, 16-, 32-Bit Data)
➢ 8-Bit Overflow Protection
➢ Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization
L1/L2 Memory Architecture
➢ 4K-Byte L1P Program Cache (Direct-Mapped)
➢ 4K-Byte L1D Data Cache (2-Way)
➢ 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and
192K-Byte Additional L2 Mapped RAM
Device Configuration
➢ Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
➢ Endianness: Little Endian, Big Endian
32-Bit External Memory Interface (EMIF)
➢ Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM
➢ 512M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
16-Bit Host-Port Interface (HPI)
Two Multichannel Audio Serial Ports (McASPs)
➢ Two Independent Clock Zones Each (1 TX and 1 RX)
➢ Eight Serial Data Pins Per Port:
Individually Assignable to any of the Clock Zones
➢ Each Clock Zone Includes:
▪ Programmable Clock Generator
▪ Programmable Frame Sync Generator
▪ TDM Streams From 2-32 Time Slots
▪ Support for Slot Size:
8, 12, 16, 20, 24, 28, 32 Bits
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▪ Data Formatter for Bit Manipulation

➢ Wide Variety of I2S and Similar Bit Stream Formats
➢ Integrated Digital Audio Interface Transmitter (DIT) Supports:
▪ S/PDIF, IEC60958-1, AES-3, CP-430 Formats
▪ Up to 16 transmit pins
▪ Enhanced Channel Status/User Data
➢ Extensive Error Checking and Recovery
Two Inter-Integrated Circuit Bus (I2C Bus™) Multi-Master and Slave Interfaces
Two Multichannel Buffered Serial Ports:
➢ Serial-Peripheral-Interface (SPI)
➢ High-Speed TDM Interface
➢ AC97 Interface
Two 32-Bit General-Purpose Timers
Dedicated GPIO Module With 16 pins (External Interrupt Capable)
Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module
IEEE-1149.1 (JTAG ) Boundary-Scan-Compatible
Package Options:
➢ 208-Pin PowerPAD™ Plastic (Low-Profile) Quad Flatpack (PYP)
➢ 272-BGA Packages (GDP and ZDP)
0.13-µm/6-Level Copper Metal Process
➢ CMOS Technology

3.3-V I/Os, 1.2 -V Internal (GDP & PYP)

• 3.3-V I/Os, 1.4-V Internal (GDP)(300 MHz only)

TMS320C6713 DSK Overview Block Diagram

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Procedure for CC studio V3.1

1. On desktop double click on icon setup CC studio V3.1.

2. One window will open with 3 column.

a) 1st column My system

b) 2nd Column processor selection

c) 3rd column description about the processor

3. In the 1st column, under My system right click and remove the processor, click Yes.

4. To add the processor to the My system:

In the 2nd column, a) Family - > C67xx, Platform -> simulator

b) Double click on C6713 device cycle accurate simulator

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5. Click on save and quit (Left side down), then click -> Yes.

6. Project window will open. Click on Project -> New

7. Project Creation (it creates folder)

Project name -> xyz (Any name)

Location -> C:\CCStudio_v3.1\MyProjects\

Target -> TMS320C67xx

then click on Finish

8. Under project, click on + mark and expand the project.

9. File -> New -> Source file

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10. Save the file in your folder, save in -> Local disk (C) -> CCStudio_v3.1 -> MyProjects -> your project (xyz) -> with name
and extension.c. For example: xyz.c

11. Add the saved file to your project by right click on Source -> Add files to project

Browsing the file from your poject, Look in -> Local disk (C) -> CCStudio_v3.1 -> My Projects -> your project (xyz) -> File
(xyz.c) -> open

12. To add the library file to the project right click on libraries-> add files to project

Look in -> Local disk (C) -> CCStudio_v3.1 -> C6000 -> cgtools -> lib -> rts6700, open

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13. To add the command file to the project right click on source -> add files to project

Look in -> Local disk (C) -> CCStudio_v3.1 -> tutorial -> dsk6713 -> hello1 (*File of type -> Linker Command file) -> hello

14. Type the program, then click on save

15. Build the program by clicking on Project -> Build Target, or Rebuild target

shortcut key is F7

16. File->load program. One pop up window will appear their open Debug folder -> Select your project name file with .out
extension -> open

17. Debug->Run

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Enter the sufficient values, if necessary

18. To check graph (common for all the Part-B experiment)

View-> Graph -> Time/Frequency

Start address y (O\p Variable)

Display Data Size 8 (example: o/p count is 7 then 8)
Data Plot Style Bar

❖ Only for N-Point Dft

View-> Graph -> Time/Frequency

Display Type Dual time

Interleaved data sources Yes
Start address y
Display Data Size o/p count + 1
DSP Data Type 32 bit IEEE Floating point
Autoscale Off
Maximum Y - value 15 or 20
Data Plot Style Bar

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EXPERIMENT-01
LINEAR CONVOLUTION

AIM:- To compute the linear convolution of the given input sequence x(n) & the impulse response of the system
h(n) using “c- programming”.

/* program to implement linear convolution */

#include<stdio.h>
int y[20];
main()
{
int m=3;
int n=4;
int i=0,j;
int x[15]={1,2,3,4,0,0,0,0,0,0};
int h[15]={1,2,3,0,0,0,0,0,0};
for(i=0;i<m+n-1;i++)
{ y[i]=0;
for(j=0;j<=i;j++)
y[i]+=x[j]*h[i-j];
}
for(i=0;i<m+n-1;i++)
printf("%d\n",y[i]);
}

Figure:

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Results and Inference:

y(n) = {1, 4, 10, 16, 17, 12}

Linear Convolution for Two Sequences is Calculated and Verified using CodeComposer Studio and
DSP Hardware Kit.

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EXPERIMENT-02
CIRCULAR CONVOLUTION

Aim: - To compute the circular convolution of the given twosequences using “c-programming”.

/* program to implement circular convolution */

#include<stdio.h>
int m,n,x[30],h[30],y[30],i,j,k;
void main()
{
printf(" Enter the length of the first sequence\n");
scanf("%d",&m);
printf(" Enter the length of the second sequence\n");
scanf("%d",&n);
printf(" Enter the first sequence\n");

for(i=0;i<m;i++)
scanf("%d",&x[i]);
printf(" Enter the second sequence\n");for(j=0;j<n;j++)
scanf("%d",&h[j]);

if(m-n!=0)
{
if(m>n)
{
for(i=n;i<m;i++)
h[i]=0;
n=m;
}

for(i=m;i<n;i++)
x[i]=0;
m=n;
}
printf("the circular convolution is\n");
for(i=0;i<n;i++)
{ y[i]=0;
for(j=0;j<n;j++)
{

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k=i-j;
if(k<0)
k=k+n;
y[i]=y[i]+x[j]*h[k];
}
printf("%d \t",y[i]);
}
}

Figure:

Results and Inference:

Enter the length of the first sequence4

Enter the length of the second sequence4

Enter the first sequence1 2 3

4

Enter the second sequence1 2

34

The circular convolution is26

28 26 20

y[n] = [26 28 26 20]

Circular Convolution for Two Sequences is Calculated and Verified using CodeComposer Studio
and DSP Hardware Kit.

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EXPERIMENT-03
N-Point DFT

AIM: - To compute the n (=4/8/16) point dft of the given sequenceusing “c- programming”.

/* program to implement N point DFT */

#include<stdio.h>
#include<math.h>
short N=4;
short x[4]={2,3,4,5};
float pi=3.1416; float
sumre=0;
float sumim=0;
float cosine=0;
float sine=0;
float out_sumre[8]={0.0};
float out_sumim[8]={0.0};
void main()
{
int n,k=0;
for(k=0;k<N;k++)
{
sumre=0;
sumim=0;

for(n=0;n<N;n++)
{
cosine=cos(2*pi*k*n/N);
sine=sin(2*pi*k*n/N);
sumre=sumre+x[n]*cosine;
sumim=sumim-x[n]*sine;
}
out_sumre[k]=sumre;
out_sumim[k]=sumim;
printf("[%d] %7.3f %7.3f\n\n",k,out_sumre[k],out_sumim[k]);
}
}

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Figure(1):Sum of real part (out_sumre)

Figure(2):Sum of Imaginary part (out_sumim)

Results and Inference:-

[0] 14.000, 0.000, [1] -2.000, 2.000, [2] -2.000, 0.000, [3] -2.000, -2.000

N-Point DFT of a Sequence is Calculated and Verified using Code Composer

Studioand DSP Hardware Kit.

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Part B Assignment Questions

1. Write the C program to compute linear convolution for the given sequences.
x(n)=(-4,3,2) h(n)=(5, 6, 7, 8)
2. Write the C program to compute circular convolution for the given sequences.
x(n)=(2,5) h(n)=(3,4,8,7).
3. Write the C program to compute N point DFT for the given sequences.
x(n)=(1,8,5,3) h(n)=(2,3,4,7).

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Open Ended Experiment

Experiment 01

Compare frequency response of FIR Filter using various window function in SIMULINK/MATLAB

MATLAB code:

clc;
clear all;
close all;
n=20;
fp=200;
fs=600;
f=1000;
wp=2*(fp/f)
ws=2*(fs/f)
wn=[wp,ws]
%window=boxcar(n+1); % rectangular window
%window=bartlett(n+1);% traiangular window
%window=hamming(n+1);% hamming wondow
%window= hanning(n+1);% hanning window
window= kaiser(n+1); % kasiser window
wn=2*(fp/fs)
%b=fir1(n,wn,window)
b=fir1(n,wn,'high',window)
[H,w]=freqz(b,1)
subplot(2,1,1)
plot(w/pi, 20*log(abs(H)))
xlabel('nf')
ylabel('mag in dB')
title("mag response")
subplot(2,1,2)
plot(w/pi, angle(H))
xlabel('nf')
ylabel('mag in dB')
title("phase response")

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 Digital Signal Processing Lab

SIMULINK MODEL

Create a Lowpass Filter in Simulink

You can use the Digital Filter Design block to design and implement a digital FIR or IIR filter. In this
topic, you use it to create an FIR lowpass filter:
➢ Open Simulink and create a new model file.
➢ From the DSP System Toolbox™ Filtering library, and then from the Filter Designs library, click-
and-drag a Digital Filter Design block into your model.
➢ Double-click the Digital Filter Design block.
➢ The filter designer app opens.
➢ Set the parameters as follows, and then click OK:
• Response Type = Lowpass
• Design Method = FIR, Equiripple
• Filter Order = Minimum order
• Units = Normalized (0 to 1)
• wpass = 0.2
• wstop = 0.5
➢ Click Design Filter at the bottom of the app to design the filter.
➢ Your Digital Filter Design block now represents a filter with the parameters you specified.
➢ From the Edit menu, select Convert Structure.
➢ The Convert Structure dialog box opens.
➢ Select Direct-Form FIR Transposed and click OK.
➢ Rename your block Digital Filter Design - Lowpass.
Create a Highpass Filter in Simulink
Double-click the Digital Filter Design block. The filter designer app opens.
➢ Set the parameters as follows:
• Response Type = Highpass

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 Digital Signal Processing Lab

• Design Method = FIR, Equiripple

• Filter Order = Minimum order
• Units = Normalized (0 to 1)
• wstop = 0.2
• wpass = 0.5
Design - Highpass.
Filter High-Frequency Noise in Simulink
➢ Add block:
• Icon shape = rectangular
• List of signs = ++
➢ Random Source block:
• Source type = = Uniform
• Minimum = 0
• Maximum = 4
• Sample mode = Discrete
• Sample time = 1/1000
• Samples per frame = 50
➢ Sine Wave block:
• Frequency (Hz) = 75
• Sample time = 1/1000
• Samples per frame = 50
➢ Time Scope block:
• File > Number of Input Ports > 3
• View > Configuration Properties. Open the Time tab and set Time span = One frame period
Connect the blocks as shown in the following figure. You might need to resize some of the blocks to
accomplish this task.
In the Modeling tab, click Model Settings. The Configuration Parameters dialog box opens.
In the Solver pane, set the parameters as follows, and then click OK:
• Start time = 0
• Stop time = 5
• Type = Fixed-step
• Solver = Discrete (no continuous states)
In the Simulation tab, select Run. The model simulation begins and the scope displays the three input
signals.

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