electronics

Article
A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in
28 nm CMOS Technology
Xu Bai 1,2, * , Jianzhong Zhao 1 , Shi Zuo 1,2 and Yumei Zhou 1,2
1 Smart Sensing R&D Centre, Institute of Microelectronics of Chinses Academy of Science, Beijing 100029,
China; [email protected] (J.Z.); [email protected] (S.Z.); [email protected] (Y.Z.)
2 Institute of Microelectronics, University of Chinese Academy of Sciences, 19A Yuquan Rd., Shijingshan
District, Beijing 100049, China
* Correspondence: [email protected]; Tel.: +86-152-2230-6300




Received: 16 January 2019; Accepted: 16 March 2019; Published: 22 March 2019


Abstract: This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS)
transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge
output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated
common mode voltage over process, voltage and temperature (PVT) variations. The receiver was
composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common
mode voltage shifter with an error amplifier shifted the common mode voltage of the input
signal to the required range, thereby the following rail-to-rail comparator obtained the maximum
transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology,
and had an area of 1.46 mm2 . The measured results showed that the output swing of the transmitter
was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power
consumption of each lane was 16.51 mW under a 1.8 V power supply.

Keywords: LVDS; high-speed serial interface; transmitter; receiver; low-power

1. Introduction
While scaled CMOS technology continues to enhance on-chip operating speeds, the power
dissipation also increases at the same time. This means that reducing power consumption is critical for
battery-powered systems to extend battery life. Low voltage differential signaling (LVDS), as one of
the data transmission standards, is now pervasive in communication networks and is used extensively
in applications such as laptop computers [1], office imaging [2,3], and medical [4] and automotive [5,6]
applications. It features a low-voltage swing (250–400 mV) and achieves a high data rate (up to several
gigahertz per single pair) with less power dissipation. A typical LVDS serial link [7,8] point-to-point
communication is shown in Figure 1, and involves a single transmitter (TX) and receiver (RX) pair.
A current source (Is) is derived from the TX, and the output amplitude is formed by the current source
flowing through the terminated resistor (RT ) to establish voltage in the input of RX. By changing the
current direction, the same amplitude with the opposite polarity is created to generate the logic of
zeros and ones. The simple termination, low-power, and low-noise characteristics have gradually
made LVDS the technology of choice for gigabit-per-second serial transmission. In addition, the wide
common mode input of LVDS makes its devices easily interoperable with other differential signaling
technologies [9–11].

Electronics 2019, 8, 350; doi:10.3390/electronics8030350 www.mdpi.com/journal/electronics

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Electronics 2019, 8, 350 2 of 9
Electronics 2019, 8, x FOR PEER REVIEW Is 2 of 10
Vinp
Is
Vinp TX RT RX
Vinn
TX RT RX
Vinn

Figure 1. Low voltage differential signaling (LVDS) serial link communication block.
Figure 1. Low voltage differential signaling (LVDS) serial link communication block.
Figure 1. Low voltage differential signaling (LVDS) serial link communication block.
In general, the architecture of LVDS drivers is divided into fully-differential NMOS-only style
[12],In general, the architecture
fully-differential PMOS-onlyofstyle LVDS [13]drivers is divided into
and complementary MOSfully-differential
style [14–16]. AsNMOS-only
shown in
In general, the architecture of LVDS drivers is divided into fully-differential NMOS-only style
style
Figure[12],
2, fully-differential
all configurationsPMOS-only style MOS
consist of four [13] and complementary
switches arranged in MOSan style [14–16].
H-bridge As shown
structure. The
[12], fully-differential PMOS-only style [13] and complementary MOS style [14–16]. As shown in
in Figure 2, all
NMOS-only styleconfigurations
LVDS driver, consistshown in of Figure
four MOS switches
2a, works wellarranged
if the supplyin an H-bridge
voltage (VDD)structure.
is 2.5 V
Figure 2, all configurations consist of four MOS switches arranged in an H-bridge structure. The
The NMOS-only
or greater style LVDSwhen
[17]. However, driver,theshown
supply in Figure
voltage2a, is works
scaled welldown if the
(1.8supply
V for voltage
28 nm (VDD)
CMOS
NMOS-only style LVDS driver, shown in Figure 2a, works well if the supply voltage (VDD) is 2.5 V
is 2.5 V or greater
technology), [17].applicable,
it is not However,as when
theretheis supply voltage
not enough is scaled
voltage down (1.8
headroom. V for 28tonm
According theCMOS
LVDS
or greater [17]. However, when the supply voltage is scaled down (1.8 V for 28 nm CMOS
technology), it is not applicable,
standard specifications as there isVnot
[18], a 1.125–1.325 enoughmode
common voltage headroom.
voltage range andAccording
250–400tomVthe output
LVDS
technology), it is not applicable, as there is not enough voltage headroom. According to the LVDS
standard
swing of specifications
the output signals [18],isa required,
1.125–1.325 whichV common modethe
would cause voltage range(M1a
transistors and 250–400
and M2a) mV to output
cut off.
standard specifications [18], a 1.125–1.325 V common mode voltage range and 250–400 mV output
swing of the output
To overcome the signals
supply isvoltage
required, which would
headroom cause
issues, the transistors
PMOS-only (M1a in
(shown andFigure
M2a) to2b)cut and
off.
swing of the output signals is required, which would cause the transistors (M1a and M2a) to cut off.
To overcome the supply
complementary MOS (shownvoltagein headroom
Figure 2c)issues,
LVDS PMOS-only (shown
drivers need to beinaddressed.
Figure 2b) and complementary
A benefit of PMOS-
To overcome the supply voltage headroom issues, PMOS-only (shown in Figure 2b) and
MOS
only (shown in Figure
style drivers 2c) LVDS
is that they can drivers
workneed to be addressed.
without A benefit
the body effect. of PMOS-only
However, style drivers
the inherent speed
complementary MOS (shown in Figure 2c) LVDS drivers need to be addressed. A benefit of PMOS-
is that theyincan
limitation PMOSwork without
devices the body
precludes effect.
their However,
use in high speedthe data
inherent speed limitation
communication. in PMOS
To achieve the
only style drivers is that they can work without the body effect. However, the inherent speed
devices precludes their use in high speed data communication. To achieve
same speed as CMOS style drivers, the size of the transistors must be increased. Consequently, the the same speed as CMOS
limitation in PMOS devices precludes their use in high speed data communication. To achieve the
style drivers,
area cost the sizeconsumption
and power of the transistors must
will also be increased.
increase. Comparing Consequently, the area cost
the above-mentioned anddrivers,
LVDS power
same speed as CMOS style drivers, the size of the transistors must be increased. Consequently, the
consumption
the complementary will alsoMOS increase.
styleComparing
driver is the the above-mentioned
optimum choice LVDS drivers,
for LVDS the complementary
transmission systems
area cost and power consumption will also increase. Comparing the above-mentioned LVDS drivers,
MOS style under
operating driver lowis thesupply
optimum choice
voltage, asfor
it isLVDS transmission
not only compatible systems operating
with the LVDS under lowbut
standard, supply
also
the complementary MOS style driver is the optimum choice for LVDS transmission systems
voltage, as itthe
faster than is not
other only compatible with the LVDS standard, but also faster than the other options.
options.
operating under low supply voltage, as it is not only compatible with the LVDS standard, but also
faster than the other options.
Is Is Is

Vinp Is Vinn Vinp Is Vinn Vinp Is Vinn

M1a M2a M1b M2b M1c M2c
Vinp Vinn Vinp Vinn Vinp Vinn
M1a M2a RT M1b M2b RT M1c M2c RT
Vinn Vinp
RT Vinn Vinp
RT Vinp Vinn
RT
M3a M4a M3b M4b M3c M4c
Vinn Vinp Vinn Vinp Vinp Vinn
M3a M4a M3b M4b M3c M4c
Is Is Is

Is Is Is
(a) (b) (c)
Figure 2.
Figure (a)
2. Simplistic
Simplistic circuit
circuitofofLVDS
LVDSoutput (b) (a)(a)NMOS-only
outputdriver:
driver: NMOS-onlystyle; (b)(b)
style; (c)
PMOS-only style;
PMOS-only (c)
style;
Complementary
(c) ComplementaryMOSMOS style.
style.
Figure 2. Simplistic circuit of LVDS output driver: (a) NMOS-only style; (b) PMOS-only style; (c)
Complementary MOS style.
In
In this
this paper,
paper,aa2.5
2.5Gbps
Gbps10-lane
10-lanelow-power
low-powerLVDS LVDStransceiver
transceiverisispresented.
presented.The
Thetransceiver
transceiver can
can
operate
operate at ataadata
datarate
rateup
uptoto2.5
2.5Gbps,
Gbps,and
andisisfully
fullycompatible
compatiblewithwithANSI/TIA/EIA-644-A
ANSI/TIA/EIA-644-A standards.
In this paper, a 2.5 Gbps 10-lane low-power LVDS transceiver is presented. The transceiver can
The
Thepaper
paperis organized
is organizedas follows: Section
as follows: 2 describes
Section the architecture
2 describes of the proposed
the architecture of the LVDS transceiver,
proposed LVDS
operate at a data rate up to 2.5 Gbps, and is fully compatible with ANSI/TIA/EIA-644-A standards.
and presentsand
transceiver, some relatedsome
presents simulation
relatedresults.
simulationIn Section
results.3,Inthe measurement
Section results are discussed.
3, the measurement results are
The paper is organized as follows: Section 2 describes the architecture of the proposed LVDS
Finally, a summary
discussed. Finally, aand the conclusions
summary are outlinedare
and the conclusions in Section
outlined4.in Section 4.
transceiver, and presents some related simulation results. In Section 3, the measurement results are
discussed.
2. Finally, a summary and the conclusions are outlined in Section 4.
2. Architecture
Architecture Design
Design
The
Theproposed
2. Architecture 10-lane,
Design
proposed low-power,
10-lane, LVDS
low-power, transceiver
LVDS is shown
transceiver in Figure
is shown in3.Figure
Each lane is comprised
3. Each lane is
of a receiver followed by a transmitter. It employs differential data transmission
comprised of a receiver followed by a transmitter. It employs differential data transmission and the receiver
and theis
The
configured proposed 10-lane, low-power,
as a switched-polarity LVDS
signal generator. transceiver is
The receiver shown in
is receiver
composed Figure 3. Each
of a pre-stage lane is
receiver is configured as a switched-polarity signal generator. The is composed of a common
pre-stage
comprised
mode of
voltage a receiver
(Vcm) followed
shifter by a
andshifter transmitter.
a rail-to-rail It employs differential data transmission and the
common mode voltage (Vcm) and a comparator (COMP), while
rail-to-rail comparator the transmitter
(COMP), includes a
while the transmitter
receiver is configured as a switched-polarity signal generator. The receiver is composed of a pre-stage
includes a CMOS H-bridge output driver with a common mode feedback (CMFB) circuit, a high-
common mode voltage (Vcm) shifter and a rail-to-rail comparator (COMP), while the transmitter
includes a CMOS H-bridge output driver with a common mode feedback (CMFB) circuit, a high-
Electronics 2019, 8, 350 3 of 9

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Electronics 2019, 8, x FOR PEER REVIEW 3 of 10
CMOS H-bridge output driver with a common mode feedback (CMFB) circuit, a high-speed level
speedlevel
shifter
speed leveland
(LS) shifter
shifter (LS)and
andpre-emphasis
pre-emphasis
(LS) pre-emphasis
(PE) driver.(PE)(PE)
In driver.In
addition,
driver. In
twoaddition,
bandgap
addition, two
two bandgap(BGR)
references
bandgap references (BGR)are
are embedded
references (BGR) are
embedded
in the scheme
embedded in
in thethe scheme
to provide to
scheme proper provide proper
DC proper
to provide bias forDC DC bias
receivers for
bias forandreceivers and
transmitters,
receivers transmitters, respectively.
respectively.respectively.
and transmitters, In
In the design,
In
thedesign,
the
the design,thethedata
differential differential data
are firstly
differential data arefirstly
firstly
addressed
are by addressed bythe
the receiver,
addressed by thereceiver,
then receiver, thenthe
the transmitter
then the transmitter
deals with the
transmitter deals with
datawith
deals and
the
sendsdata
themand outsends
in them
accordanceout in accordance
with specified with specified
requirements. requirements.
Therefore, onlyTherefore,
if
the data and sends them out in accordance with specified requirements. Therefore, only if both the both only
the if both
receiver the
and
receiver
transmitter
receiver and
andare transmitter are
operated properly
transmitter operated
can the
are operated properly can
transmitted
properly the transmitted
signals
can the be output.
transmitted signals be output.
The detailed
signals be output. The detailed
implementation
The detailed
implementation
of the transceiver of the
will transceiver
be expatiated will
in be
the expatiated
following in the
sections.following
implementation of the transceiver will be expatiated in the following sections. sections.

BGR BGR
BGR BGR

Lane10
Lane10
Lane2
Lane2
Lane1
INP Receiver Transmitter Lane1
INP Receiver Transmitter Voutp
CMFB Voutp
Vcm LS CMFB Voutn
RT LS driver
RT Vcm
shifter
COMP
COMP driver Voutn
INN shifter
INN
PE
PE
driver
driver

Figure3.
Figure
Figure 3.3.Simplistic
Simplisticcircuit
Simplistic circuitof
circuit of10-lane
of 10-laneLVDS
10-lane LVDStransceiver.
LVDS transceiver.

2.1. Receiver
2.1.Receiver
Receiver
2.1.
According
Accordingto totoLVDS
LVDSspecifications
specifications[18],
[18],aaareceiver
receiveris required
requiredto operate
operatein a wide input common
According LVDS specifications [18], receiver isisrequired totooperate ininaawide
wideinput
inputcommon
common
mode
mode voltage
voltage range of0.05–2.35
of 0.05–2.35V.V.Therefore,
Therefore, withwiththethe1.8 1.8
V V supply
supply voltage,
voltage, the the receiver
receiver firstlyfirstly
needs
mode voltage range of 0.05–2.35 V. Therefore, with the 1.8 V supply voltage, the receiver firstly needs
needs to achieve the common mode voltage conversion.
Figure44Figure 4the
shows the simplistic
circuitofofacircuit of a
totoachieve
achieve thecommon
the common modevoltage
mode voltage conversion.
conversion. Figure showsthe
shows simplistic
simplistic circuit apre-stage
pre-stage
pre-stage
common common
mode modeshifter,
voltage voltage shifter,
which which aincludes
includes current aregulator
current regulator
and an andamplifier.
error an error amplifier.
The error
common mode voltage shifter, which includes a current regulator and an error amplifier. The error
The error amplifier
amplifier detects the detects
the the common
common mode voltage
mode voltage
voltage difference difference
between between input
input data
data (INPdata (INP
(INP and
INN)INN)
and INN) and
amplifier detects common mode difference between input and and
and reference
reference voltage
voltage (VREF)
(VREF) andand amplifies
amplifies thethevoltage
voltagedifference
differencetotocontrol
control thethe current regulator
regulator by
by
reference voltage (VREF) and amplifies the voltage difference to control the current regulator by
injecting
injecting or
or extracting
extracting currents
currents from
from resistors
resistors R1R1 and
and R2.
R2. As
As aaresult,
result, voltage
voltage drops
drops across
across R1
R1 and
and R2
R2
injecting or extracting currents from resistors R1 and R2. As a result, voltage drops across R1 and R2
are
aregenerated,
generated,andand
andthethe
thecommon
commonmodemode voltage
modevoltage
voltageis isisshifted [19].
shifted[19]. ItItisisobvious
[19].It obviousthat thatthetheshifted
shiftedcommon
common
are generated, common shifted is obvious that the shifted common
mode
mode voltage
voltage isisaffected
affected bybyVREF.
VREF.Thus,
Thus,thethe
valuevalue of VREF
of VREF waswas
set setat 0.9
at V for
0.9 V the
for following
the rail-to-rail
following rail-to-
mode voltage is affected by VREF. Thus, the value of VREF was set at 0.9 V for the following rail-to-
comparator
rail to
comparator obtain
to a higher
obtain a gain.
higher
rail comparator to obtain a higher gain. gain.

20/1 20/1 VREF

20/1 20/1 20/1 VREF
20/1
R1 M4
M4 M5
M5 M6
M6 M7 M8 M9 M10
INP R1 M7 M8 M9 M10
INP
R3
R3
R2 40/0.5 40/0.5 40/0.5 40/0.5
INN R2 Vf 40/0.5 40/0.5 40/0.5 40/0.5
INN Vf
OP R4
R4 ON
OP ON 5/1
M1 M2 M3 5/1
M11
M1 M2 M3
60/1 M11
60/1 60/1
60/1 60/1
60/1

Currentregulator
Current regulator Erroramplifier
Error amplifier

Figure 4.4.The
Figure4. input
Theinput common
inputcommon mode
commonmode voltage
modevoltage shifter.
voltageshifter.
shifter.
Figure The
A simple rail-to-rail comparator [20,21], as shown in Figure 5,5,was constructed as
asaaacomposite
composite of
AAsimple
simplerail-to-rail
rail-to-railcomparator
comparator[20,21],
[20,21],asasshown
shownin inFigure
Figure5, wasconstructed
was constructedas compositeof of
PPand NMOS
andNMOS pairs.
NMOSpairs. The
pairs.The amplifier
Theamplifier with
amplifierwith rail-to-rail
withrail-to-railinput identifies
rail-to-railinput the
inputidentifies voltage
identifiesthe difference
thevoltage from
voltagedifference the
differencefrom input
fromthethe
P and
data
input(OP
dataand(OPON)and and
ON) converts
and them into
converts them currents
into through
currents the input
through the trans-conductor
input cell (M1–M4).
trans-conductor cell (M1–
input data (OP and ON) and converts them into currents through the input trans-conductor cell (M1–
After this,
M4).After
Afterthethis,
currents are bothare
thecurrents
currents mirrored and summed
bothmirrored
mirrored up at the node
andsummed
summed upatatN1,
thebefore the
N1,data
nodeN1, is reinstituted
before thedata
dataisis
M4). this, the are both and up the node before the
and reshaped
reinstitutedand by the last-stage
andreshaped
reshapedby shaping
bythe buffer.
thelast-stage
last-stageshaping
shapingbuffer.
buffer.
reinstituted
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2019, 8, FOR PEER REVIEW 4 of109
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80/1 20/0.15 80/0.15 20/0.15

80/1 200/1 20/0.15 20/0.15 80/0.15 20/0.15
200/1 20/0.15 20/0.15 80/0.15 15/0.15 30/0.15
20/0.15 80/0.15 15/0.15 30/0.15
20/0.15 20/0.15
20/0.15
OP 60/0.15 ON
20/0.15
OP 60/0.15 ON N1 Vout
BGR N1 Vout
BGR M1 M3 60/0.15 M4 M2
M1 M3 60/0.15 M4 M2
Iref
Iref
80/0.15 20/0.15 25/0.15
50/1 80/0.15 20/0.15 25/0.15 10/0.15 20/0.15
50/1 20/0.15 25/0.15 10/0.15 20/0.15
10/1 20/1 20/0.15 25/0.15
10/1 20/1

Rail to rail comparator Shaping buffer

Rail to rail comparator Shaping buffer
Figure 5. Schematic of the rail-to-rail comparator.
Schematicofofthe
Figure5.5.Schematic
Figure therail-to-rail
rail-to-railcomparator.
comparator.

2.2.
2.2. Transmitter
Transmitter
2.2. Transmitter
In
In this
this paper, the transmitter contained
contained three parts: aa high-speed
high-speed level
level shifter,
shifter, aa pre-emphasis
pre-emphasis
In this paper, the transmitter contained three parts: a high-speed level shifter, a pre-emphasis
driver
driver and
and anan output driver. TheThe high-speed
high-speed level
level shifter
shifter [22,23]
[22,23] was
was introduced
introduced to to achieve
achieve the
the
driver and an output driver. The high-speed level shifter [22,23] was introduced to achieve the
different
different voltage
voltagedomain
domainconversion
conversionininthethepre-stage
pre-stageofof
the transmitter,
the transmitter,whose
whose circuit is presented
circuit in
is presented
different voltage domain conversion in the pre-stage of the transmitter, whose circuit is presented in
Figure
in Figure6. A
6. pair of of
A pair NMOS
NMOS devices
devices(M3
(M3andandM4)
M4)receive
receivethe
thelow-voltage
low-voltageinput
inputsignals
signals (Dp_L
(Dp_L and
and
Figure 6. A pair of NMOS devices (M3 and M4) receive the low-voltage input signals (Dp_L and
Dn_L)
Dn_L) andand convert
convert them
them into
into high-voltage
high-voltage signals
signals through
through the
the positive
positive feedback
feedback transistors
transistors (M1
(M1 and
and
Dn_L) and convert them into high-voltage signals through the positive feedback transistors (M1 and
M2).
M2). Then,
Then, the
the buffer
buffer chain
chain with
with several
several inverters
inverters reshapes
reshapes the
the output
output signals
signals under
under the
the high-voltage
high-voltage
M2). Then, the buffer chain with several inverters reshapes the output signals under the high-voltage
(VDDH)
(VDDH) supply.
(VDDH) supply.
VDDH
VDDH
4/0.15 4/0.15
4/0.15 4/0.15
M1 M2
Buffer chain M1 M2 Buffer chain
Buffer chain Buffer chain
Dp_H N1 N2 Dn_H
Dp_H N1 N2 Dn_H

30/0.15 30/0.15
30/0.15
Dp_L 30/0.15
Dn_L
Dp_L M3 M4 Dn_L
M3 M4

Figure 6.
Figure Simplified schematic
6. Simplified schematic level
level shifter.
shifter.
Figure 6. Simplified schematic level shifter.
Figure 77 shows
Figure shows thethe proposed
proposed transmitter
transmitter output
output driver
driverbased
basedon onthe
theCMOS
CMOSH-bridge
H-bridgestructure.
structure.
Figure
As Figure 7 shows
Figure 77 shows,
shows, thethe proposed
the output
output stage transmitter
stage ofof the
the driveroutput
driver usesdriver
uses the based
the PMOS
PMOS and on the
and NMOS CMOS H-bridge
NMOS configuration.
configuration. A structure.
A simple
simple
As
As Figure mode
common 7 shows, the output
feedback (CMFB)stage of the
circuit driverwith
[24,25], usestransistors
the PMOSM5–M8,and NMOS is configuration.
used to stabilize A simple
the output
common mode feedback (CMFB) circuit [24,25], with transistors M5–M8, is used to stabilize the
common
common mode
mode feedback
voltage (CMFB)
(Vcm), andcircuit
is less[24,25], with on
dependent transistors
PVT. The M5–M8,
two is used to
differential stabilize
output the
voltages
output common mode voltage (Vcm), and is less dependent on PVT. The two differential output
output
(Voutpcommon
and Voutn)mode voltage (Vcm),
areVoutn)
averaged formand is less dependent on PVT. The tworesistors
differential output
voltages (Voutp and are to
averaged a common
to form amode
commonvoltage
mode(Vcm) by two
voltage (Vcm) by two (R1resistors
and R2),
voltages
which is(Voutp
compared and Voutn)
with the are averaged
designed to
referenceform a common
common mode mode voltage
voltage (Vbg).(Vcm)
The by two
differenceresistors
is then
(R1 and R2), which is compared with the designed reference common mode voltage (Vbg). The
(R1 and R2),
amplified and which is compared
converted intoand with the mode
the converted
common designed reference
current common
to adjust thecurrent mode mode
common voltage (Vbg).(Vcm). The
difference is then amplified into the common mode to adjustvoltage
the common
difference
In addition,is then amplified and converted into the common mode current to adjust the common
mode voltagean Rc and
(Vcm). InCc pole-zero
addition, an Rccompensation network
and Cc pole-zero is exploitednetwork
compensation to obtain an adequate
is exploited phase
to obtain
mode
marginvoltage
of CMFB(Vcm). In addition,
under the an Rc and
conditions Cc pole-zero
created by the compensation
PVT variations. network
Meanwhile, is exploited
a cascade to obtain
current
an adequate phase margin of CMFB under the conditions created by the PVT variations. Meanwhile,
an adequate phase ismargin of to
CMFB under theprecision
conditions created byatthe PVT variations. Meanwhile,
amirror
cascade(M9–M12)
current mirrorutilized
(M9–M12) provide high
is utilized to providecurrent bias
high precision a 1.8 V voltage
current bias atsupply.
a 1.8 V voltage
a cascade current mirror (M9–M12) is utilized to provide high precision current
In addition, a pre-emphasis driver with a simple pulse-width modulation (PWM) technique bias at a 1.8 V voltage
[26,27]
supply.
supply.
is used in the transmitter to enhance signal integrity. A simplistic circuit of this pre-emphasis driver is
presented in Figure 8. The pre-emphasis driver exploits the timing relationship between signals and
delay signals to establish the signal-related pulse (UP and DN), which is only enabled at the rise and
fall of the signal [28,29]. During the signal transition, the pre-emphasis driver adds a current to the
output node, and also extracts the current from the output node by the UP and DN pulses, so that the
 120/1 Vbp M11 M12
M9
120/1 Vbp M11
240/1 M12
240/1
M9
240/1 1600/1 240/1 PU
M10 1600/1 PU
M10 200/1 80/0.15 80/0.15 30/0.15
240/1 200/1 Vinp Vinn
80/0.15 M2 80/0.15 30/0.15
240/1
10/1 200/1M6
M5 200/1 800/1 Vinp M1 Vinn Voutp
M5 M6 800/1 M1 M2 Vop
Electronics 2019, 8, 350 10/1 Voutp 5 of 9
Vop
BGR Vbg
BGR Vbg Vcm Voutn
M7 M8 Vcm Vinn R1 R2 Vinp Voutn Von
Iref M7 M8 Vinn R1
M3 R2
M4 Vinp Von
280/0.5 280/0.5 60/0.15 60/0.15
rise and Ireftime
fall is
decreased.
280/0.5 Figure
280/0.59
shows the60/0.15 M3
eye diagram M4 of the transmitter
PD after the channel,
Vbn Rc 1600/1 60/0.15 PD
which operates at Vbn 2.5 Gbps. Figure 9aRc presents
800/1 the simulated results
1600/1 of the
20/0.15 eye diagram without a
10/1 40/1 20/1 80/1 Cc 800/1 20/0.15
pre-emphasis 10/1
driver, while the
40/1 20/1
simulated
80/1 Cc results of120/1
the eye diagram 120/1 with a pre-emphasis driver are
shown in Figure 9b. As shown, the pre-emphasis driver 120/1 is not only120/1able to shorten the rise time but

also improves
Electronics 2019, 8, xthe
FOR amplitude of theCMFB
PEER REVIEW
Reference output signal. Output stage CH. & Pack. model 5 of 10
Reference CMFB Output stage CH. & Pack. model

Figure 7. The architecture of the output driver.

120/1 Vbp Figure 7. The architectureM11
of the output driver.
M12
M9
240/1 240/1
In addition, a pre-emphasis driver with a simple pulse-width 1600/1 modulation
PU (PWM) technique
In addition, M10 a pre-emphasis driver with a simple pulse-width modulation (PWM) technique
[26,27] is used in the transmitter to enhance 200/1
signal integrity.
80/0.15 A simplistic circuit of this pre-emphasis
80/0.15 30/0.15
[26,27] is used 240/1
in the transmitter to enhance
200/1 signal Vinp
integrity. A M2 Vinn
simplistic circuit of this pre-emphasis
driver is presented in 10/1 Figure 8. The
M5 M6 pre-emphasis
800/1 driver M1 exploits the timing relationship between
driver is presented in Figure 8. The pre-emphasis driver exploits the Voutp timing relationship Vop between
signals and delay
Vbg signals to establish the signal-related pulse (UP and DN), which is only enabled at
BGR delay
signals and signals to establish Vcmthe signal-related pulse (UP and DN), which is only enabled at
the rise and fall of the signal M7 [28,29].
M8 During the signalVinn transition,
R1 R2 the Voutn
Vinp pre-emphasis driver adds a
Von
the rise and fall of the signal [28,29]. During the signalM3 transition, the pre-emphasis driver adds a
current to Iref
the output node,280/0.5
and also extracts the current
280/0.5 60/0.15 fromM4the output node by the UP and DN
60/0.15
current to the output node, and also extracts the current from the output PDnode by the UP and DN
pulses, so that the rise Vbn and fall time is Rcdecreased. Figure 9 shows 1600/1 the eye diagram of the transmitter
pulses, so that the rise and fall time is decreased. 800/1 Figure 9 shows the eye diagram of the transmitter
20/0.15
after the channel,
10/1
which operates
40/1 20/1 80/1 atCc2.5 Gbps. Figure 9a presents the simulated results of the eye
after the channel, which operates at 2.5 Gbps. Figure 120/1 9a presents the simulated results of the eye
120/1
diagram without a pre-emphasis driver, while the simulated results of the eye diagram with a pre-
diagram without a pre-emphasis driver, while the simulated results of the eye diagram with a pre-
emphasis driver are shown in Figure 9b. As shown, the pre-emphasis driver is not only able to shorten
emphasis driverReference
are shown in Figure 9b. As shown, the pre-emphasis
CMFB Output stage driver is not
CH. only able
& Pack. to shorten
model
the rise time but also improves the amplitude of the output signal.
the rise time but also improves the amplitude of the output signal.
Thearchitecture
Figure7.7.The
Figure architectureof
ofthe
theoutput
outputdriver.
driver.
Dp_L
Dp_L UP
In addition, a pre-emphasis driver with a simple pulse-width Level UP
modulation (PWM) technique
Level
shifter DN
[26,27] is used in the transmitter to enhance signal integrity.shifter DN
A simplistic circuit of this pre-emphasis
driver is presented in Figure 8. The pre-emphasis Dp_L
driver exploits the timing relationship between
Dp_L
Dn_L
signals and delay signals to establish the signal-related pulse (UP and DN), which is only enabled at
Dn_L Dn_L
Dn_L
the rise and fall of the signal UP
[28,29]. During the signal transition, the pre-emphasis driver adds a
UP
DN
current to the output node, and also extracts the currentDN from the output node by the UP and DN
pulses, so that the rise and fall time is decreased. Figure 9 shows the eye diagram of the transmitter
Figure
after the channel, whichFigure
Figure8. Simplified
operates Simplifiedschematic
at 2.5 Gbps. of
Figure
schematic the pre-emphasis
9apre-emphasis
ofthe
the driver.
presents thedriver.
pre-emphasis simulated results of the eye
driver.
8.8.Simplified schematic of
diagram without a pre-emphasis driver, while the simulated results of the eye diagram with a pre-
emphasis driver are shown in Figure 9b. As shown, the pre-emphasis driver is not only able to shorten
the rise time but also improves the amplitude of the output signal.

Dp_L
UP
Level
shifter DN

Dp_L
(a) Dn_L (b)
(a) Dn_L (b)
Figure UP
Figure9.9.Simulated
Simulatedresult
resultof
ofthe
theeye
eyediagram
diagram(a)
(a)without
withoutand
and(b)
(b)with
withthe
thepre-emphasis
pre-emphasis driver.
driver.
Figure 9. Simulated result of the eye diagram (a) DN
without and (b) with the pre-emphasis driver.
3. Measured Result Analysis and Discussion
Figure 8. Simplified schematic of the pre-emphasis driver.
Figure 10 shows a chip microphotograph of the 10-lane LVDS transceiver. The entire chip was
fabricated with SMIC 28 nm CMOS technology and the total area was 1.46 mm2 . The area of each
TX/RX lane was 0.0333 mm2 , where TX and RX occupy 0.0306 mm2 and 0.0027 mm2 , respectively.
In multi-lane high-speed serial links, crosstalk and interference of lanes are important issues that
deteriorate the performance of output signals. In this paper, two lanes of the transceiver shared supply
voltage to improve the power integrity, and the BGR utilized a pair of individual supply voltages to
provide the dependable DC bias for TX and RX, respectively. Plentiful on-chip decoupling capacitors
were also inserted in the empty area to enhance signal integrity. These methods simply and effectively
suppressed output jitter.
(a) (b)
Figure 9. Simulated result of the eye diagram (a) without and (b) with the pre-emphasis driver.
multi-lane
multi-lane high-speed
high-speed serialserial links,
links, crosstalk
crosstalk andand interference
interference of
of lanes
lanes are
are important
important issues
issues that
that
deteriorate the performance of output signals. In this paper, two lanes of the
deteriorate the performance of output signals. In this paper, two lanes of the transceiver shared transceiver shared
supply
supply voltage
voltage to to improve
improve thethe power
power integrity,
integrity, andand the
the BGR
BGR utilized
utilized aa pair
pair of
of individual
individual supply
supply
voltages
voltages to to provide
provide the the dependable
dependable DC DC bias
bias for
for TX
TX and
and RX,
RX, respectively.
respectively. Plentiful
Plentiful on-chip
on-chip decoupling
decoupling
capacitors
Electronics
capacitors were
2019, also
8, 350
were also inserted
inserted in
in the
the empty
empty area
area toto enhance
enhance signal
signal integrity.
integrity. These
These methods
methods simply
6 of 9
simply
and
and effectively
effectively suppressed
suppressed output
output jitter.
jitter.

Figure
Figure 10.
10. Microphotograph
Microphotograph of
of the
the LVDS
LVDS transceiver.
LVDS transceiver.
transceiver.

An Agilent
An Agilent pulse
Agilentpulse generator
pulsegenerator
generator 81134A
81134A
81134Awaswas
usedused
was to
to produce
used 231 -1 pseudorandom
to produce
produce 223131-1
-1 pseudorandom
pseudorandom bit
bit sequence
bit sequence (PRBS)
sequence
(PRBS)
data
(PRBS) data
data patterns
patterns to
to the
the receiver,
to the receiver,
patterns while a while
receiver, while aa Tektronix
Tektronix MSO71604C
Tektronix MSO71604C
mixed signal
MSO71604C mixed signal
signal oscilloscope
mixedoscilloscope was used
oscilloscope was
to
was
used
detectto detect
the the differential
differential output output
eye eye
diagram diagram
of the of the transmitter.
transmitter. A 22-inch A 22-inch
coupled
used to detect the differential output eye diagram of the transmitter. A 22-inch coupled micro-strip coupled micro-strip
micro-strip line on
line
the on
on the
the testing
linetesting PCB
PCB acted
testing PCBasacted
the as
acted the
the transmission
transmission
as channel,
channel,
transmission the
the channel
the channel
channel, loss of
channel loss of
of which
which
loss is
is shown
is shown
which in
in Figure
in Figure
shown 11.
Figure
11.
11. The
The channel
channel
The lossloss
channel waswas
loss 2.2
2.2 dB
was dB
2.2at
dB625at
at 625 MHz,
MHz,
625 andand
MHz, 1.8
1.8 dB
and 1.8atdB at
at 1.25
dB1.25 GHz.
1.25 GHz.
GHz.

Figure
Figure 11.
Figure 11. The
11. The frequency
The frequency response
frequency response of
response the
of the
of 22-inch
the 22-inch FR4
22-inch FR4 channel.
FR4 channel.
channel.

According
According to
According to the
the measured
measured results,
results, the
the maximum
maximum data data rate
rate of
of the
the transceiver
transceiver reached
reached 2.5Gbps.
2.5Gbps.
Figure 12a,b
Figure 12a,b
Figure shows
12a,b shows
shows thethe single
the single lane
single lane of
lane of transmitter
of transmitter differential
transmitter differential output
differential output
output eye eye diagrams
eyediagrams
diagrams withwith
with22231
31-1
31 PRBS
-1 PRBS
-1 PRBS
patterns and
patterns and
patterns data
and data rates
datarates of 1.25
ratesofof
1.25 Gbps
Gbps
1.25 and
andand
Gbps 2.5 Gbps.
2.5 Gbps. Both output
Both output
2.5 Gbps. swings
swings of
Both output of the two
the two
swings operating
of operating data
data rates
the two operating rates
were
data around
wererates
around
were350 mV,
350around
mV, andand350the
the root-mean-square
root-mean-square
mV, (RMS) jitters were
(RMS) jitters(RMS)
and the root-mean-square 5.48
were 5.48 ps and
pswere
jitters 3.65
and 3.65 ps,
5.48ps, respectively.
ps respectively.
and 3.65 ps,
Figure
Figure 12c,d show
show transmitter
12c,d Figure
respectively. 12c,d show differential
transmitter transmitter output
differential output eye
eye diagrams
differential diagrams
output eyeof 1.25
1.25 Gbps
ofdiagramsGbps of and
1.25 2.5
and 2.5 Gbps
Gbps andfor
Gbps 2.5multi-
for multi-
Gbps
for multi-lane transmission communication. Similarly, their output swings were around 350 mV, but
their performance was degraded. This is due to the lane-to-lane interference of signals and power lines,
which introduced higher deterministic jitter (DJ) that deteriorated the signal integrity of the output
signals. The total power dissipation of the two operating data rates were 8.72 mW and 16.51 mW at a
1.8 V power supply for each lane.
 lane transmission communication. Similarly, their output swings were around 350 mV, but their
performance was degraded. This is due to the lane-to-lane interference of signals and power lines,
which introduced higher deterministic jitter (DJ) that deteriorated the signal integrity of the output
signals.2019,
Electronics The8,total
350 power dissipation of the two operating data rates were 8.72 mW and 16.51 mW at9
7 of
a 1.8 V power supply for each lane.

(a) (b)

(c) (d)
Figure12.
Figure 12. Measured
Measured output
output eye
eyediagrams
diagramsfor
fordifferent
differentdata rates
data (a)(a)
rates 1.25 Gbps
1.25 of single
Gbps lane;lane;
of single (b) 2.5
(b)
Gbps
2.5 of of
Gbps single lane
single (c)(c)
lane 1.25 Gbps
1.25 of multi-lane
Gbps (d)(d)
of multi-lane 2.5 2.5
Gbps of multi-lane.
Gbps of multi-lane.

Table11summarizes
Table summarizes thethe comparison
comparison of of the
the performance
performance of the
the previously
previously reported
reported LVDS
LVDS
transmitters. This LVDS transmitter, based on a complementary
transmitters. This LVDS transmitter, based on a complementary MOS H-bridge, had excellent noise
H-bridge, had excellent noise
immunityperformance,
immunity performance,with
with an
an RMS
RMS jitter
jitter of
of 3.65
3.65 ps with a data rate up to 2.5 Gbps.
Gbps. The
The proposed
proposed
LVDStransmitter
LVDS transmitteralso
alsohad
hadsuperior
superiorpower
power consumption
consumption performance
performance ofof 16.51
16.51 mW
mWat ataadata
datarate
rateof
of
2.5 Gbps, with a figure of merit (FOM) of 6.6 mW/Gbps.
2.5 Gbps, with a figure of merit (FOM) of 6.6 mW/Gbps.

Table1.1.Comparison
Table Comparison with
with previous
previous works.

Ref. Ref. [9] * [9] * [15]

[15] **** [30]
[30]** [31] **
[31] **This Work This**
Work **
Year 2016 2011 2014 2018 2019
Year 2016 2011 2014 2018 2019
Technology
Technology (nm) (nm)28 CMOS 28 CMOS 180 180CMOS
CMOS 4040CMOS CMOS 28 CMOS
28 CMOS 28 CMOS 28 CMOS
SupplySupply
voltagevoltage
(V) (V) 1.8/11.8/1 2.5
2.5 1.8/1
1.8/1 1.8/11.8/1 1.8/0.9 1.8/0.9
OutputOutput
swing (mV)
swing (mV) 350 350 313
313 320320 348 348 350 350
Data rate (Gbps)
Data rate (Gbps) 1 1 2 2 1 1 1 1 2.5 2.5
RMS jitter (ps) 2.2 7.65 4 9.8 3.65
RMS jitter (ps)
Power(mW) 8.7
2.2 7.65
15.41
47 9.8 7.9 3.65 16.51
Power(mW)
Area (mm 2) 0.009 8.7 15.41
0.061 7
0.0168 7.9 0.085 16.51 0.0306
Area (mm2)
FOM # (mW/Gbps) 8.7 0.009 0.061
7.705 0.01687 0.085 7.9 0.0306 6.60
FOM # (mW/Gbps) 8.7Measured result;
*: Simulated result; **: 7.705# : FOM = Power
7 (mW)/Data
7.9rate (Gbps). 6.60
*: Simulated result; **: Measured result; #: FOM = Power (mW)/Data rate (Gbps).
4. Conclusions
4. Conclusions
In this paper, a 2.5 Gbps, 10-lane, low-power, LVDS transceiver was presented. In the receiver,
In thiscommon
a pre-stage paper, a mode
2.5 Gbps, 10-lane,
voltage low-power,
shifter LVDS transceiver
was introduced wasthe
to implement presented.
commonInmodethe receiver,
voltage
conversion, and a rail-to-rail comparator embedded with a shaping buffer was utilized to voltage
a pre-stage common mode voltage shifter was introduced to implement the common mode recover
conversion,
the and a rail-to-rail
input signal. Comparedcomparator
with the embedded with of
characteristics a shaping buffer
previous LVDSwasdriver
utilized to recover thea
architectures,
input signal. Compared with the characteristics of previous LVDS driver architectures,
complementary MOS LVDS driver using a CMFB circuit was exploited to provide the required output a
complementary MOS LVDS driver using a CMFB circuit was exploited to provide the
common mode voltage and differential output swing at 1.8 V supply voltage. In addition, a high-speed required
level shifter was designed for voltage domain conversion, and a pre-emphasis driver with PWM
technique was employed to reduce the signal transition time. Further, the proposed LVDS transceiver
was compatible with ANSI/TIA/EIA-644-A standards. The tranceiver is easy to interoperate with
other differential signaling technologies, and can be embedded in other chips as an IP core, which
Electronics 2019, 8, 350 8 of 9

makes it suitable for use in portable electronics. The whole circuit was fabricated with SMIC 28 nm
CMOS technology, with a total chip area of 1.46 mm2 . The measured results show that the proposed
low-power LVDS was able to be properly operated at 2.5 Gbps, with an RMS jitter of 3.65 ps and an
FOM of 6.6 mW/Gbps.

Author Contributions: Conceptualization, X.B.; formal analysis, X.B. and J.Z.; data curation, X.B. and Y.Z.;
writing—original draft preparation, X.B. and S.Z.; writing—review and editing, X.B. and S.Z.; visualization, X.B.
and S.Z.; supervision, J.Z.; project administration, Y.Z.
Funding: This research was funded by National Science and Technology Major Project of China, grant
number 2014ZX0302002.
Acknowledgments: The authors would like to thank the National Science and Technology Major Project of China
for their support.
Conflicts of Interest: The authors declare no conflict of interest.

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