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SeqVHDL

The document explains how to describe sequential circuits in VHDL, focusing on process statements and their execution rules. It covers the behavior of signals and variables, the concurrency of processes, and the use of conditional assignments, including IF and CASE statements. Examples illustrate the concepts, demonstrating how processes execute and how signals are updated based on changes in sensitivity lists.

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walid Qaja
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7 views4 pages

SeqVHDL

The document explains how to describe sequential circuits in VHDL, focusing on process statements and their execution rules. It covers the behavior of signals and variables, the concurrency of processes, and the use of conditional assignments, including IF and CASE statements. Examples illustrate the concepts, demonstrating how processes execute and how signals are updated based on changes in sensitivity lists.

Uploaded by

walid Qaja
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Sequential Circuits in VHDL SeqVHDL

Describing Sequential Circuits in VHDL.

Process Statement. (Rules)

1. Statements within a process repeat executing sequentially until the process is


suspended.
2. A suspended process can resume if a wait condition is satisfied or if a signal that is
on its sensitivity list has changed.
3. Signals cannot be declared inside the process statement. Only the variables or
constants can declared there (and nowhere else).
4. Any assignment to a signal will take place only when the process suspends. Until
such a time all signals will keep their previous values.
5. Only the last assignment before the process suspension is effective.

Example:

process (c,d) is
begin
a <= 2;
b <= a+c;
a <= d+1;
e <= a*2;
end process;

What will be the values if initially a = b = c = d = 1 and d changes to 2;

Signal Resumes Suspends

a 1 2+1
b 1 1+1
c 1 1
d 2 2
e 1 1*2

Example:

process (c,d) is
begin
variable Av, Bv, Ev : integer := 0;
Av := 2;
Bv := Av+C;
Av := Dv+1;
Ev := Av*2;
a <= Av;
b <= Bv;
e <= Ev;
end process;

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Sequential Circuits in VHDL SeqVHDL

The same initial values for signals. Again, change d from 1 to 2.

a b c d e Av Bv Ev
process suspended 1 1 1 1 1 0 0 0
process resumes 1 1 1 2 1 0 0 0
Av := 2 1 1 1 2 1 2 0 0
Bv := Av + c 1 1 1 2 1 2 3 0
Av := d + 1 1 1 1 2 1 3 3 0
Ev := Av*2 1 1 1 2 1 3 3 6
a <= Av 1 1 1 2 1 3 3 6
b <= Bv 1 1 1 2 1 3 3 6
e<= Ev 1 1 1 2 1 3 3 6
process suspends 3 3 1 2 6 3 3 6

This time the terminal values of signals will be a = 3, b= 3 c=1, d= 2, e = 6

Concurrency of Processes.

Behavioural specification of a system is a set of concurrent sequential processes. All


processes within an architecture execute concurrently. When a signal changes then all
processes that have that signal in their sensitivity list resume their individual sequential
executions. These executions are independent of each other. Only signals can be used to
transfer information between processes. Variables are local objects to the process.

Concurrent signal Assignments are simple processes that do not require the use of the
process syntax.

Example:

process ( A, B) is
begin is the same as C < = A and B;
C < = A and B;
end process;

The assignment C < = A and B; executes each time either A or B or both change.
Two assignments represent two independent processes.

C <= A and B;
A < = B or C;

If the B variable changes C and A will be recalculated. If any of the two values has been
changed as a result, another re-calculation takes place. The recalculations are repeated
indefinitely, unless a steady state, in which no new values are produced, is reached.

However, were the two assignments been included in a process structure then they would be
executed sequentially according the rules governing the signal assignment in processes.

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Sequential Circuits in VHDL SeqVHDL

Example:

The two architectures below describe the same functionality:

architecture ar1 of ent1 is architecture ar2 of ent1 is


signal Int1, Int2 : std_logic; begin
begin Int1 <= A or C;
GATE1 : process (A,C) is Int2 < = B or D;
begin Out <= Int1 and Int2;
Int1 <= A or C; end ar2;
end process;
GATE2 : process (B,D) is
begin
Int2 <= B or D;
end process;

GATE3 : process (Int1, Int2) is


begin
Out <=Int1 and Int2;
end process;
end ar1;

Conditional Assignments are short ways of expressing simple processes using the conditional
statement if ..then. For example, a 2-1 multiplexer can be described in two equivalent ways:

process (A, B, S) is Q <= A when S=’1’ else


begin <= B;
if S = ‘1’ then
Q <= A;
else
Q <= b;
end if;
end process;

Use of CASE versus IF statements.

Both these statements can be used inside the process (but not outside).

The CASE statement should be used when running through a set of mutually exclusive
conditions. All conditions have to be accounted for or one has to use the qualifier OTHERS to
cover the possibilities not considered explicitly.

Example:
signal switch : std_logic_vector (3 downto 0);
case switch is
when “0000” =>
statement1;
statement2;
when “0010” =>
statement 3;
when OTHERS
statement4;
end case;

The CASE statement will, in most situations, be synthesised by a multiplexer.

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Sequential Circuits in VHDL SeqVHDL

The IF statement allows a comparison of various, not necessarily mutually exclusive,


conditions. Conditions are checked sequentially so the first IF condition has the highest
priority.
For example, consider the following IF statement that appears in a process:

if a = ‘1’ then
statement1;
statement2;
elseif b = ‘1’ then
statement3;
else
statement4;
end if;

For a = ‘1’ , b = ‘1’ only the statements 1 and 2 will execute. However, for a = ‘0’ , b = ‘1’ the
statement3 will execute. The statement4 will execute only when a = ‘0’ and b=’0’.

The IF statement will, in most situations, be synthesised by a series of comparators; one


comparator for each of the IF.. ELSE construct.

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