SSC15-VI-2

Software Defined Radio (SDR) for Parallel Satellite Reception in Mobile/Deployable

Ground Segments
Mamatha R. Maheshwarappa
Surrey Space Centre, University of Surrey
Guildford, Surrey, GU2 7XH, UK; Phone: +44 (0) 1483 686029
[email protected]

Mark Bowyer
Airbus Defence and Space Ltd, Anchorage Road
Portsmouth, Hampshire, PO3 5PU, UK; Phone: +44 (0) 2392 705733
[email protected]

Christopher P. Bridges
Surrey Space Centre, University of Surrey
Guildford, Surrey, GU2 7XH, UK; Phone: +44 (0) 1483 689137
[email protected]

ABSTRACT
Software Defined Radios (SDRs) have emerged as a viable approach for space communications over the last decade
by delivering low-cost hardware and flexible software solutions. The flexibility introduced by the SDR concept not
only allows the realization of multiple standards on one platform, but also promises to ease the implementation of
one communication standard on differing SDR platforms by waveform porting. This technology would facilitate
implementing reconfigurable nodes for parallel satellite reception in Mobile/Deployable Ground Segments. The
SDR architecture was implemented initially in C/C++ and tested over varied embedded platforms and at different
data rates from 1.2 to 19.2 kbps. Profiling using gprof demonstrated the need to move the up and down sampling
blocks demanding higher computation to Field Programmable Gate Array (FPGA) logic in order to benefit new
architecture optimization and thereby facilitating more than one signal at any given time. The paper includes the
implementation of the Digital Down Converter (DDC) block in VHDL and design tradeoffs that yields insight into
optimal solutions along with effective evaluation of the new candidate architecture.

INTRODUCTION [11, 12]. In this decade, the introduction of Field

The ongoing evolution in constellation/formation of Programmable Gate Array (FPGA)system-on-a-chip
(SoC) and, most recently, RF programmable transceiver
CubeSats along with steadily increasing number of
satellites deployed in Lower Earth Orbit (LEO), SoC can fulfill the early promise.
demands a generic yet reconfigurable multimode This work aims at three specific application areas.
communication platforms [1, 2]. Furthermore, there is Firstly, the ground station that can handle multiple
an ongoing evolution of multiple small satellite
satellite signals at any given time, an example scenario
scenarios such as FLOCK-1 [3], QB50 [4],
is shown in Figure 1. The increasing number of
Autonomous Assembly of a Reconfigurable Space
satellites in Lower-Earth Orbit (LEO) occupying
Telescope (AAReST [5]), Surrey Training Research Amateur Radio Spectrum together with variety of
and Nano-Satellite Demonstrator (STRaND-2) [6] and modulation techniques, data rates and protocols [13]
Edison Demonstration of Smallsat Network (EDSN)
used across the CubeSat community demands the
[7].The objectives of these missions are very ambitious
integration of a multitude communication standards
and driven by new complexities which require multi-
onto a single platform. This is compounded by the
mode operation of wireless transceivers [8]. problem of crowded spectrum [14] which is driving
research on more efficient use of the available spectrum
For over two decades, Software Defined Radio [9, 10]
e.g., by de-confliction or Cognitive Radio (CR)
technology has promised to revolutionize the
techniques. For all such applications, a universal
communication industry by delivering low-cost,
programmable hardware is desirable, which intensified
flexible software solutions for communication protocols

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the interest in Software Defined Radio (SDR) in recent consumption and complexity in integrating previously
years [15]. Such an SDR must be robust in noisy and/or separated building blocks on a single die.
contested spectrum and make maximum use of a priori
information to minimise initial acquisition and This paper focuses on the implementation of one such
detection bandwidths. SDR and the challenges faced during the
implementation. Initially, a baseline architecture uses a
reference signal and then revised to support parallel
reception. Also, a new SDR functionality flowchart is
presented with equations to detail time and
memorydesign requirements favoring the ground
station that supports the transition from single satellite
communications to multi-satellite communications.

SDR ARCHITECTURE – IMPLEMENTATION &

VALIDATION IN C/C++
The architecture consists of a Base-Band (BB) System-
on-Chip (SoC) paired with Radio Frequency (RF) SoC.
The BB SoC contains Field Programmable Gate Array
(FPGA) fabric and ARM dual-core Cortex A9
processor. For initial development, the Avnet Zedboard
containing the Xilinx Zynq 7020 FPGA SoC [18] is
chosen, which provides a low-cost and well supported
back-end for the signal processing functionalities. On
the RF programmable transceiver SoC, initial
evaluation took place using the Lime Micro Myriad RF
containing the LMS6002D RF SoC [19]. More recent
development has taken place using the Analog Devices
Figure 1: Radar View of the Antenna Showing AD-FMCOMMS3-EBZ containing the newer AD9361
Different Satellites in Visibility RF SoC [20]. It is hoped that future developments will
incorporate the latest and most capable Lime Micro
Second, the concept of deploying mobile ground station
SoC, the LMS7002M [21]. The two boards
network for the purposes of increased access time. A
communicate using conventional parallel I/O for high
ground station based on SDR hardware is suitable for
speed sampled data (up to ~123 complex MSPS) and
worldwide distributed systems, as ESA’s Global
Serial Peripheral Interface (SPI) for configuration,
Educational Network for Satellite Operations (GENSO)
control and monitoring.
system [16] and Satellite Networked Open Ground
Station (SatNOGS) [17], where updates containing the Transmitter Implementation
software for communicating with new waveforms could
be shared among different distant stations without the As a first step towards validating the architecture, a
need for hardware upgrades. simple coder modulator/demodulator decoder reference
model for a well-known CubeSat beacon telemetry was
Finally, a candidate embedded design is presented as a implemented. The FUNcube-1 (AO-73) CubeSat [22]
possible enabler of the future SDR for distributed provides a good starting point for our work because its
satellite communication systems. The growth of SDR telemetry beacon is well documented and addressed by
offers small satellites the opportunity to improve the number of Open Source Software (OSS) demodulator
way space missions develop and operate transceivers decoder implementations written in C/C++.
for communication network in space. The ability to
change the operating characteristics of a radio through The particular scheme, from AO-40 heritage [23],
software once deployed to space offers the flexibility to common among several CubeSats [22], is based on
adapt to new science opportunities, recover from BPSK modulation and a robust concatenated code
anomalies within the science payload or communication comprising Viterbi (Rate 1/2) and two Reed Solomon
system, and potentially reduce development cost and (160,128) blocks. Much work here derives from Phil
risk by adapting generic space platforms to meet
Karn’s well-known AO-40 design and implementation
specific mission requirements. However, the flexibility
[KA9Q] [23]. The Analog Devices AD-FMCOMMS3-
and adaptability comes with an expense of power
EBZ has noOS and Linux Operating System (OS) based
device drivers accompanied by application examples.

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For this work, we start with the Zynq ARM Linux OS targeted for Linux, is designed to work offline using
based approach as the application integration and test sample files captured from the FUNcube Pro Dongle
related OSS can be simplified. To this end, Analog [28]. Using IIO, along with fcdec it has been possible to
Devices provides a capable AD9361 Linux device create a soft real time reference decoder called “iio-
driver dependent on Linux industrial I/O (IIO) fcdec”. This was tested for interoperability against
framework [26]. Linux IIO allows user space waveform FUNcube-1 reference waveforms up-sampled, stored
applications to configure/query/sample-stream to and and played back on a Rohde & Schwarz SMBV100
from the AD9361 using familiar UNIX calls VSG oscilloscope [30].
(open/close/read/write/ioctl) and perhaps, and more
preferred, by a user space library called libiio [27]. The
Linux libiio provides a modern high performance
abstraction to all IIO devices including the AD9361.
Using IIO, it has been possible to create a soft real time
reference encoder called iio-fcenc.

Successful interoperability testing of iio-fcenc took

place for different symbol rates such as 1k2, 2k4, 4k8,
9k6 and 19k2. Figure 2 show the signals being received
on a FUNcube Pro+ dongle and spectrum analysis
performed using SDR# [28]. The AD-FMCOMMS3
provides the flexibility to transmit at any desired
frequency within the range of 70 MHz to 6.0 GHz. This
has an advantage over traditional transmitters which Figure 3: Decoded Signal
involved unique hardware for each frequency band and
The transmitted signals were looped back to the
thereby demonstrating the SDR attributes mentioned
receiver port to transmit and receive the signals
earlier. In addition to maximum and minimum tuning
simultaneously. Figure 3 shows the decoded packets
frequencies, the limits imposed by the RF SoC include
from the loopback test. Different symbol rates (1k2,
front-end bandwidth, tuning resolution, sampling rate
2k4, 4k8, 9k6 and 19k2) were achieved by changing the
and resolution. The freedom to adjust centre
interpolation ratio and decimation ratio in iio_fcenc and
frequencies and sample rates under software control
iio_fcdec respectively.
helps compensating thermal drift, clock timing and
Doppler Effects. Implementation and validation of the signals received
from real-time satellite and the transmitter built in-
house along with the results are discussed in [31]. It
was evident that the desktop application can be
implemented on an embedded system which would not
only aid in upgrading the traditional ground stations but
can also be implemented on a small satellite.

Profiling
Profiling can visualize the execution weight of each
block in the compiled C/C++ program.GNU gprof [32]
was used to identify critical regions, determine which
blocks need to be optimized, vectorized and/or moved
to FPGA firmware (HDL) in order to optimise the
implementation to accommodate more than one signal
Figure 2: Signal Received on SDR Sharp at
path on the BB SoC.
Different Data Rates 1k2, 2k4, 4k8, 9k6 and 19k2
(from left to right) The above implementation was run different platforms:
x86 PC and Odroid-XU Lite (Octa - ARM Cortex A15
Receiver Implementation
Quad Core and ARM Cortex A7 Quad Core) and
The chosen OSS starting point to form a “reference stream samples from Zedboard (which is running iiod
implementation” is Alex Csete’sFUNcube Decoder by default) over Ethernet network to compare the
(fcdec) available on github [29]. This C/C++ code base, performance of the blocks on different processors.

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While real time profiling, the packet/frame decoding, handle multiple signals at any given time. Based on
success rates are recorded to later aid results time/memory/functional requirements the signals will
reconciliation. In this approach, the data rate was be routed within the SoC as discussed later in this
increased to (and beyond) the point that CPU starvation paper. As a first step towards validating the revised
sets in. architecture, a simple DDC block was implemented
based on a CIC filter. The reference design includes the
It was evident that the up-sampling and down-sampling core from Analog Devices which fetches the samples
were the most computationally intensive blocks in the from RF core and provides them to Zynq PS for further
transceiver. Detailed explanation of transceiver processing. The DDC block was implemented in
profiling using gprof visualizing the relative and between RF core (AXI_AD9361) and DMA (just
absolute performances, success rates due to CPU before entering the Zynq PS) as seen in Figure 6 in
starvation along with functional diverse behavior such order to prevent the saving of the undesired spectrum.
as linear/quadratic and cubic on dissimilar platforms Other blocks such as modulation/demodulation,
can be found in [33]. frequency/phase correction and packet handling which
are computationally less intensive were retained on
SDR ARCHITECTURE – IMPLEMENTATION & ARM Cortex A9 processors.
VALIDATION IN VHDL
The C/C++ implementation discussed earlier was
Based on the profiling results obtained, the architecture carried out on the reference Linux OS based design
was revised in order to efficiently utilize the FPGA provided by Analog Devices. However, it was required
firmware and take advantage of its flexibility and to understand the reference design and the process of
speed. The FPGA firmware was re-configured to creating a new image with DDC block integrated to the
include Digital Down Converter (DDC) and Digital Up FPGA fabric. This was not a straight forward task as
Converter (DUC) blocks as seen in Figure 4 to perform there are several releases of the reference design, Linux
higher computational tasks. Having multiple OS, Bootloader and the documentation on adding a new
DDC/DUCs would facilitate parallelization required to block and creating a new image is very thin.

Figure 4: Future Pipeline Architecture

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Implementation Steps & Challenges
1. File generated: System.bit; Tool Used: Vivado
The following implementation can be used to create 2014.2.
different files that go on to the SD Card as seen in
Figure 5. The reference HDL was downloaded from
Analog Devices’ repository [34] which has
only the sources, bit/elf files were generated
by running the .tcl scripts. The libraries
required for AD-FMCOMMS2-3 board and
the project were built as per [35]. DDC blocks
(I and Q) based on CIC filters were integrated
with the reference design. This design was
validated, synthesized and implemented to
generate system.bit file.
2. File generated: First Stage Boot Loader
(FSBL.elf); Tool Used: SDK 2014.2.
Figure 5: Files on a SD Card for ZedboardBootup
Once the system.bit was generated, the HDL

My_DDC_I

My_DDC_Q

util_adc_pack

AXI_AD9361

Figure 6: Overall Block Diagram

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 design was exported to SDK to create a new Where N = number of CIC stages; R = rate change; M
application project using Zynq FSBL. = differential delay in the comb stages of the filter. And
the nulls in the magnitude response are at integer
3. The u-boot.elf(bootloader) was provided by multiples of f = 1 / (RM).
Analog Devices[36]. Alternatively, this can be
independently built for the Zedboard. The parameters provide the passband characteristics
over the frequency range from zero to a predetermined
4. File generated: BOOT.BIN; Tool Used:
Bootgen in SDK 2014.2. cutoff frequency fc. This pass band frequency range is
typically the bandwidth of interest occupied by the
Above files were added to the partition list in signal undergoing filtering. Different configurations of
Create Zynq Boot Image dialog to generate clock frequency and number of stages had different
BOOT.BIN file. responses as listed in Table 2. The larger the number of
cascaded stages, the more attenuated the magnitude
5. File generated: uImage and Devicetree Tool response of side lobes become. The reference plot with
Used: Linux Terminal. software DDC implemented on ARM processor is
shown in Figure 7.
This files were generated by cloning the right
version/branch repository as mentioned in
Case 1: Clock frequency: 300 MHz; No. of stages: 3
Table 1 and built on a Linux PCas per [25].
Here the side lobes were dominating and as a result
Table 1: Page Margins for Letter and A4 the decoder failed to identify the valid signal.
Submissions
Case 2: Clock frequency: 250 MHz; No. of stages:5
Repository Version Branch
Though the side lobes were suppressed when
Linux linux 2014_R2 compared to Case 1, they still existed and the decoding
HDL 2014.2 hdl_2014_R2 was not successful.

Case 3: Clock frequency: 250 MHz; No. of stages: 6

6. uEnv.txt contains the base address of all the
above files and it was provided by Analog In this case the side lobes were completely
Devices. suppressed and the signal was decoded successfully.
The response matches the frequency response of the
Debugging original design.

Though the HDL design including the DDC block Increasing N also droops the pass band as seen in the
compiled without any issues, the decoder was not Table 2, thus narrowing the filter bandwidth.
successful in decoding the signal received. In order to
investigate this issue further, the transmitter was looped
back to the receiver. In the software, a buffer was
created to capture the samples after decimation and just
before entering the decoder.

DDC block is based on Cascaded Integrator Comb

(CIC) filter. CIC filter was chosen over FIR (Finite
Impulse Response) as CIC filters are hardware-efficient
for multirate implementations [24] with structures that
use only adders, subtractors and delay elements. CIC
filter has a low-pass response that results from filtering
an input signal with a cascade of N unit-amplitude,
rectangular windows of length R*M. The magnitude
response of CIC filter is given by:

sin(𝜋𝑅𝑀𝑓) 𝑁 Figure 7: FFT Plot - Original Design

𝐻(𝑓) = [ ] (1)
sin(𝜋𝑓)

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 Table 2: CIC Block Configurations

CIC Filter Response Samples Received

Case 1: Clock Frequency: 300 MHz; No. of Stages: 3

Case 2: Clock Frequency: 250 MHz; No. of Stages: 5

Case 3: Clock Frequency: 250 MHz; No. of Stages: 6

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 Table 3:Overhead Analysis of DDC Implementation
Original Design (Software DDC) With DDC Block on FPGA Overhead
Power: Power: Power:
 Total On-Chip Power: 2.2 W  Total On-Chip Power: 2.231 W  Total On-Chip Power: 1.4%
 Dynamic Power : 2.03 W  Dynamic Power : 2.06 W  Dynamic Power : 1.47%
 Device Static : 0.17 W  Device Static : 0.171 W  Device Static : 0.58%

Post Implementation: Post Implementation: Post Implementation:

 Flip Flop : 19%  Flip Flop : 19%  Flip Flop :0
 LUT : 24%  LUT : 24%  LUT :0
 Memory LUT : 4%  Memory LUT : 5%  Memory LUT : 1
 I/O : 61%  I/O : 61%  I/O :0
 BRAM : 6%  BRAM : 6%  BRAM :0
 DSP48 : 31%  DSP48 : 33%  DSP48 :2
 BUFG : 28%  BUFG : 28%  BUFG :0
 MMCM : 50%  MMCM : 50%  MMCM :0

Implementation on FPGA Fabric Implementation on FPGA Fabric

Discussion
REQUIREMENTS OF SDR FOR MULTI-
Table 3 shows the implementation results of DDC on SATELLITE COMMUNICATIONS
the FPGA firmware. Adding a DDC block to the The new SDR functionality flowgraph to handle
original design didn’t increase the power consumption multiple signals is shown in Figure 8.
or the hardware requirements significantly. Total
overhead of on-chip power is 1.4% and the only Step 1: Scan the Spectrum
hardware components changes on the FPGA firmware
Currently, the FFT (8192) in software is used to scan
are DSP48 and Memory LUT.
the spectrum and detect the bin value with maximum
magnitude. This can be implemented on FPGA
This adds confidence to implement the architecture firmware.
with multiple DDC/DUCs. Multiple DDC/DUCs
provide a parallel system to receive multiple signals at Step 2: Detect the Valid Signal
the same time. Implementation of FPGA fabric shows
that nearly half of the hardware is still available. A Lookup Table (LUT) in software will include the
Therefore, along with DDC/DUCs, the next highly centre frequency, Doppler, modulation, data rate and
computationally intensive block which is Fast Fourier packet size. A signal that matches the combination in
Transform (FFT) can also be implemented in hardware the LUT and if the power received in above the
which is now in software. In this way the software can required Eb/No, it signal will be down converted and
accommodate more decoding threads and aid decoded.
parallelization.

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 𝐸𝑏
Power Received ∝
𝑁𝑜

𝑚 𝐶𝑅𝑣 𝐶𝑅𝑟𝑠
𝑇 = 𝑇𝑅 + ( ) + 𝑇𝑤
𝐷𝑎𝑡𝑎 𝑅𝑎𝑡𝑒

m = Modulation Scheme

𝐶𝑅𝑣 𝐶𝑅𝑟𝑠 = Forward Error Correction Codes

𝑇𝑅 , 𝑇𝑤 = Read & Write Time

Figure 8: SDR Functionality Flowgraph

This step also includes the changes in the front end 𝑇 = 𝑇𝑅 + 𝑇𝑇 + 𝑇𝑤 (2)
configurations such as gain to enhance the signal
power.

Step 3: Time and Memory Calculation Where TR, TW = read and write timewhich is given by:
Once the valid signal is detected, time/memory 𝐷𝑎𝑡𝑎
= 𝑐𝑙𝑜𝑐𝑘 𝑓𝑟𝑒𝑞 × × 𝑁𝑜. 𝑜𝑓 𝐼/𝑂
requirements are checked. Time and memory 𝐶𝑙𝑜𝑐𝑘 𝑅𝑎𝑡𝑒
calculations were carried out for the FUNcube-1 signal
𝑇𝑅 , 𝑇𝑤 = 533 𝑀𝐻𝑧 × 8 ∗ 32 = 7.3 𝑝𝑠
as an example.
And
Time Calculations
The active data is 256 bytes, modulation technique is 1 (3)
BPSK with (160, 128) RS Encoder and ½ Viterbi. The 𝑇𝑇 =
𝑆𝑦𝑚𝑏𝑜𝑙 𝑅𝑎𝑡𝑒
total time is given by:

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 𝐷𝑎𝑡𝑎 𝑅𝑎𝑡𝑒 (4) ACKNOWLEDGMENTS
𝑆𝑦𝑚𝑏𝑜𝑙 𝑅𝑎𝑡𝑒 =
𝑚 𝐶𝑅𝑣 𝐶𝑅𝑟𝑠
The authors would like to thank Dr. Brian Yeomans,
Research Fellow, Surrey Space Centre for his valuable
Where m = Modulation Scheme; CRvCRrs = Forward time, discussions and contributions towards the paper.
Error Correction Codes
REFERENCES
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1×( ) satellites for global coverage: Potential and
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“Autonomous Assembly of a Reconfiguarble
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Maheshwarappa 12 29th Annual AIAA/USU

Conference on Small Satellites