Chapter 4
Sequential logic
circuits
Sequential logic circuits
Flip-Flops
Counters
Part 1
Flip-Flops
Flip-Flops
1. Definition and classification
2. SC-FF or RS-FF
3. SC-FF with the synchronous inputs
4. JK-FF with the synchronous inputs
5. D-FF with the synchronous inputs
6. T-FF with the synchronous inputs
7. FF with Clear and Preset
Definition and classification
Flip-Flops:
is a circuit which can memorize data.
has one or more inputs and clock.
has two outputs Q and Q’
can use synchronous inputs.
+ “Clear” Q returns 0.
+ “Preset” set Q to 1.
Definition and classification
Block diagram of a Flip-Flop
Definition and classification
To describe a FF, we can apply one of the following ways:
The Truth Table.
The diagram of state transition.
The characteristic equation
Definition and classification
Classification for FF:
Based on the operation function:
SC-FF, JK-FF, D-FF, T-FF.
Based on the control function:
Synchronous or asynchronous
SC-FF or RS-FF
SC-FF (or RS-FF, R (reset) is equivalent to C (clear)):
has two inputs S and C.
has two outputs: Q and Q’
If the input S (set) is active set Q to logic 1.
If C (clear) is active Q returns logic 0.
SC-FF or RS-FF
Block diagram of SC-FF with high active inputs:
SC-FF or RS-FF
Truth Table:
SC-FF or RS-FF
Pulse diagram:
SC-FF having the synchronous inputs
(SC-Latch/Clocked SC-FF)
SC-Latch:
is a SC-FF synchronized by the input enable EN
EN (enable).
If EN is active: SC-Latch operates as a SC-FF.
If EN is not active: the output Q of SC-Latch
doesn’t change.
SC-Latch
(SC-FF has the input synchronized by voltage level)
Block diagram of SC-Latch:
SC-Latch
(SC-FF has the input synchronized by voltage level)
Truth Table
SC-Latch
(SC-FF has the input synchronized by voltage level)
Pulse diagram
SC-FF having the synchronous inputs
(SC-Latch/Clocked SC-FF)
Clocked SC-FF:
is a SC-FF synchronized by the input CLK (clock).
At the moment when CLK’s voltage level changes from
0 to 1 (excited by the rising edge) or 1 to 0 (excited by
falling edge): Clocked SC-FF operates as SC-FF.
In the other duration: the output Q of Clocked SC-FF
doesn’t change.
Clocked SC
(SC-FF with the synchronous input excited
by the rising edge)
Block diagram of Clocked SC-FF:
Clocked SC
(SC-FF with the synchronous input excited
by the rising edge)
Truth Table
Clocked SC
(SC-FF with the synchronous input excited
by the rising edge)
Pulse diagram:
Clocked SC
(SC-FF with the synchronous input excited
by the falling edge)
Block diagram of Clocked SC-FF:
Clocked SC
(SC-FF with the synchronous input excited
by the falling edge)
Truth table
Clocked SC
(SC-FF with the synchronous input excited
by the falling edge)
Pulse diagram
JK-FF with the synchronous input
(Clocked JK-FF)
Clocked JK-FF:
Has the same operation as Clocked SC-FF (RS-FF).
Except for the case in which both J and K are equal
to 1 The Q’s state is reversed.
JK-FF with the synchronous input
(excited by the rising edge)
Block diagram
JK-FF with the synchronous input
(excited by the rising edge)
Truth table
JK-FF with the synchronous input
(excited by the rising edge)
Pulse diagram
JK-FF with the synchronous input
(excited by the falling edge)
Block diagram:
JK-FF with the synchronous input
(excited by the falling edge)
Truth table
JK-FF with the synchronous input
(excited by the falling edge)
Pulse diagram
D-FF with the synchronous inputs
(D-Latch/Clocked D-FF)
D-Latch:
is a FF synchronized by the input EN.
During the duration which EN is active, the output Q
equals to the input D.
When EN is not active, the output Q of D-Latch
doesn’t change.
Block diagram
D-FF with the synchronous inputs
(synchronized by voltage level)
Truth Table
D-FF with the synchronous inputs
(synchronized by voltage level)
Pulse diagram
D-FF with the synchronous inputs
(D-Latch/Clocked D-FF)
Clocked D-FF:
is a FF synchronized by the input CLK.
At the moment when CLK’s voltage level changes from
0 to 1 (excited by the rising edge) or 1 to 0 (excited by
falling edge): the output Q equals to the input D.
In the other duration: the output Q of Clocked D-FF
doesn’t change.
D-FF with the synchronous inputs
(excited by the rising edge)
Block diagram
D-FF with the synchronous inputs
(excited by the rising edge)
Truth table
D-FF with the synchronous inputs
(excited by the rising edge)
Pulse diagram
D-FF with the synchronous inputs
(excited by the falling edge)
Block diagram
D-FF with the synchronous inputs
(excited by the falling edge)
Truth Table
D-FF with the synchronous inputs
(excited by the falling edge)
Pulse diagram
T-FF with the synchronous input
(Clocked T-FF)
Clocked T-FF:
is a FF synchronized by the input CLK.
At the moment when CLK’s voltage level changes from
0 to 1 (excited by the rising edge) or 1 to 0 (excited by
falling edge), the output Q doesn’t change if the input T=0.
In the other duration: the output Q of Clocked T-FF
doesn’t change.
T-FF with the synchronous input
(excited by the rising edge)
Block diagram
T-FF with the synchronous input
(excited by the rising edge)
Truth Table
T-FF with the synchronous input
(excited by the falling edge)
Block diagram
T-FF with the synchronous input
(excited by the falling edge)
Truth Table
FF with the inputs
Clear (CLR) and Preset (PRE)
To set the beginning state for Q of FF, the inputs Clear
and Preset are added.
FFs with CLR and PRE are:
JK-FF has the input CLR.
D-FF has CLR and PRE.
JK-FF with the input CLR
Block diagram
JK-FF with the input CLR
Truth Table
D-FF with inputs
CLR and PRE
Block diagram
D-FF with inputs
CLR and PRE
Truth Table
Part 2
Counters
Definition for Counter
Counter is a sequential logic circuit with:
The input is Clock used to count.
The output displays the numbers in the specified order.
After K Clock signals, the counter returns the beginning
state.
The counter is designed by FFs and combinational logic
circuit.
Counters
Serial counter (asynchronous counter)
Parallel counter (synchronous counter)
Chapter 5
