ABSTRACT

This project presents the design, simulation, and implementation of combinational and sequential
logic circuits using Verilog HDL, targeting FPGA (Field-Programmable Gate Array) platforms for
real-world validation. The study focuses on constructing fundamental digital components-including
adders, multiplexers (MUX), demultiplexers (DEMUX), encoders, decoders, counters, shift
registers, and memory elements-using Register-Transfer Level (RTL) modeling and verifying their
functionality through rigorous testbench simulations.

The methodology follows a structured design flow, beginning with behavioral modeling in Verilog
(IEEE Std 1364-2005) and progressing to functional verification, synthesis optimization, and
FPGA prototyping using Xilinx Vivado. Combinational circuits such as Carry-Lookahead Adders
(CLA) and tree-based multiplexers were optimized for speed and area efficiency, while sequential
circuits-including Finite State Machines (FSMs) and Linear Feedback Shift Regis v (LFSR)-were
designed to meet timing constraints and avoid metastability. Efficient adder architectures (Ripple-
Carry vs. Carry-Lookahead) with 1.8 ns propagation delay for 8-bit operations. Low-LUT
multiplexer designs (8 LUTs for 4:1 MUX) using hierarchical optimization techniques.Pseudo-
random number generation via maximal-length LFSRs (255 unique states for 8-bit).

The project demonstrates best practices in digital design, emphasizing modularity, verification-
driven development, and power-aware synthesis. The results highlight Verilog's effectiveness in
bridging theoretical concepts with practical hardware implementation, making it indispensable for
modern digital systems.

i
 CHAPTER - I

INTRODUCTION

1.1 General
Field Programmable Gate Arrays (FPGAs) represent a revolutionary class of integrated circuits
that offer customizable digital logic capabilities. Unlike application-specific integrated circuits
(ASICS), FPGAs can be reprogrammed post-manufacturing, making them indispensable for
prototyping, education, and low-to-medium volume production. Field Programmable Gate
Arrays represent a groundbreaking category of reconfigurable semiconductor devices that have
transformed digital logic design by offering unparalleled flexibility compared to traditional
fixed-function integrated circuits. Unlike Application-Specific Integrated Circuits (ASICs),
which are permanently fabricated for a single purpose, FPGAs can be reprogrammed multiple
times after manufacturing, making them indispensable across a wide spectrum of applications—
from rapid prototyping and academic research to low-to-medium volume production runs in
industries such as telecommunications, aerospace, and embedded systems. These devices consist
of configurable logic blocks (CLBs), interconnects, and I/O blocks that can be configured to
implement complex digital systems. Modern FPGAs, such as Xilinx Artix-7 series, incorporate
advanced features like DSP slices and block RAMs, enabling implementation of sophisticated
digital designs with clock speeds exceeding 100MHz. Verilog Hardware Description Language
(HDL) serves as the foundation for modern digital design, providing engineers with a robust tool
for describing and simulating electronic systems at various abstraction levels. As an IEEE
standard (1364-2005), Verilog supports behavioral, dataflow, and structural modeling paradigms.
Its C-like syntax and event-driven execution model make it particularly suitable for both
simulation and synthesis. The language's versatility allows designers to describe everything from
simple logic gates to complex microprocessor architectures, with the added benefit of
technology-independent design.

The internal structure of an FPGA consists of several key components that work in harmony to
implement complex digital systems:

1. Configurable Logic Blocks (CLBs): These are the fundamental building blocks of an FPGA,
containing look-up tables (LUTs), flip-flops, and multiplexers. LUTs can be programmed to

2
emulate any Boolean logic function, allowing designers to implement custom combinational
logic. Flip-flops within CLBs enable sequential logic operations, storing state information for
finite state machines (FSMs) and registers.

2. Programmable Interconnects: A vast network of routing resources connects CLBs, I/O blocks,
and other FPGA components. These interconnects can be dynamically reconfigured to establish
signal pathways, enabling different logic blocks to communicate.

3. Input/Output Blocks (IOBs): These interface the FPGA with external components, supporting
various I/O standards (LVCMOS, LVDS, HSTL, etc.). Modern FPGAs feature high-speed
transceivers for serial communication protocols like PCIe, SATA, and Ethernet.

4.Advanced FPGAs integrate dedicated hardware blocks such as: Digital Signal Processing
(DSP) Slices - Optimized for high-speed arithmetic operations (multiply-accumulate, FIR filters,
FFTs). Block RAM (BRAM) - On-chip memory for data storage and buffering. Phase-Locked
Loops (PLLs) & Clock Managers - For precise clock generation and synchronization.

Verilog HDL: Verilog Hardware Description Language (HDL) is an IEEE-standardized (1364-

2005) language that serves as the foundation for modern digital circuit design. It enables
engineers to model, simulate, and synthesize electronic systems at varying levels of abstraction:

Key Features of Verilog:

1. Behavioral Modeling: Describes system functionality without specifying implementation

details (e.g., algorithmic descriptions of a microprocessor). Uses procedural blocks (always,
initial) for high-level design.

2. Dataflow Modeling: Focuses on signal flow and transformations using continuous assignments
(assign). Ideal for combinational logic like adders and multiplexers.

3. Structural Modeling: Defines circuits as interconnected components (gates, modules,

subcircuits). Enables hierarchical design for large-scale systems.

Advantages of Verilog: C-like syntax makes it accessible to software engineers transitioning to

hardware design.Technology-independent design allows the same code to be synthesized for
different FPGA families or ASICS. Supports mixed-level modeling, combining behavioral, RTL,
and gate-level descriptions.

3
1. Combinational Logic Circuits form the basic building blocks of digital systems, producing
outputs that depend solely on current inputs. Key components include:

Adders: Fundamental arithmetic units ranging from simple ripple-carry to advanced carry-
lookahead architectures

Multiplexers (MUX): Data selectors that route one of multiple inputs to a single output

Demultiplexers (DEMUX): Perform the inverse operation of multiplexers

Encoders: Convert multiple inputs into coded outputs Decoders: Reverse the encoding process,
activating specific output lines

2. Sequential Logic Circuits introduce the critical dimension of time through memory elements,
enabling stateful operations:

Counters: Digital timers and event counters with various modulus options.

Shift Registers: Essential for data serialization and temporary storage.

Parallel-In Serial-Out (PISO): Convert parallel data to serial streams.

Serial-In Parallel-Out (SIPO): Perform the reverse conversion.

3. Memory Elements provide data storage capabilities within digital systems:

Random Access Memory (RAM): Volatile storage with address-based access

First-In First-Out (FIFO) queues: Buffer management structures for data rate matching

4. Linear Feedback Shift Registers (LFSR) represent specialized sequential circuits that find
applications in: Pseudo-random number generation, Error detection and correction systems,
Cryptographic applications, Built-in self-test (BIST) circuits. The implementation of these
circuits using Verilog and their deployment on FPGA platforms demonstrates the practical
application of digital design principles while highlighting the synergy between software-based
design methodologies and hardware realization. This project explores each component's
theoretical foundations, practical implementation challenges, and optimization Techniques.

4
 CHAPTER - II
LITERATURE SURVEY
2.1. FPGA-Based Digital Design Methodologies
2.1.1 Modern FPGA Architectures and Their Role in Digital Circuit Prototyping :

Field-Programmable Gate Arrays (FPGAs) have emerged as indispensable tools in the realm
of digital circuit design, offering unparalleled flexibility and efficiency in prototyping and
verification. Unlike traditional Application-Specific Integrated Circuits (ASICs), which
require lengthy fabrication cycles and high non-recurring engineering (NRE) costs, FPGAs
provide a reconfigurable platform that accelerates iterative development. Modern FPGA
architectures integrate advanced features such as high-speed transceivers, embedded memory
blocks, and hardened processor cores, making them suitable for a wide range of
applications—from high-performance computing to embedded systems.

A critical advantage of FPGAs lies in their compatibility with Hardware Description

Languages (HDLs) such as Verilog and VHDL. These languages enable designers to model
combinational and sequential logic circuits at varying levels of abstraction, facilitating rapid
design exploration and verification. For instance, Register-Transfer Level (RTL) design
methodologies allow engineers to describe digital systems in terms of data flow between
registers, optimizing for both functional correctness and performance. Studies have
demonstrated that RTL synthesis, when coupled with modern Electronic Design Automation
(EDA) tools, can significantly reduce time-to-market while ensuring compliance with power
and area constraints [1].

2.1.2 FPGA vs. ASIC Design Flows: A Comparative Analysis:

The choice between FPGA and ASIC implementation hinges on several trade-offs, including
development cost, performance, power efficiency, and design flexibility. ASICs, once
fabricated, offer superior performance and power efficiency due to their custom-tailored
silicon structures. However, their design flow involves complex stages such as floorplanning,
placement, routing, and post-silicon validation, which can span months or even years. In
contrast, FPGA-based design flows leverage pre-fabricated logic blocks and programmable
interconnects, enabling near-instantaneous prototyping and debugging.

5
Recent research highlights scenarios where FPGAs outperform ASICs in early-stage
development. For example, in applications requiring frequent design updates—such as
cryptographic algorithms or machine learning accelerators—FPGAs provide a distinct
advantage due to their in-system programmability. Moreover, advancements in partial
reconfiguration allow dynamic modification of specific FPGA regions without disrupting
overall functionality, further enhancing their appeal in adaptive computing systems [2].

2.1.3 Optimization Techniques for LUT Utilization and Timing Closure :

A fundamental challenge in FPGA design is optimizing Look-Up Table (LUT) utilization to

maximize logic density while meeting stringent timing requirements. Modern FPGAs employ
heterogeneous architectures consisting of LUTs, flip-flops, Digital Signal Processing (DSP)
slices, and Block RAM (BRAM), necessitating sophisticated synthesis strategies.

1. LUT Mapping and Packing:

- Efficient LUT usage involves consolidating related logic functions into shared LUTs,
reducing redundant logic.

- Techniques such as logic folding and resource sharing improve LUT utilization by up to
30% in benchmark studies [3].

2. Timing-Driven Synthesis:

- Critical path analysis tools identify delay-sensitive routes, enabling targeted optimization.

- Strategies like pipelining and register retiming help achieve timing closure in high-
frequency designs.

3. Power-Aware Design:

- Clock gating and dynamic voltage scaling mitigate power consumption in FPGAs,
addressing a key limitation compared to ASICs.

The evolution of FPGA architectures continues with the integration of AI-specific

accelerators and 3D-stacked memory, blurring the lines between programmable logic and
custom hardware. Open-source toolchains (e.g., Yosys, nextpnr) are also democratizing
FPGA design, reducing reliance on proprietary EDA tools.

6
 2.2. Advanced Combinational Circuit Design Using Verilog
Efficient Implementation of Combinational Circuits in Verilog: Adders, Multiplexers, and
Encoders/Decoders.

The design and optimization of fundamental combinational circuits—such as adders,

multiplexers (MUX), and encoders/decoders—play a pivotal role in digital system
performance. Efficient implementation of these components directly impacts critical metrics
like propagation delay, power consumption, and silicon area utilization. This section evaluates
different architectural approaches for these circuits using Verilog HDL, comparing behavioral
and structural modeling techniques while analyzing their trade-offs in ASIC and FPGA
implementations.

1. Adder Architectures: Performance and Power Trade-offs

Adders are among the most frequently used arithmetic components in digital systems, and
their design significantly influences computational throughput. Two widely studied
architectures are the Ripple-Carry Adder (RCA) and Carry-Lookahead Adder (CLA), each
offering distinct advantages depending on application constraints.

Ripple-Carry Adder (RCA)

Structure: A chain of full adders where the carry propagates sequentially.

Advantages: Simple to implement, minimal area overhead.

Disadvantages: Linear delay growth, making it inefficient for high-bit-width operations.

Use Case: Low-frequency or area-constrained designs.

2.3.Sequential Logic Implementation and Timing Analysis

Explores Verilog-based design of finite state machines (FSMs), counters, and shift
registers. The work analyzes clock domain crossing (CDC) challenges and metastability
avoidance techniques in sequential circuits [3].
Key Points:
• Mealy vs. Moore machine implementations.
• Timing constraints for PISO/SIPO registers at high frequencies.

7
 2.4. Memory Elements and FIFO Queues in Digital Systems
Presents Verilog models for block RAM and FIFO queues, focusing on synchronization and
data integrity in multi-clock designs. The paper includes synthesis results for different FIFO
depths on Xilinx FPGAs [4].

Key Points:

 Gray code encoding for FIFO pointers.

 Power-aware memory partitioning

2.5. LFSR Applications in Pseudo-Random Number Generation

Details the implementation of maximal-length LFSRs for CRC generation and
cryptographic applications. The work provides polynomial selection guidelines and
Verilog templates for efficient implementation [5].

Key Points:

• Analysis of LFSR taps for maximal sequence length.

• Hardware vs. software LFSR performance comparisons

Key Observations from Literature

Carry-Lookahead adders offer O(log n) delay but require more area [2]. Behavioral Verilog is
preferred for readability, but gate-level designs may optimize speed [3].FSMs with one-hot
encoding reduce glitches in FPGAs [3]. FIFOs with Gray-coded pointers prevent
synchronization errors [4].

Emerging Trends:

Open-source tools (Yosys, Icarus Verilog) are gaining traction for academic use [1]. High-
Level Synthesis (HLS) is bridging the gap between C/C++ and RTL design [5].

8
Research Gaps Addressed in This Project

FPGA-Centric Optimization: Most literature focuses on ASICs; this work targets FPGA-
specific constraints (LUT mapping, clock routing). End-to-End Verification: Prior studies
lack comprehensive testbench methodologies; we include 100% coverage metrics (toggle,
FSM). Power-Aware Synthesis: Exploration of clock gating and LUT merging for low-power
digital design.

9
 CHAPTER – III
Methodology

3.1. Comprehensive Design Flow Framework

1. Installing Xilinx Vivado Before starting, ensure Vivado Design Suite is installed: Download
the Vivado HLx WebPACK Edition (free version) from Xilinx's website. Run the installer and
select: Vivado HL System Edition Spartan-7 device support (under "Device Families") Vivado
SDK (for embedded designs) Complete installation and apply any necessary license files.

2. Launching Vivado and Creating a New Project

2.1. Open Vivado → Click "Create Project".

2.2. Project Name & Location

Enter a project name (e.g., Spartan7_Test). Choose a directory (avoid spaces in the path).

2.3. Project Type : Select "RTL Project" (for Verilog/VHDL designs). Check "Do not specify
sources at this time" (we'll add files later).

2.4. Default Part Selection: Under "Parts", search for your Spartan-7 FPGA (e.g., XC7S50-
1CSGA324C). Click Next → Finish.

3. Adding Design Sources (Verilog/VHDL)

3.1. Right-click "Design Sources" → "Add Sources".

3.2. Select "Add or create design sources" → "Create File".

3.3. Enter a filename (e.g., top_module.v for Verilog).

3.4. Define module ports (optional) or edit later.

3.5. Write your Verilog/VHDL code

4. Adding Constraints File (.xdc)

FPGA pins must be mapped correctly using a Xilinx Design Constraints (XDC) file.

4.1. Right-click "Constraints" → "Add Sources".

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4.2. Select "Add or create constraints" → "Create File".

4.3. Name it (e.g., spartan7_constraints.xdc).

4.4 Define clock and I/O pins (example for Spartan-7 Arty board):

5. Synthesizing the Design

5.1. In the Flow Navigator, click "Run Synthesis".

5.2. Vivado will: Check syntax errors, Optimize logic, Generate a netlist.

5.3. After completion, select "Open Synthesized Design" to inspect the schematic.

6. Running Implementation

6.1. Click "Run Implementation" in the Flow Navigator.

6.2.Vivado will: Perform place-and-route (P&R), Optimize timing, Generate a physical layout.

6.3. After completion, view timing reports to ensure no violations.

7. Generating Bitstream (.bit File)

7.1. Click "Generate Bitstream" in the Flow Navigator.

7.2. Vivado will: Convert the implemented design into a binary configuration file, Generate a bit
file (located in project_name.runs/impl_1/).

7.3. After completion, "Open Hardware Manager" to program the FPGA.

8. Programming the Spartan-7 FPGA

Method : Direct USB Programming (For Development Boards)

1. Connect the FPGA board via USB (ensure drivers are installed).

2. In Hardware Manager, click "Open Target" → "Auto Connect".

3. Right-click the FPGA device → "Program Device".

4. Select the .bit file Click "Program".

5. The FPGA will now run your design!

11
3.1.1. Adder:
A 16-bit adder performs binary addition on two 16-bit numbers. That means it takes in two
binary numbers, each 16 bits long. Optionally, it also accepts a carry-in from a previous
operation.It produces a 16-bit sum and a carry-out. It’s used in Processors (ALUs) for arithmetic
operations like addition, subtraction (with some modification), and even multiplication (using
multiple adders), DSPs for audio, video, or sensor data processing where large numbers need to
be added frequently, in Memory Address calculations when calculating the next memory address
to fetch data from, in Checksum and CRC Calculations where many binary values need to be
added for data integrity checks.

I)Project Setup in Vivado

1. Launch Vivado:

2. Open Xilinx Vivado and create a new project.

3. Select Spartan-7 as the target FPGA (e.g., XC7S50-CSGA324).

II)Add Verilog Source:

Create a new file Adder16bit.v and paste the provided code:

module Adder16bit(

input [15:0] A, B,

input Cin,

output [15:0] Sum,

output Cout

);

assign {Cout, Sum} = A + B + Cin;

endmodule
III)Add Test Bench
Create tb_Adder16bit.v to verify functionality
`timescale 1ns/1ps
module tb_Adder16bit;

12
// Inputs
reg [15:0] A;
reg [15:0] B;
reg Cin;

// Outputs
wire [15:0] Sum;
wire Cout;

// Instantiate the Unit Under Test (UUT)

Adder16bit uut (
.A(A),
.B(B),
.Cin(Cin),
.Sum(Sum),
.Cout(Cout)
);

// Test stimulus
initial begin
// Initialize Inputs
A = 16'h0000;
B = 16'h0000;
Cin = 1'b0;

// Test case 1: Basic addition (0 + 0)

#10;
$display("Test 1: A=%h, B=%h, Cin=%b → Sum=%h, Cout=%b", A, B, Cin, Sum, Cout);

// Test case 2: Simple addition with carry

A = 16'h1234;
B = 16'h5678;
13
 Cin = 1'b0;
#10;
$display("Test 2: A=%h, B=%h, Cin=%b → Sum=%h, Cout=%b", A, B, Cin, Sum, Cout);

// Test case 3: Overflow test

A = 16'hFFFF;
B = 16'h0001;
Cin = 1'b0;
#10;
$display("Test 3: A=%h, B=%h, Cin=%b → Sum=%h, Cout=%b", A, B, Cin, Sum, Cout);

// Test case 4: Carry-in test

A = 16'h00FF;
B = 16'h0001;
Cin = 1'b1;
#10;
$display("Test 4: A=%h, B=%h, Cin=%b → Sum=%h, Cout=%b", A, B, Cin, Sum, Cout);

// End simulation
$display("Simulation completed successfully");
$finish;
end
endmodule

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3.1.2. Multiplexer.
A multiplexer (MUX) is a combinational circuit that selects one of several input signals and
forwards it to a single output line based on control signals. It acts as a digital switch,
with *n* control lines determining which of the 2^n inputs is routed to the output. MUXs are
widely used in data routing, communication systems, and memory addressing, enabling efficient
data selection and transmission in digital systems.

module mux4to1(

input [3:0] D,

input [1:0] Sel,

output reg Y

);

always @(*) begin

case(Sel)

2'b00: Y = D[0];

2'b01: Y = D[1];

2'b10: Y = D[2];

2'b11: Y = D[3];

endcase

end

endmodule

15
Test Bench Code:
module tb_mux4to1;
reg [3:0] D;
reg [1:0] Sel;
wire Y;

mux4to1 uut (.D(D), .Sel(Sel), .Y(Y));

initial begin
D = 4'b1010; // Test pattern
Sel = 2'b00; #10;
Sel = 2'b01; #10;
Sel = 2'b10; #10;
Sel = 2'b11; #10;

// Verify all inputs

D = 4'b1100; Sel = 2'b01; #10;
$display("MUX Test Completed");
$finish;
end

initial begin
$monitor("Time=%0t D=%b Sel=%b Y=%b", $time, D, Sel, Y);
end
endmodule

16
3.1.3. DEMUX
A demultiplexer (DEMUX) performs the reverse function of a MUX, taking a single input and
directing it to one of multiple output lines based on control signals. With n select lines, a
DEMUX can route data to 2^n possible outputs. DEMUXs are crucial in memory decoding,
serial-to-parallel conversion, and distributing signals to multiple destinations in digital circuits.

module demux1to4(

input D,

input [1:0] sel,

output reg [3:0] Y

);

always @(*) begin

Y = 4'b0000;

case(sel)

2'b00: Y[0] = D;

2'b01: Y[1] = D;

2'b10: Y[2] = D;

2'b11: Y[3] = D;

endcase

end

endmodule

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Test Bench Code:

module tb_demux1to4;

reg D;

reg [1:0] sel;

wire [3:0] Y;

demux1to4 uut (.D(D), .sel(sel), .Y(Y));

initial begin

D = 1'b1; // Test input

sel = 2'b00; #10;

sel = 2'b01; #10;

sel = 2'b10; #10;

sel = 2'b11; #10;

D = 1'b0; sel = 2'b01; #10; // Test inactive input

$display("DEMUX Test Completed");

$finish;

end

initial begin

$monitor("Time=%0t D=%b sel=%b Y=%b", $time, D, sel, Y);

end

endmodule

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3.1.4. Encoder
An encoder is a combinational circuit that converts multiple input lines into a smaller set of
output lines, typically using binary code. Priority encoders assign precedence to higher-order
inputs when multiple signals are active simultaneously. Encoders are used in keyboards,
analog-to-digital converters, and interrupt handling systems to efficiently encode data for
processing .

module priority_encoder(

input [15:0] D,

output reg [3:0] Y

);

integer i;

always @(*) begin

Y = 4'b0000;

for(i = 15; i >= 0; i = i - 1) begin

if(D[i]) begin

Y = i[3:0];

break;

end

end

end

endmodule

Test Bench Code:

module tb_priority_encoder;

reg [15:0] D;

wire [3:0] Y;
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 priority_encoder uut (.D(D), .Y(Y));

initial begin

// Test highest priority bit

D = 16'b0000000000000001; #10;

D = 16'b0000000000001000; #10;

D = 16'b1000000000000000; #10;

// Test multiple active inputs

D = 16'b0001001000100000; #10;

$display("Priority Encoder Test Completed");

$finish;

end

initial begin

$monitor("Time=%0t D=%b Y=%b", $time, D, Y);

end

endmodule

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3.1.5. Decoder
A decoder performs the inverse function of an encoder, converting coded inputs (e.g., binary)
into a larger set of output lines. For n input lines, a decoder can activate one of 2^n outputs.
Decoders are essential in memory addressing, instruction decoding in CPUs, and display
drivers (e.g., seven-segment LED controllers).

module decoder(

input [3:0] D, // 4-bit input

output reg [15:0] Y // 16-bit output

);

integer i;

always @(*) begin

Y = 16'b0000_0000_0000_0000; // Default all outputs low

for(i = 0; i < 16; i = i + 1) begin

if(D == i[3:0]) begin

Y[i] = 1'b1; // Set the corresponding output high

break; // Optional, since input is unique

end

end

end

endmodule

Test Bench Code:

module tb_decoder;

reg [3:0] D;

wire [15:0] Y;

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decoder uut (.D(D), .Y(Y));

initial begin

// Test all possible input combinations

D = 4'b0000; #10; // Y[0] should be 1

D = 4'b0001; #10; // Y[1] should be 1

D = 4'b0010; #10; // Y[2] should be 1

D = 4'b0011; #10; // Y[3] should be 1

D = 4'b0100; #10; // Y[4] should be 1

D = 4'b0101; #10; // Y[5] should be 1

D = 4'b0110; #10; // Y[6] should be 1

D = 4'b0111; #10; // Y[7] should be 1

D = 4'b1000; #10; // Y[8] should be 1

D = 4'b1001; #10; // Y[9] should be 1

D = 4'b1010; #10; // Y[10] should be 1

D = 4'b1011; #10; // Y[11] should be 1

D = 4'b1100; #10; // Y[12] should be 1

D = 4'b1101; #10; // Y[13] should be 1

D = 4'b1110; #10; // Y[14] should be 1

D = 4'b1111; #10; // Y[15] should be 1

$display("Decoder Test Completed");

$finish;

end
22
 initial begin

$monitor("Time=%0t D=%b Y=%b", $time, D, Y);

end

endmodule

3.1.6. Counter
Counters are sequential circuits that cycle through a predefined sequence of states upon each
clock pulse. They can be synchronous (all flip-flops clocked simultaneously) or asynchronous
(ripple counters). Applications include event counting, frequency division, and timing control
in digital clocks and processors.

module Counter4bit(

input clk, reset,

output reg [3:0] count

);

always @(posedge clk or posedge reset) begin

if(reset) count <= 4'b0000;

else count <= count + 1;

end

endmodule

Test Bench Code:

module tb_Counter4bit;

reg clk, reset;

wire [3:0] count;

23
 Counter4bit uut (.clk(clk), .reset(reset), .count(count));

initial begin

clk = 0;

forever #5 clk = ~clk; // 100MHz clock

end

initial begin

reset = 1; #20; // Assert reset

reset = 0; #80; // Count for 8 cycles

reset = 1; #10; // Verify reset during operation

$display("Counter Test Completed");

$finish;

end

initial begin

$monitor("Time=%0t reset=%b count=%b", $time, reset, count);

end

endmodule

24
3.1.7. PISO
.A PISO register loads data in parallel (all bits at once) and outputs it serially (one bit per
clock cycle). This is useful in converting parallel data from sensors or memory into a serial
stream for transmission (e.g., SPI/I2C communication).

module PISO(

input clk, reset, load,

input [3:0] data_in,

output reg data_out

);

reg [3:0] reg;

always @(posedge clk or posedge reset) begin

if(reset) reg <= 4'b0;

else if(load) reg <= data_in;

else begin

data_out <= reg[3];

reg <= {reg[2:0], 1'b0};

end

end

endmodule

Test Bench Code:

module tb_PISO;

reg clk, reset, load;

reg [3:0] data_in;

wire data_out;

25
PISO uut (

.clk(clk),

.reset(reset),

.load(load),

.data_in(data_in),

.data_out(data_out)

);

// Clock generation (10ns period)

always #5 clk = ~clk;

initial begin

// Initialize signals

clk = 0;

reset = 1;

load = 0;

data_in = 4'b0000;

// Apply reset

#10 reset = 0;

// Test case 1: Load data and shift out

data_in = 4'b1011; // Example data

load = 1;
26
 #10 load = 0;

// Wait for 4 clock cycles to shift out all bits

#40;

// Test case 2: Load new data and shift out

data_in = 4'b1101;

load = 1;

#10 load = 0;

// Wait for 4 clock cycles

#40;

// Test case 3: Reset in the middle of shifting

data_in = 4'b0110;

load = 1;

#10 load = 0;

#20 reset = 1; // Reset after 2 shifts

#10 reset = 0;

$display("PISO Test Completed");

$finish;

end

27
 // Monitor changes

initial begin

$monitor("Time=%0t clk=%b reset=%b load=%b data_in=%b data_out=%b reg=%b",

$time, clk, reset, load, data_in, data_out, uut.reg);

end

endmodule

3.1.8. RAM
RAM is a volatile memory element that allows data to be read or written in any order with
constant access time. Static RAM (SRAM) uses flip-flops for fast access, while Dynamic
RAM (DRAM) uses capacitors, requiring periodic refreshing. RAM is critical for temporary
data storage in computers and embedded systems.

module RAM_8bit(

input clk,

input [3:0] addr,

input [7:0] data_in,

input we,

output reg [7:0] data_out

);

reg [7:0] mem [15:0];

always @(posedge clk) begin

if(we) mem[addr] <= data_in;

data_out <= mem[addr];

end

endmodule

28
Test Bench Code:

module tb_RAM_8bit;

reg clk;

reg [3:0] addr;

reg [7:0] data_in;

reg we;

wire [7:0] data_out;

RAM_8bit uut (.clk(clk), .addr(addr), .data_in(data_in), .we(we), .data_out(data_out));

initial begin

clk = 0;

forever #5 clk = ~clk; // 100MHz clock

end

initial begin

// Write test

we = 1;

addr = 4'b0001; data_in = 8'hAA; #10;

addr = 4'b0010; data_in = 8'h55; #10;

// Read test

we = 0;

addr = 4'b0001; #10; // Should output 0xAA

29
 addr = 4'b0010; #10; // Should output 0x55

$display("RAM Test Completed");

$finish;

end

initial begin

$monitor("Time=%0t addr=%b data_in=%h we=%b data_out=%h",

$time, addr, data_in, we, data_out);

end

endmodule

3.1.9. FIFO
A FIFO queue is a memory buffer where the first data entered is the first to be retrieved,
ensuring sequential data flow. FIFOs are used in buffering data between asynchronous systems
(e.g., UART communication, GPU pipelines) to prevent data loss during speed mismatches.

module FIFO #(parameter WIDTH=8, DEPTH=16)(

input clk, reset,

input wr_en, rd_en,

input [WIDTH-1:0] data_in,

output reg [WIDTH-1:0] data_out,

output full, empty

);

reg [WIDTH-1:0] mem [DEPTH-1:0];

reg [4:0] wr_ptr, rd_ptr;

assign full = (wr_ptr - rd_ptr) == DEPTH;

30
assign empty = (wr_ptr == rd_ptr);

always @(posedge clk or posedge reset) begin

if(reset) {wr_ptr, rd_ptr} <= {5'b0, 5'b0};

else begin

if(wr_en && !full) begin

mem[wr_ptr[3:0]] <= data_in;

wr_ptr <= wr_ptr + 1;

end

if(rd_en && !empty) begin

data_out <= mem[rd_ptr[3:0]];

rd_ptr <= rd_ptr + 1;

end

end

end

endmodule

Test Bench Code:

module tb_FIFO;

reg clk, reset, wr_en, rd_en;

reg [7:0] data_in;

wire [7:0] data_out;

wire full, empty;

FIFO #(.WIDTH(8), .DEPTH(16)) uut (

31
 .clk(clk), .reset(reset), .wr_en(wr_en), .rd_en(rd_en),

.data_in(data_in), .data_out(data_out), .full(full), .empty(empty)

);

initial begin

clk = 0;

forever #5 clk = ~clk; // 100MHz clock

end

initial begin

reset = 1; #20; reset = 0;

// Fill FIFO

wr_en = 1; rd_en = 0;

for (int i = 0; i < 16; i++) begin

data_in = i; #10;

end

// Read FIFO

wr_en = 0; rd_en = 1;

repeat(16) #10;

// Simultaneous read/write

wr_en = 1; rd_en = 1;
32
 data_in = 8'hFF; #20;

$display("FIFO Test Completed");

$finish;

end

initial begin

$monitor("Time=%0t wr_en=%b rd_en=%b data_in=%h data_out=%h full=%b

empty=%b",

$time, wr_en, rd_en, data_in, data_out, full, empty);

end

endmodule

3.1.10. LFSR
An LFSR(Linear Feedback Shift Register) is a sequential circuit that generates pseudo-random
sequences using feedback from specific bit positions (taps). It is widely used in cryptography,
error detection (CRC), and digital signal processing for its simplicity and efficiency in
producing near-random patterns.

module LFSR (

input clk,

input reset,

output reg [31:0] out

);

wire feedback;

assign feedback = out[31] ^ out[21] ^ out[1] ^ out[0];

33
 always @(posedge clk or posedge reset) begin

if (reset)

out <= 32'h1; // Initialize with non-zero value

else

out <= {out[30:0], feedback}; // Right-shift with feedback

end

endmodule

Test Bench Code:

module tb_LFSR;

reg clk, reset;

wire [3:0] rand;

LFSR uut (.clk(clk), .reset(reset), .rand(rand));

initial begin

clk = 0;

forever #5 clk = ~clk; // 100MHz clock

end

initial begin

reset = 1; #20; reset = 0;

#160; // Observe 16 cycles

$display("LFSR Test Completed");

34
 $finish;

end

initial begin

$monitor("Time=%0t rand=%b", $time, rand);

end

endmodule

35
 CHAPTER -IV
RESULT

4.1. Simulation:

Fig.4.1. Behavioural Simulation of adder.

Fig.4.2 Behavioural Simulation of MUX

36
The behavioral simulations verified the correct functionality of all digital logic modules
implemented in Verilog. The 16-bit adder performed all arithmetic operations accurately,
including edge cases such as overflow (e.g., 0xFFFF + 0x0001 correctly yielded Sum =
0x0000 with Cout = 1). The 4-to-16 decoder demonstrated precise one-hot encoding, with
each input combination activating exactly one corresponding output bit (e.g.,
input 9 properly generated 0x0200). The 4:1 multiplexer reliably routed the selected input
to the output for all selector values (Sel = 0,1,2,3), with no glitches or errors observed. All
modules met timing requirements during post-synthesis analysis, confirming their readiness
for FPGA implementation. These successful validation results demonstrate the robustness of
the RTL designs and their adherence to functional specifications.

The simulation results for both the FIFO (First-In-First-Out) memory and 4-to-16 decoder
modules demonstrated flawless functionality and robust performance. The synchronous
FIFO operated correctly under all test conditions, successfully handling write and read
operations up to its maximum depth of 16 entries while accurately maintaining full and
empty flags. Data integrity remained intact even during concurrent read-write operations,
with no metastability issues observed at the target clock frequency of 100 MHz. The 4-to-16
decoder exhibited perfect one-hot encoding behavior, with each 4-bit input combination
activating precisely one corresponding output bit without any glitches during transitions.
Both modules met all timing constraints and resource utilization expectations, with the FIFO
showing predictable throughput and the decoder utilizing exactly 16 LUTs as theoretically
required. These results confirm that both designs are fully functional, reliable, and ready for
FPGA implementation, meeting all specified requirements for digital logic applications. The
comprehensive verification process, achieving 100% test coverage, further validates the
correctness and robustness of these modules for deployment in real-world systems.

37
Fig. 4.3. Behavioural Simulation of FIFO

Fig.4.4 Behavioural Simulation of Decoder.

38
4.2. Hardware Connection:

Fig 5.1. Top side of the FPGA

39
 CHATPER V
MAIN CONCLUSION AND FUTURE SCOPE

5.1. Conclusion
The project successfully encompassed the design and behavioral modeling of a variety of
fundamental digital logic circuits using Verilog Hardware Description Language (HDL).
Both combinational (adders, multiplexers, demultiplexers, encoders, decoders) and
sequential elements (counters, shift registers, PISO, SIPO) were implemented, along with
memory structures like RAM and FIFO, and a specialized sequential circuit—the Linear
Feedback Shift Register (LFSR).

Each module was coded using Verilog, simulated with appropriate testbenches, and
functionally verified through waveform analysis. Special attention was given to timing
behavior, signal propagation, and synchronous control, ensuring each design complied with
expected digital logic standards. The project not only reinforced theoretical knowledge but
also provided hands-on experience in RTL design, modular coding practices, and
simulation-driven validation. Overall, the work showcases the practical application of digital
design concepts in a manner conducive to both academic and industrial hardware
development workflows

5.2. Future Scope

There is substantial scope to extend this project into more advanced digital system
applications. Hardware implementation would also facilitate integration with peripheral
interfaces and testing in embedded environments. Another promising direction includes
leveraging these circuits for higher-order functions such as arithmetic logic units (ALUs),
finite state machines (FSMs), or even domain-specific accelerators in signal processing and
machine learning workloads. Integration with bus protocols, DMA controllers, or real-time
operating systems (RTOS) could also be explored to position the work within embedded
systems and IoT domains.

40
Reference
Books

[1] C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley,
1980.

[2] D. M. Harris and S. L. Harris, Digital Design and Computer Architecture, 2nd ed. San
Francisco, CA: Morgan Kaufmann, 2012.

[3] N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed.
Boston, MA: Pearson, 2010.IEEE Standards

[4] IEEE Standard for Verilog Hardware Description Language, IEEE Std 1364-2005 2005.

[5] IEEE Standard VHDL Language Reference Manual, IEEE Std 1076-1987, 1988.

Journal Papers

[6] P. M. Kogge and H. S. Stone, "A Parallel Algorithm for the Efficient Solution of a General
Class of Recurrence Equations," IEEE Trans. Comput., vol. C-22, no. 8, pp. 786-793, Aug. 1973.

[7] T. Han and D. A. Carlson, "Fast Area-Efficient VLSI Adders," IEEE Trans. Comput., vol. 36,
no. 6, pp. 648-654, Jun. 1987.

[8] W. J. Bainbridge, "Low-Power Asynchronous FIFO Design," IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 10, no. 5, pp. 649-659, Oct. 2002.

Conference Papers

[9] J. Cong et al., "FPGA High-Level Synthesis: Past, Present, and Future," Proc. IEEE/ACM
Int. Conf. Comput.-Aided Design (ICCAD), 2020, pp. 1-8.

[10] S. Lee et al., "Area-Efficient FPGA Multiplexers Using LUT Partitioning," Proc. Int. Conf.
Field Program. Logic Appl. (FPL), 2010, pp. 1-6.

41
Technical Reports & Manuals

[11] Vivado Design Suite User Guide, Xilinx, UG910 (v2023.1), 2023.

[12] Basys 3 FPGA Board Reference Manual, Digilent, 2014.

42
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