TESTING

• Fault models.
• Path sensitizing random test.
• design for testability.
• Built-in self test
• JTAG and Boundary scans.
 Fault models

• Transistor- open or closed.

• Wire – shorted to Vdd or Gnd.
• Unwanted connection between two wires.
 Fault models

 Stuck-at model:
 Some wires(inputs or outputs of gates) being permanently stuck at
logic value 0 or 1.
 wire ‘w’ is stuck-at-0, which is denoted as w/0( To Gnd)
 wire ‘w’ is stuck-at-1, which is denoted as w/1.(To Vdd)
 Fault models

 Single and multiple Faults:

 A circuit can be faulty because it has either a single fault or possibly
many faults.
 Multiple faults is difficult because each fault can occur in many
different ways.
 Set of tests vectors are used to detect vast majority of multiple faults.
 Fault models

 CMOS Circuits :
 The transistors may fail in permanently open or shorted (closed) state.
 Many such failures manifest themselves as stuck-at faults.
 Some faults produce entirely different behavior i.e. a combinational
CMOS circuit starts behaving as a sequential circuit.
 A test set developed using the stuck-at model provide an adequate
coverage of faults in all circuits.
 Complexity of Test Set
 Testing combinational and sequential circuits:
 Combinational circuits can be tested adequately regardless of their
design.

 Sequential circuits present a much greater challenge because the

behavior of a circuit under test is influenced not only by the tests that
are applied to the external inputs but also by the states that the circuit
is in when the tests are applied (Present /Next State).

 It is very difficult to test a sequential circuit designed by a designer

who does not take its testability into account.
 Testing of combinational circuits
 For n-inputs, we require 2n test vectors.
 It is not necessary to apply all 2n valuations as tests for an n-input
circuit.
Eg:

The vectors w1w2w3 = 000 can detect the occurrence of a stuck-at-1 fault on wires a, d, and f .
The vectors w1w2w3 = 001 can detect the occurrence of a stuck-at-1 fault on wires a, b,d and f.
The last test, 111, can detect only one fault, f /0.
 Testing of combinational circuits
 A minimal test set that covers all faults in the circuit can be derived
from the table by inspection.
 The fault b/1 is covered only by 001.
 The fault c/1 iscovered only by 010.
 The faults b/0, c/0, and d/0 are covered only by 011.
 Selecting the tests 001, 010, and 011 covers all faults except a/0.
 This fault can be covered by three different tests & Choosing 100
arbitrarily, a complete test set for the circuit is :
Test set = {001, 010, 011, 100}
 The conclusion is that all possible stuck-at faults in this circuit can be
detected using four tests, rather than the eight tests that would be used
if we simply tried to test the circuit using its complete truth table.
 Path Sensitizing

 The basic principle of the path sensitization method is to choose some

path from the origin of the fault to the circuit output.

 A path is sensitized if the inputs to the gates along the path are
assigned values such that the effect of the fault can be propagated to
the output.
 Path Sensitizing
 Consider a path as an entity that can be tested for several faults using
a single test.
 Activate a path so that the changes in the signal that propagates along
the path have a direct impact on the output signal.
 Eg.
 Path Sensitizing
 Consider path from input w1  f , through three gates, which
consists of wires a, b, c, and f .
 The path is activated by ensuring that other paths in the circuit do not
determine the value of the output f .
 Thus the input w2 must be set to 1 so that the signal at b depends only
on the value at a.
 The input w3 = 0 so that it does not affect the NOR gate, and w4 =1
to not affect the AND gate.
 Then if w1 = 0 the output will be f = 1, whereas w1 = 1 will cause f
= 0.
 Instead of saying that the path from w1 to f is activated, a more
specific term is used in technical literature, which says that the path is
sensitized.
Path Sensitizing
 Detection of a Specific Fault
 In general, the fault on a given wire can be detected by propagating
the effect of the fault to the output, sensitizing an appropriate path.

 This involves assigning values to other inputs of the gates along the
path.

These values must be obtainable by assigning specific values to the

primary inputs, which may not always be possible.

 Following Example illustrates the process.

 FAULT PROPAGATION

 Let the symbol D denote a stuck-at-0 fault in general.

 Let the symbol D-bar denote a stuck-at-1 fault in general.

If D is on an input of an AND (OR) gate and the other inputs are set to
1 (0), then the output of the gate will behave as having D on it.

 But if D is on an input of a NOT, NAND, or NOR gate, then the output

will appear to be stuck-at-1, which is denoted as D-bar.
 Detection of faults.

 We want to propagate the effect of this fault along the path b − h − f .

 This can be done Setting g = 1, propagates the fault to the wire h.
 Then h appears to be stuck-at-1, denoted by D-bar .
 Next the effect is propagated to f by setting k = 1.
 Since the last NAND also inverts the signal, the output becomes equal
to D, which is equivalent to f /0.
 Thus for good circuit, f = 1, but in a faulty circuit it will be 0.
 Assigning the appropriate values to the primary input variables g = 1
and k = 1 is called the consistency check.
 Detection of faults.

 By setting c = 0, both g and k will be forced to 1, which can be

achieved with w3 = w4 = 1.

 Finally, to cause the propagation of the fault D on wire b, it is

necessary to apply a signal that causes b to have the value 1, which
means that either w1 or w2 has to be 0.

 Then the test w1w2w3w4 = 0011 detectsthe fault b/0.

 Test vectors that detects a fault b/0 are {0011,0111,1011}

 Detection of faults( g ⁄ 1 )

 g is stuck-at-1, denoted by D-bar.

Propagate the effect of fault through the path g − h − f by setting b =
1 and k = 1..
 To make b = 1, we set w1 = w2 = 0.
 To make k = 1, we have to make c = 0.
 But it is also necessary to cause the propagation of the D-bar fault on
g by means of a signal that makes g = 0 in the good circuit.
 Thiscan be done only if b = c = 1.
The problem is that at the same time we need c = 0, to make k = 1.
 Therefore, the consistency check fails, and the fault g/1 cannot be
propagated in this way .
 Another Way - Detection of faults( g ⁄ 1 )

 To propagate the effect of the fault along two paths simultaneously.

 Fault is propagated along the paths g −h−f and g − k − f .
 This requires setting b = 1 and c = 1, which also happens to be the
condition needed to cause the propagation as explained above.
 Test vectors that detects a fault g/1 are {0000,0101,1010}
Example
 Testing of Sequential Circuits
 It is much more difficult to test sequential circuits.
 The presence of memory elements allows a sequential circuit to be in
various states.
 And the response of the circuit to externally applied test inputs
depends on the state of the circuit.

Design for Testability

 Design for Testability
 A Synchronous sequential circuit comprises the
combinational circuit that implements :
The output and next-state functions.
 As well as the flip-flops that hold the state information
during a clock cycle.
 Design for Testability
The question is how to apply the test vectors on the present-
state Inputs.
 How to observe the values on the next-state outputs.

A possible approach is to include a two-way multiplexer in

the path of each present-state variable so that the input to the
combinational network can be :

 Either the value of the state variable (obtained from the

output of the corresponding flip-flop)

 Or the value that is a part of the test vector.

 Design for Testability
 A significant drawback of this approach is that :

 The second input of each multiplexer must be directly

accessible through external pins, which requires many pins if
there are many state variables.

An attractive alternative is to provide a connection that

allows shifting the test vector into the circuit one bit at a time,
thus trading off pin requirements for the time it takes to
perform a test

 Several such schemes have been proposed, one of which is

described below is Scan-Path Technique.
Scan-Path Technique
 Scan-Path Technique
 It uses multiplexers on flip-flop inputs to allow the flip-
flops to be used :
 Either independently during normal operation of the
sequential circuit.
 Or as a part of a shift register for testing purposes.

 A 2:1 Mux connects the D input of each flip-flop either to

the corresponding NS- variable or to the serial path that
connects all flip-flops into a shift register.
 The control signal Normal/Scan selects the active input of
the Mux.
 During the normal operation the flip-flop inputs are driven
by the next-state variables, Y1, Y2, and Y3.
 Scan-Path Technique
 The input to the first flip-flop is the externally accessible in
Scan-in.
 The output comes from the last flip-flop, which is provided
on the Scan-out pin.

The scan-path technique involves the following steps:

1. The operation of the flip-flops is tested by scanning into
them a pattern of 0`s and 1`s , for Eg. 01011001, in
consecutive clock cycles, and observing whether the same
pattern is scanned out.
2. The combinational circuit is tested by applying test vectors
on w1w2 ・ ・ ・wn y1 y2 y3 and observing the values
generated on z1 z2 ・ ・ ・ zk Y1 Y2 Y3. This is done as
follows :
 Scan-Path Technique
 The y1 y2 y3 portion of the test vector is scanned into the flip-flops
during three clock cycles, using Normal/Scan = 1.

 The w1 w2 ・ ・ ・wn portion of the test vector is applied as usual

and the normal operation of the sequential circuit is performed for one
clock cycle, by setting Normal/Scan = 0. The outputs z1 z2 ・ ・ ・ zk
are observed. The generated values of Y1 Y2 Y3 are loaded into the flip-
flops at this time.

 The select input is changed to Normal/Scan = 1, and the contents of

the flip-flops are scanned out during the next three clock cycles, which
makes the Y1 Y2 Y3 portion of the test result observable externally. At
the same time, the next test vector can be scanned in to reduce the total
time needed to test the circuit.
 Built-in Self-Test
 Testing capability within the circuit itself so that no external
equipment is needed.
 Such built-in capability would allow the circuit to be self-
testable. This testing capability scheme is called the built-in
self-test (BIST).

The expected responses to the applied tests must be stored

on the chip so that a comparison can be made when the circuit
is being tested.
 Built-in Self-Test
 A practical approach for generating the test vectors on-chip
is to use pseudorandom tests.

 The generator for pseudorandom tests is easily constructed

using a feedback shift-register circuit.

 A four-bit shift register, with the signals from the first and
fourth stages fed back through an XOR gate, generates 15
different patterns during successive clock cycles.

 Observe that the pattern 0000 cannot be used, because the

circuit would be locked in this pattern indefinitely.
 This circuit is known as linear feedback shift registers
(LFSRs).
 Pseudorandom binary sequence generator (PRBSG).

For n-bit shift register

its possible to
generate a sequence
of 2n − 1 patterns.

linear feedback shift registers (LFSRs).

 Single-input compressor circuit (SIC).
 The remaining question is how to check whether the circuit
indeed produces the required response.

 It is not attractive to have to store a large number of

responses to the tests on a chip that also includes the main
circuit.
 A practical solution is to compress the results of the tests
into a single pattern called as signature.

Following Diagram shows a single-input compressor circuit

(SIC), which uses the same feedback connections as the
PRBSG.
 Single-input compressor circuit (SIC).

The input p is the output of a circuit under test.

 After applying a number of test vectors, the resulting values of p drive the SIC.
 And, coupled with the LFSR functionality, produce a four-bit pattern.
 The pattern generated by the SIC is called a signature of the tested circuit for the
given sequence of tests.
The signature represents a single pattern that may be interpreted as a result of all the
applied tests.
 It can be compared against a predetermined pattern to see if the tested circuit is
working properly.
Multiple-input compressor circuit (MIC)
BIST in a Sequential circuit
 BIST in a Sequential circuit
 The test outputs are compressed using the two compressor circuits.

 The patterns on the primary outputs, Z = z1z2 ・ ・ ・ zm, are

compressed using the MIC circuit, and…

Those on the next-state wires Y = Y1Y2 ・ ・ ・Yk , by the SIC

circuit.

 These circuits produce the Z-signature and Y -signature, respectively.

 The testing procedure is the same as earlier except that the comparison
with the test result that a good circuit is supposed to give is done only
once;

At the end of the testing process the two signatures are compared with
the stored patterns.
 BIST in a Sequential circuit
 Instead of storing signature patterns of results as a part of the
designed circuit, it is possible to shift out the contents of MIC and SIC
shift registers onto two output pins and to perform the necessary
comparison with the expected signatures externally.

 Signature testing in this way reduces the testing time significantly.

The effectiveness of the BIST approach depends on the length of the

LFSR generator and compressor circuits.

 Longer shift registers give better results.

 Drawbacks of BIST in a Sequential circuit
 One reason for failing to detect that the CUT may be faulty is that the
pseudorandomly generated tests do not have perfect coverage of all
possible faults.

 Another reason is that a signature generated by compressing the

outputs of a faulty circuit may coincidentally end up being the same as
the signature of the good circuit.

 This can occur because the compression process results in a loss of

some information, such that two distinct output patterns may be
compressed into the same signature. This is known as the aliasing
problem.
 Built-in Logic Block Observer(BILBO)

 BIST is to have internal capability for generation of tests and for

compression of the results.

Instead of using separate circuits for these two functions, it is possible

to design a single circuit that serves both purposes.

 Such structure of a possible circuit, known as the built-in logic block

observer (BILBO)
Built-in Logic Block Observer(BILBO)
 Built-in Logic Block Observer(BILBO)
 The BILBO circuit has four modes of operation, which are controlled
by the mode bits, M1 and M2.
 M1M2 = 11—Normal system mode in which all flip-flops are
independently controlled by the signals on inputs p0 through p3. In this
mode each flip-flop may be used to implement a state variable of a finite
state machine by using p0 to p3 as y0 to y3.
 M1M2 = 00 — Shift-register mode in which the flip-flops are
connected into a shift register. This mode allows test vectors to be
scanned in, and the results of applied tests to be scanned out, if the
control input G/S is equal to 1. If G/S = 0, then the circuit acts as the
PRBS generator.
 M1M2 = 10 — Signature mode in which a series of patterns applied
on inputs p0 through p3 are compressed into a signature available as a
pattern on q0 through q3.
 M1M2 = 01— Reset mode in which all flip-flops are reset to 0.