COURSE DESCRIPTION

FPGA Design for Embedded Systems

Dr. Mohamed M. Eljhani
Department of Computer Engineering
Faculty of Engineering
University of Tripoli, Libya
[email protected]

Welcome to the course on FPGA Design for Embedded Systems, with Hardware
Description Language. In this course over the next 2 weeks of lectures, we will
discussing the various features of the Verilog (verifying logic) hardware
description language, and see that how as a designer you can utilize facilities
and features that are the part of the language to the best possible extent. So,
today we will start with some of basic introductory topics, and let’s start with
those three questions:
Q1. What is an FPGA?
Q2. What are the advantages of using FPGA over other hardware design?
Q3. What are the main differences between FPGAs and ASICs?

1. An FPGA (Field-Programmable Gate Array) is an integrated circuit that can

be configured by a customer or designer after manufacturing. The FPGA
configuration is generally specified using a hardware description language
(HDL), similar to that used for an ASIC (Application Specific Integrated
Circuit). FPGAs contain an array of programmable logic blocks and a
hierarchy of reconfigurable interconnects allowing blocks to be wired
together. Logic blocks can be configured to perform complex combinational
functions or act as simple logic gates like AND and XOR. In most FPGAs,
logic blocks also include memory elements, which may be simple flip-flops or
more complete blocks of memory. Many FPGAs can be reprogrammed to
implement different logic functions, allowing flexible reconfigurable computing
as performed in computer software. Xilinx produced the first commercially
viable FPGA in 1985.
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2. FPGAs have several advantages over other hardware. These include the
ability to develop special-purpose hardware more quickly and cost-effectively
than ASIC designs. FPGAs can perform many data operations
simultaneously, allowing for faster and parallel processing of signals. They
are also very flexible, reusable, and quicker to acquire than microcontrollers.
FPGAs have a quicker time-to-market because they are not pre-designed.
Additionally, FPGAs have their own energy source and do not require a host
computer to run, making them more energy-efficient than CPUs or GPUs.
FPGAs can easily change their functionality, which is not possible with ASICs
or discrete circuits. Another benefit of FPGAs is their parallel processing
ability, or parallel execution of identical operations. In summary, the main
advantage of FPGAs over microprocessors and microcontrollers is their
ability to perform many data operations simultaneously and their flexibility to
be reprogrammed to perform different tasks.

3. ASICs are not reprogrammable and require a new design for each new
application, while FPGAs can be reprogrammed to perform different tasks.
FPGAs are more flexible, reusable, and quicker to acquire than ASICs.
FPGAs have a much higher unit cost compared to ASICs, which means that
if you are looking to use them for high volume mass production, ASICs are
more cost-effective. In summary, ASICs are designed for a specific
application and offer higher performance and power efficiency, while FPGAs
are more flexible and can be reprogrammed to perform different tasks.

Now, let’s start by talking about the main objectives of our course. So, as you
know the name of this course is FPGA Design for Embedded Systems.
Verilog HDL is one of the so-called hardware description languages, it is a
language that used by designers to specify behavior, functionality, or
structure of given hardware; or specified digital circuit, the other language is
called VHDL.
As mentioned above, there are two most popular HDLs today: so, one is
Verilog HDL, the other is VHDL. In this course we will be using the language
Verilog HDL. Now earlier designs that created using HDLs, Verilog HDL or
VHDL are very typical examples of these HDLs.
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Verilog HDL and VHDL are not the only hardware description languages
used in academia and industry, there are other hardware description
languages as well, some of the popular languages are System Verilog, but
here in this course we will be concentrating only on Verilog HDL as more
popular language.

As part of this course, we well learn about the Verilog hardware description
language, its various features, the syntaxes. Specifically, we will be looking
at, two different distinct way of modeling the functionality of a circuit that so-
called behavioral and the structural design styles, and we will explain the
differences. So, specifying a design in either Verilog HDL, or VHDL, the CAD
tools will transform these designs from one level to the next, so the
transformed design is also expressed in similar kind of hardware description
languages.

From the point of view of verifying whether the design is correctly working or
not, (its correct or not), we have to write something called test benches, or
test harness. So, we shall also see how to write such test benches and
evaluate the results of simulations,

We will learn about modeling both combinational and sequential circuits, and
during the course we will learn also what are the good practices and what are
the so-called avoidable practices, that a designer should be aware off.

We will look at some of the case studies. Specifically, at the end of the course
we will design a complete real world engineering project.

In the course we have to rely on computer aided design (EDA) tools, that are
all based on hardware description languages. Just like the high-level
languages like C, C++ or Java, we can specify our hardware, and after
specifying the functionality of the system we use our CAD tools to proceed
the rest of design cycle.
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We will use Intel-Altera software tools:

1. ModelSim for design simulation
2. Quartus II for synthesis and place and routing
As I said, these tools are based on hardware description languages, and
these description languages provide ways to describe and represent designs.

CAD translate or transform designs they will represent at different steps of

transformation; we will see this later. So, here is exactly what I was trying to
mean. CAD tool will transform input which is specified in the hardware
description language and generate an output which will also be a hardware
description language, but the output will contain more detailed information
about the hardware.

The typical steps in the CAD tool transformation as follows:

• Describe your design in behavior level.
• From the behavior, translate or transform your design into a register
level design, register transfer level (RTL), which means from the
behavior, you convert it into a form where you have the registers,
counters, adders, multipliers, multiplexers.
• Once you have done that, the next step will be to convert each of
those functional blocks into gate levels, gates and flip flops.
• Then convert the gate level to the transistor level.
• Then each transistor will be converted to the final layout level.
• So, once you have done this, your design will be ready for fabrication.

So, once you have carried out sufficient analysis and simulation to find out,
that your design is meeting your requirements in terms of power
consumption and delay, and now you can send it for fabrication to become
a system on programmable chip (SoPC).

So, talking about the steps in the design flow, the first was the behavioral
design. As I have said here, we just specify the functionality of the design in
terms of the behavior we do not say, how it is doing it, we just say what we
want. Some examples, in the behavioral style, so we can express a Boolean
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expression function in the form of Boolean expression or in the form of a

truth table.

If it is a sequential circuit, we can express it as a finite state machine: for

example, just as a state transition diagram, or as a state transition table. Or
you can just specify it as a very high level, just like a program written in C or
C++ in a very high level of abstraction by writing a pseudo code just in the
form of an algorithm.

Now, during the design flow the behavioral design has to be transformed
which is called synthesis, that means the design is synthesized to more
detailed specification as a result of which you will be finally getting your
hardware.

Register transfer level components means that the behavior design is

transformed to registers, adders, multipliers, multiplexers, decoders, bus
etc. Netlist is a kind of a graphic where the vertices indicate components
and the edges indicate interconnects. Like you think of a graph where there
are some vertices and there are some edges. So, when we say netlist,
means that we have a number of such blocks, and also specify how these
blocks are interconnected.

Now, these blocks can be at different levels. this block can be very high
level, like adder, it can be a gate, it can be a transistor for example. So, we
could specify a netlist at various different levels of abstraction. So,
whenever we specify a netlist this kind of a design specification is also
referred to as a structural design. And during the synthesis process it will be
systematically transformed from one level to the next.

Now, when we come to the logic design level, here we have a netlist, but
now your blocks are gates and flip flops, or something called standard cells.
Well, a standard cell basically is a pre designed circuit module like gates, and
flip flops, or small circuit like a multiplexer, whose layout is already given to
you. So, we have these standard cells already present in a library, so your
design can pick up one of those standard cells and put them in your layout
directly. In that way you create your layout and this standard cell library
contains the most commonly used small functional modules in a highly
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optimized layout form. And in this type of logic design, various logic
optimization techniques are used to minimize your design, to create a so-
called cost-effective design.

Now, as we said earlier that during this process there can be some
conflicting requirements, like minimizing number of gates, minimizing
delays, that means, number of gate levels, minimizing powers, which
means number of signal transitions that are taking place at the outputs of
the gates. These requirements are often conflicting, so if you want to
minimize one of these, possibly the others can increase.

If you do not want to go for a chip to be fabricated, as an alternative you can

also go for something called a field programmable gate array, or FPGA,
where from the design you can directly program the device which can be
done in field in your laboratory, and as a result you can have much greater
flexibility. But as compared to a chip you are fabricating, here the speed will
be less. This is the tradeoff you have to realize.

Another step in the design flow, is simulation that is very important step for
verification. In this course we will extensively using simulation to check and
verify the Verilog HDL modules that we will be writing. We will also be
informing you how to do this simulation and what is the different simulation
techniques so that you can do or carry out the simulation yourself.
Simulation can be carried out at various levels of specification, behavioral
level, gate level, and circuit level.

So, now we come to the end of the description of the course. In this
description we have basically give you an overview about what are the
things we are expected to cover in this course and some basic concepts of
FPGA design flow. Because understanding the design flow will allow you to
have a better understanding of how you can create a great design using
Verilog HDL, so that the final hardware that will be generated in the process
can be reliable and useful.