Lecture 10:

Circuit
Families
 Outline
❑ Pseudo-nMOS Logic
❑ Dynamic Logic
❑ Pass Transistor Logic

10: Circuit Families CMOS VLSI Design 4th Ed. 2

 Introduction
❑ What makes a circuit fast?
– I = C dV/dt -> tpd  (C/I) V
– low capacitance
– high current
4
– small swing B
A 4
❑ Logical effort is proportional to C/I Y
1 1
❑ pMOS are the enemy!
– High capacitance for a given current
❑ Can we take the pMOS capacitance off the input?
❑ Various circuit families try to do this…

10: Circuit Families CMOS VLSI Design 4th Ed. 3

 Pseudo-nMOS
❑ In the old days, nMOS processes had no pMOS
– Instead, use pull-up transistor that is always ON
❑ In CMOS, use a pMOS that is always ON
– Ratio issue
– Make pMOS about ¼ effective strength of
pulldown network 1.8

1.5
load
P/2 1.2
P = 24
Ids Vout 0.9

Vout 0.6
P = 14
16/2 0.3
P=4
Vin
0
0 0.3 0.6 0.9 1.2 1.5 1.8
Vin

10: Circuit Families CMOS VLSI Design 4th Ed. 4

 Pseudo-nMOS
❑ Pull-up transistor must be much weaker than pull-
down transistor.
❑ Reduces logical effort because inputs must only
drive the nMOS transistors.
❑ However, nMOS current reduced by contention with
pull-up transistor.
❑ Unequal rising and falling efforts short power
dissipation when output is low.

10: Circuit Families CMOS VLSI Design 4th Ed. 5

 Pseudo-nMOS Gates
❑ Design for unit current on output to compare
with unit inverter. Y
❑ pMOS fights nMOS inputs
f

Inverter NAND2 NOR2

gu = gu = gu =
gd = g = gd =
gavg = Y gd = gavg =
avg
A
Y pu = pu = Y pu =
A pd = B pd = A B pd =
pavg = pavg = pavg =

10: Circuit Families CMOS VLSI Design 4th Ed. 6

 Pseudo-nMOS Gates
❑ Design for unit current on output to compare
with unit inverter. Y
❑ pMOS fights nMOS inputs
f

Inverter NAND2 NOR2

gu = 4/3 gu = 8/3 gu = 4/3

gd = 4/9 2/3 g = 8/9 gd = 4/9
gavg = 8/9 Y gd = 16/9 gavg = 8/9
2/3 avg 2/3
A 8/3
Y pu = 6/3 pu = 10/3 Y pu = 10/3
A 4/3 pd = 6/9 B 8/3 pd = 10/9 A 4/3 B 4/3 pd = 10/9
pavg = 12/9 pavg = 20/9 pavg = 20/9

10: Circuit Families CMOS VLSI Design 4th Ed. 7

 Pseudo-nMOS Design
❑ Ex: Design a K-input AND gate using pseudo-
nMOS. Estimate the delay driving a fanout of H
Pseudo-nMOS
In1 1
Y
H
Ink 1

4 2 H 8k + 13
+
3 9

10: Circuit Families CMOS VLSI Design 4th Ed. 8

 Pseudo-nMOS Design
❑ Ex: Design a k-input AND gate using pseudo-nMOS.
Estimate the delay driving a fanout of H
Pseudo-nMOS
❑ G = 1 * 8/9 = 8/9 In1 1
Y
❑ F = GBH = 8H/9 H
Ink 1
❑ P = 1 + (4+8k)/9 = (8k+13)/9
❑ N=2
4 2 H 8k + 13
❑ D = NF + P = 3 + 9
1/N

10: Circuit Families CMOS VLSI Design 4th Ed. 9

 Pseudo-nMOS Power
❑ Pseudo-nMOS draws power whenever Y = 0
– Called static power P = IDDVDD
– A few mA / gate * 1M gates would be a problem
– Explains why nMOS went extinct
❑ Use pseudo-nMOS sparingly for wide NORs
❑ Turn off pMOS when not in use

en
Y
A B C

10: Circuit Families CMOS VLSI Design 4th Ed. 10

 Dynamic Logic
❑ Dynamic gates uses a clocked pMOS pullup
❑ Two modes: precharge and evaluate

2 2/3  1
A Y Y Y
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic

 Precharge Evaluate Precharge

10: Circuit Families CMOS VLSI Design 4th Ed. 11

 The Foot
❑ What if pulldown network is ON during precharge?
❑ Use series evaluation transistor to prevent fight.

 
precharge transistor
 Y Y
Y inputs inputs
A f f
foot

footed unfooted

10: Circuit Families CMOS VLSI Design 4th Ed. 12

 Logical Effort
Inverter NAND2 NOR2

 1
Y
 1  1
A 2
unfooted Y Y
A 1 B 2 A 1 B 1
gd = 1/3 gd = 2/3 gd = 1/3
pd = 2/3 pd = 3/3 pd = 3/3

 1
Y
 1  1
A 3
Y Y
footed A 2 B 3 A 2 B 2
gd = 2/3 gd = 3/3 gd = 2/3
2 pd = 3/3 3 pd = 4/3 2 pd = 5/3

10: Circuit Families CMOS VLSI Design 4th Ed. 13

 Monotonicity
❑ Dynamic gates require monotonically rising inputs
during evaluation

– 0 -> 0
A
– 0 -> 1
– 1 -> 1
violates monotonicity
– But not 1 -> 0 during evaluation
A

 Precharge Evaluate Precharge

Output should rise but does not

10: Circuit Families CMOS VLSI Design 4th Ed. 14

 Monotonicity Woes
❑ But dynamic gates produce
monotonically falling
outputs during evaluation
❑ Illegal for one dynamic gate
to drive another!

A=1

  Precharge Evaluate Precharge

Y
X
A
X
X monotonically falls during evaluation
Y
Y should rise but cannot

10: Circuit Families CMOS VLSI Design 4th Ed. 15

 Domino Gates
❑ Follow dynamic stage with inverting static CMOS gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs
 Precharge Evaluate Precharge

domino AND
W

W X Y Z X
A
Y
B C

Z

dynamic static
 
NAND inverter  
A W X A X
H Y =
B H Z B Z
C C

10: Circuit Families CMOS VLSI Design 4th Ed. 16

 Domino Optimizations
❑ Each domino gate triggers next one, like a string of
dominos toppling over.
❑ Gates evaluate sequentially but precharge in parallel.
❑ Thus evaluation is more critical than precharge.
❑ HI-skewed static stages can perform logic


S0 S1 S2 S3
D0 D1 D2 D3
Y
H


S4 S5 S6 S7
D4 D5 D6 D7

10: Circuit Families CMOS VLSI Design 4th Ed. 17

 Dual-Rail Domino
❑ Domino only performs noninverting functions:
– AND, OR but not NAND, NOR, or XOR
❑ Dual-rail domino solves this problem
– Takes true and complementary inputs
– Produces true and complementary outputs

sig_h sig_l Meaning

Y_l  Y_h
0 0 Precharged
inputs
0 1 ‘0’ f f

1 0 ‘1’ 

1 1 invalid

10: Circuit Families CMOS VLSI Design 4th Ed. 18

 Example: AND/NAND
❑ Given A_h, A_l, B_h, B_l
❑ Compute Y_h = AB, Y_l = AB
❑ Pulldown networks are conduction complements

Y_l  Y_h
= A*B A_h = A*B
A_l B_l B_h

10: Circuit Families CMOS VLSI Design 4th Ed. 19

 Example: XOR/XNOR
❑ Sometimes possible to share transistors

Y_l  Y_h
= A xnor B A_h A_l A_l A_h = A xor B
B_l B_h

10: Circuit Families CMOS VLSI Design 4th Ed. 20

 Leakage
❑ Dynamic node floats high during evaluation
– Transistors are leaky (IOFF  0)
– Dynamic value will leak away over time
– Formerly miliseconds, now nanoseconds
❑ Use keeper to hold dynamic node
– Must be weak enough not to fight evaluation
weak keeper
 1 k
X
H Y
A 2
2

10: Circuit Families CMOS VLSI Design 4th Ed. 21

 Charge Sharing
❑ Dynamic gates suffer from charge sharing



Y A
A x CY
Y
B=0 Cx Charge sharing noise

CY
Vx = VY = VDD
C x + CY

10: Circuit Families CMOS VLSI Design 4th Ed. 22

 Secondary Precharge
❑ Solution: add secondary precharge transistors
– Typically need to precharge every other node
❑ Big load capacitance CY helps as well

secondary
 precharge
Y transistor
A x
B

10: Circuit Families CMOS VLSI Design 4th Ed. 23

 Noise Sensitivity
❑ Dynamic gates are very sensitive to noise
– Inputs: VIH  Vtn
– Outputs: floating output susceptible noise
❑ Noise sources
– Capacitive crosstalk
– Charge sharing
– Power supply noise
– Feedthrough noise
– And more!

10: Circuit Families CMOS VLSI Design 4th Ed. 24

 Power
❑ Domino gates have high activity factors
– Output evaluates and precharges
• If output probability = 0.5,  = 0.5
– Output rises and falls on half the cycles
– Clocked transistors have  = 1
❑ Leads to very high-power consumption

10: Circuit Families CMOS VLSI Design 4th Ed. 25

 Domino Summary
❑ Domino logic is attractive for high-speed circuits
– 1.3 – 2x faster than static CMOS
– But many challenges:
• Monotonicity, leakage, charge sharing, noise.
❑ Widely used in high-performance microprocessors in
1990s when speed was king.
❑ Largely displaced by static CMOS now that power is
the limiter
❑ Still used in memories for area efficiency

10: Circuit Families CMOS VLSI Design 4th Ed. 26

 Pass Transistor Circuits
❑ Use pass transistors like switches to do logic
❑ Inputs drive diffusion terminals as well as gates

❑ CMOS + Transmission Gates:

– 2-input multiplexer
– Gates should be restoring
S S

A A

S Y S Y

B B

S S

10: Circuit Families CMOS VLSI Design 4th Ed. 27

 LEAP
❑ LEAn integration with Pass transistors
❑ Get rid of pMOS transistors
– Use weak pMOS feedback to pull fully high
– Ratio constraint

S
A
S L Y
B

10: Circuit Families CMOS VLSI Design 4th Ed. 28

 CPL
❑ Complementary Pass-transistor Logic
– Dual-rail form of pass transistor logic
– Avoids need for ratioed feedback
– Optional cross-coupling for rail-to-rail swing

S
A
S L Y
B
S
A
S L Y
B

10: Circuit Families CMOS VLSI Design 4th Ed. 29

 Pass Transistor Summary
❑ Researchers investigated pass transistor logic for
general purpose applications in the 1990’s:
– Benefits over static CMOS were small or negative.
– No longer generally used.
❑ However, pass transistors still have a niche in special
circuits such as memories where they offer small
size, and the threshold drops can be managed.

10: Circuit Families CMOS VLSI Design 4th Ed. 30