1.

esign of basic combinational and sequential (Flip-flops)

circuits using HDL. Simulate it using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA

Program:
VHDL code for D flip-flop:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity D_FLIPFLOP_SOURCE is

Port ( D, CLK, RST : in STD_LOGIC;

Q, Qb : out STD_LOGIC);

end D_FLIPFLOP_SOURCE;

architecture Behavioral of D_FLIPFLOP_SOURCE is

begin

process (D, CLK, RST)

begin

if (RST = '1') then

Q <= '0';

elsif (rising_edge(CLK)) then ---this is for data flip-flop, for delay flip-flop use negative edge

Q <= D;

Qb <= not D;

end if;

end process;

end Behavioral;

Test bench for D flip-flop:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DFF_tb is

end entity;

architecture tb of DFF_tb is

component D_FLIPFLOP_SOURCE is

Port ( D, CLK, RST : in STD_LOGIC;

Q, Qb : out STD_LOGIC);

end component ;

signal D, CLK, RST, Q, Qb : STD_LOGIC;

begin

uut: D_FLIPFLOP_SOURCE port map(

D => D,

CLK => CLK,

RST => RST,

Q => Q,

Qb => Qb);

Clock : process

begin

CLK <= '0';

wait for 10 ns;

CLK <= '1';

wait for 10 ns;

end process;

stim : process

begin

RST <= '0';

D <= '0';

wait for 40 ns;

D <= '1';

wait for 40 ns;

end process;

end tb;
Truth table for D flip flop:

2. Design an Adder ; Multiplier (Min 8 Bit) using HDL. Simulate

it using Xilinx/Altera Software and implement by Xilinx/Altera
FPGA

Adder:
Program:
library ieee;
use ieee.std_logic_1164.all;

entity FA_8bit is
port(x,y : in std_logic_vector(7 downto 0);
cin : in std_logic;
sum : out std_logic_vector(7 downto 0);
co : out std_logic);
end FA_8bit;

architecture FA_arch of FA_8bit is

signal cary : std_logic_vector(6 downto 0);

component full_adder is
port (p,q,r:in std_logic; sm,cr: out std_logic);
end component;
begin
a0:full_adder port map (x(0),y(0),cin,sum(0),cary(0));
a1:full_adder port map (x(1),y(1),cary(0),sum(1),cary(1));
a2:full_adder port map (x(2),y(2),cary(1),sum(2),cary(2));
a3:full_adder port map (x(3),y(3),cary(2),sum(3),cary(3));
a4:full_adder port map (x(4),y(4),cary(3),sum(4),cary(4));
a5:full_adder port map (x(5),y(5),cary(4),sum(5),cary(5));
a6:full_adder port map (x(6),y(6),cary(5),sum(6),cary(6));
a7:full_adder port map (x(7),y(7),cary(6),sum(7),co);
end FA_arch;
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port (p,q,r:in std_logic; sm,cr: out std_logic);
end full_adder;

architecture FA_arc of full_adder is

begin
sm <= p xor q xor r;
cr <= (p and q) or (q and r) or (r and p);
end FA_arc;

Test bench for 8-bit adder:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity tb_FA_8bit is

end tb_FA_8bit;

architecture behavior of tb_FA_8bit is

component FA_8bit is

port(

x : in std_logic_vector(7 downto 0);

y : in std_logic_vector(7 downto 0);

cin : in std_logic;

sum : out std_logic_vector(7 downto 0);

co : out std_logic

);

end component;

-- Testbench signals

signal x_tb, y_tb : std_logic_vector(7 downto 0);

signal cin_tb : std_logic;

signal sum_tb : std_logic_vector(7 downto 0);

signal co_tb : std_logic;

begin

uut: FA_8bit port map (

x => x_tb,
 y => y_tb,

cin => cin_tb,

sum => sum_tb,

co => co_tb

);

-- Stimulus process

stim_proc: process

begin

-- Test case 1: 5 + 10

x_tb <= "00000101"; -- 5

y_tb <= "00001010"; -- 10

cin_tb <= '0';

wait for 20 ns;

-- Test case 2: 255 + 1

x_tb <= "11111111"; -- 255

y_tb <= "00000001"; -- 1

cin_tb <= '0';

wait for 20 ns;

-- Test case 3: 128 + 128 with carry in

x_tb <= "10000000"; -- 128

y_tb <= "10000000"; -- 128

cin_tb <= '1';

wait for 20 ns;

-- Test case 4: 0 + 0 with carry in

x_tb <= "00000000";

y_tb <= "00000000";

cin_tb <= '1';

wait for 20 ns;

-- Stop simulation

wait;

end process;
end behavior;

Multiplier(2bit):
Program:
library ieee;

use ieee.std_logic_1164.all;

entity AND2 is

port(

A,B: in BIT;

x : out BIT);

end AND2;

architecture behavioral of AND2 is

begin

x <= A and B;

end behavioral;

entity half_adder is

port (a, b : in BIT;

sum, carry : out BIT

);

end half_adder;

architecture arch of half_adder is

begin

sum <= a xor b;

carry <= a and b;

end arch;

entity multiply_struct is

port (A, B : in bit_vector(1 downto 0);

P : buffer bit_vector(3 downto 0)

);

end multiply_struct;

architecture structural of multiply_struct is

component AND2

port(

A,B: in BIT;

X : out BIT);

end component;

component half_adder

port (A, B : in BIT;

sum, carry : out BIT);

end component;

signal S1,S2,S3,S4:BIT;

begin

A1: AND2 port map(A(0),B(0),P(0));

A2: AND2 port map(A(1),B(0),S1);

A3: AND2 port map(A(0),B(1),S2);

A4: AND2 port map(A(1),B(1),S3);

H1: half_adder port map(S1,S2,P(1),S4);

H2: half_adder port map(S4,S3,P(2),P(3));

end architecture;

Test bench for 2 bit multiplier:

library ieee;

use ieee.std_logic_1164.all;
entity multiply_behav_tb is

end multiply_behav_tb;

architecture tb of multiply_behav_tb is

component multiply_behav is

port (A, B : in bit_vector(1 downto 0);

P : out bit_vector(3 downto 0)

);

end component;

signal A, B : bit_vector(1 downto 0);

signal P : bit_vector(3 downto 0);

begin

UUT : multiply_behav port map (

A => A,

B => B,

P => P);

Force:process

constant period: time := 20 ns;

begin

A <= "00";

B <= "00";

wait for period;

A <= "00";

B <= "01";

wait for period;

A <= "00";

B <= "10";

wait for period;

A <= "00";

B <= "11";

wait for period;

A <= "01";
B <= "00";

wait for period;

A <= "01";

B <= "01";

wait for period;

A <= "01";

B <= "10";

wait for period;

A <= "01";

B <= "11";

wait for period;

A <= "10";

B <= "00";

wait for period;

A <= "10";

B <= "01";

wait for period;

A <= "10";

B <= "10";

wait for period;

A <= "10";

B <= "11";

wait for period;

A <= "11";

B <= "00";

wait for period;

A <= "11";

B <= "01";

wait for period;

A <= "11";
B <= "10";

wait for period;

A <= "11";

B <= "11";

wait for period;

wait;

end process;

end tb;

3. Design and implement Universal Shift Register using HDL.

Simulate it using Xilinx/Altera Software

Program:
4 bit universal shift register:
library ieee;
use ieee.std_logic_1164.all;

entity uni_shift is

port (clock, clear, sl_in, sr_in : in bit;

mode : in bit_vector ( 1 downto 0 );

data : in bit_vector ( 3 downto 0 );

q : inout bit_vector (3 downto 0 ));

end uni_shift;

architecture behav of uni_shift is

begin

process (clock, clear)

begin -- Asynchronous, active-low Clear input:

if clear = '0' then

q <= "0000" ; -- Rising edge-triggered D flip-flops:

elsif clock'event and clock = '1' then

case mode is

when "00" => null; -- "Do Nothing" mode: retain current flip-flop outputs

when "01" => q <= (q srl 1) or (sr_in & "000") ; -- Shift Right Serial Input

when "10" => q <= (q sll 1) or ("000" & sl_in) ; -- Shift Left Serial Input

when "11" => q <= data ; -- Parallel (Broadside) Load

end case;

end if;

end process;

end behav;

Test-bench:
library ieee;

use ieee.std_logic_1164.all;

entity tb_uni_shift is

end tb_uni_shift;

architecture behavior of tb_uni_shift is

 -- Component declaration

component uni_shift

port (

clock, clear : in bit;

sl_in, sr_in : in bit;

mode : in bit_vector(1 downto 0);

data : in bit_vector(3 downto 0);

q : inout bit_vector(3 downto 0)

);

end component;

-- Signals for testbench

signal clock_tb : bit := '0';

signal clear_tb : bit := '1';

signal sl_in_tb, sr_in_tb : bit := '0';

signal mode_tb : bit_vector(1 downto 0) := "00";

signal data_tb : bit_vector(3 downto 0) := "0000";

signal q_tb : bit_vector(3 downto 0) := "0000";

begin

-- Instantiate Unit Under Test

uut: uni_shift port map (

clock => clock_tb,

clear => clear_tb,

sl_in => sl_in_tb,

sr_in => sr_in_tb,

mode => mode_tb,

data => data_tb,

q => q_tb

);

-- Clock generation: 20 ns period

clk_process : process

begin
 while now < 200 ns loop

clock_tb <= '0';

wait for 10 ns;

clock_tb <= '1';

wait for 10 ns;

end loop;

wait;

end process;

-- Stimulus process

stim_proc: process

begin

-- Clear the register

clear_tb <= '0';

wait for 20 ns;

clear_tb <= '1';

-- Parallel load 1010

data_tb <= "1010";

mode_tb <= "11"; -- Parallel load

wait for 20 ns;

-- Hold

mode_tb <= "00";

wait for 20 ns;

-- Shift right, insert '1' into MSB

mode_tb <= "01";

sr_in_tb <= '1';

wait for 20 ns;

-- Shift left, insert '0' into LSB

mode_tb <= "10";

sl_in_tb <= '0';

wait for 20 ns;

-- Hold again
 mode_tb <= "00";

wait;

end process;

end behavior;

4. Design Memories using HDL. Simulate it using Xilinx/Altera

Software and implement by Xilinx/Altera FPGA

Program:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

USE ieee.numeric_std.ALL;

-- A 128x8 single-port RAM in VHDL

entity Single_port_RAM_VHDL is

port(

RAM_ADDR: in std_logic_vector(6 downto 0); -- Address to write/read RAM

RAM_DATA_IN: in std_logic_vector(7 downto 0); -- Data to write into RAM

RAM_WR: in std_logic; -- Write enable

RAM_CLOCK: in std_logic; -- clock input for RAM

RAM_DATA_OUT: out std_logic_vector(7 downto 0) -- Data output of RAM

);

end Single_port_RAM_VHDL;

architecture Behavioral of Single_port_RAM_VHDL is

type RAM_ARRAY is array (0 to 127 ) of std_logic_vector (7 downto 0);

signal RAM: RAM_ARRAY :=(

x"55",x"66",x"77",x"67",-- 0x00:

x"99",x"00",x"00",x"11",-- 0x04:

x"00",x"00",x"00",x"00",-- 0x08:

x"00",x"00",x"00",x"00",-- 0x0C:

x"00",x"00",x"00",x"00",-- 0x10:

x"00",x"00",x"00",x"00",-- 0x14:

x"00",x"00",x"00",x"00",-- 0x18:
 x"00",x"00",x"00",x"00",-- 0x1C:

x"00",x"00",x"00",x"00",-- 0x20:

x"00",x"00",x"00",x"00",-- 0x24:

x"00",x"00",x"00",x"00",-- 0x28:

x"00",x"00",x"00",x"00",-- 0x2C:

x"00",x"00",x"00",x"00",-- 0x30:

x"00",x"00",x"00",x"00",-- 0x34:

x"00",x"00",x"00",x"00",-- 0x38:

x"00",x"00",x"00",x"00",-- 0x3C:

x"00",x"00",x"00",x"00",-- 0x40:

x"00",x"00",x"00",x"00",-- 0x44:

x"00",x"00",x"00",x"00",-- 0x48:

x"00",x"00",x"00",x"00",-- 0x4C:

x"00",x"00",x"00",x"00",-- 0x50:

x"00",x"00",x"00",x"00",-- 0x54:

x"00",x"00",x"00",x"00",-- 0x58:

x"00",x"00",x"00",x"00",-- 0x5C:

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00",

x"00",x"00",x"00",x"00"

);

begin

process(RAM_CLOCK)

begin

if(rising_edge(RAM_CLOCK)) then

if(RAM_WR='1') then -- when write enable = 1,

RAM(to_integer(unsigned(RAM_ADDR))) <= RAM_DATA_IN;

end if;

end if;

end process;

RAM_DATA_OUT <= RAM(to_integer(unsigned(RAM_ADDR)));

end Behavioral;

Test-Bench :
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.ALL;

ENTITY tb_RAM_VHDL IS

END tb_RAM_VHDL;

ARCHITECTURE behavior OF tb_RAM_VHDL IS

COMPONENT Single_port_RAM_VHDL

PORT(

RAM_ADDR : IN std_logic_vector(6 downto 0);

RAM_DATA_IN : IN std_logic_vector(7 downto 0);

RAM_WR : IN std_logic;

RAM_CLOCK : IN std_logic;

RAM_DATA_OUT : OUT std_logic_vector(7 downto 0)

);

END COMPONENT;

signal RAM_ADDR : std_logic_vector(6 downto 0) := (others => '0');

signal RAM_DATA_IN : std_logic_vector(7 downto 0) := (others => '0');

signal RAM_WR : std_logic := '0';

signal RAM_CLOCK : std_logic := '0';

signal RAM_DATA_OUT : std_logic_vector(7 downto 0);

constant RAM_CLOCK_period : time := 10 ns;

BEGIN

uut: Single_port_RAM_VHDL PORT MAP (

RAM_ADDR => RAM_ADDR,

RAM_DATA_IN => RAM_DATA_IN,

RAM_WR => RAM_WR,

RAM_CLOCK => RAM_CLOCK,

RAM_DATA_OUT => RAM_DATA_OUT

);

RAM_CLOCK_process :process

begin

RAM_CLOCK <= '0';

wait for RAM_CLOCK_period/2;

RAM_CLOCK <= '1';

wait for RAM_CLOCK_period/2;

end process;

stim_proc: process

begin

RAM_WR <= '0';

RAM_ADDR <= "0000000";

RAM_DATA_IN <= x"FF";

wait for 100 ns;

for i in 0 to 5 loop

RAM_ADDR <= RAM_ADDR + "0000001";

wait for RAM_CLOCK_period*5;

end loop;

RAM_ADDR <= "0000000";

RAM_WR <= '1';

wait for 100 ns;

for i in 0 to 5 loop

RAM_ADDR <= RAM_ADDR + "0000001";

RAM_DATA_IN <= RAM_DATA_IN-x"01";

wait for RAM_CLOCK_period*5;

end loop;

RAM_WR <= '0';

wait;

end process;

END;

5. Design Finite State Machine (Moore/Mealy) using HDL.

Simulate it using Xilinx/Altera Software and implement by
Xilinx/Altera FPGA

Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity moore is
Port ( clk : in STD_LOGIC;
din : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end moore;
architecture Behavioral of moore is
type state is (st0, st1, st2, st3);
signal present_state, next_state : state;
begin
synchronous_process: process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
present_state <= st0;
else
present_state <= next_state;
end if;
end if;
end process;
output_decoder : process(present_state, din)
begin
next_state <= st0; case (present_state) is when st0 =>
if (din = '1') then
next_state <= st1;
else
next_state <= st0; end if; when st1 =>
if (din = '1') then
next_state <= st1;
else
next_state <= st2; end if; when st2 =>
if (din = '1') then
next_state <= st3;
else
next_state <= st0; end if; when st3 =>
if (din = '1') then
next_state <= st1;
else
next_state <= st2; end if; when others =>
next_state <= st0; end case; end process;
next_state_decoder : process(present_state) begin case (present_state) is when st0 =>
dout <= '0'; when st1 =>
dout <= '0'; when st2 =>
dout <= '0'; when st3 =>
dout <= '1'; when others =>
dout <= '0';
end case;
end process;
Test-bench for Sequence detector (101) using mealy state machine:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mealy is
Port ( clk : in STD_LOGIC;
din : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end mealy;
architecture Behavioral of mealy is
type state is (st0, st1, st2, st3);
signal present_state, next_state : state;
begin
syncronous_process : process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
present_state <= st0;
else
present_state <= next_state;
end if;
end if;
end process;
next_state_and_output_decoder : process(present_state, din)
begin
dout <= '0'; case (present_state) is when st0 =>
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st0;
dout <= '0'; end if; when St1 =>
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st2;
dout <= '0'; end if; when St2 =>
if (din = '1') then
next_state <= st1;
dout <= '1';
else
next_state <= st0;
dout <= '0'; end if; when others =>
next_state <= st0;
dout <= '0';
end case;
end process;
end Behavioral;

6. Design 3-bit synchronous up/down counter using HDL. Simulate it

using Xilinx/Altera Software and implement by Xilinx/Altera FPGA

Program(up-counter):

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SOURCE is

Port ( CLK,RST : in STD_LOGIC;

COUNT : inout STD_LOGIC_VECTOR (3 downto 0));

end SOURCE;

architecture Behavioral of SOURCE is

begin

process (CLK,RST)

begin

if (RST = '1')then

COUNT <= "0000";

elsif(rising_edge(CLK))then
COUNT <= COUNT+1;

end if;

end process;

end Behavioral;

Test-bench (up-counter):
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sync_upcounter_tb is

end entity;

architecture tb of sync_upcounter_tb is

component SOURCE is

Port ( CLK,RST : in STD_LOGIC;

COUNT : inout STD_LOGIC_VECTOR (3 downto 0));

end component;

signal CLK,RST : STD_LOGIC := '1';

signal COUNT : STD_LOGIC_VECTOR(3 downto 0);

begin

uut: SOURCE port map(

CLK => CLK,

RST => RST,

COUNT => COUNT);

clock: process

begin

RST <= '0';

CLK <= '0';

wait for 20 ns;

CLK <= '1';

wait for 20 ns;

end process;

end tb;

program(down-count):
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity down_count is

Port ( clk,rst : in STD_LOGIC;

count : out STD_LOGIC_VECTOR (3 downto 0));

end down_count;

architecture Behavioral of down_count is

signal temp:std_logic_vector(3 downto 0);

begin

process(clk,rst)

begin

if(rst='1')then

temp<="1111";

elsif(rising_edge(clk))then

temp<=temp-1;

end if;

end process;

Test-Bench(down-count):
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sync_downcounter_tb is

end entity;
architecture tb of sync_downcounter_tb is

component down_count is

Port ( clk,rst : in STD_LOGIC;

count : out STD_LOGIC_VECTOR (3 downto 0));

end component;

signal clk, rst : STD_LOGIC := '1';

signal count : STD_LOGIC_VECTOR(3 downto 0);

begin

uut: down_count port map(

clk => clk,

rst => rst,

count => count);

clock: process

begin

rst <= '0';

clk <= '0';

wait for 20 ns;

clk <= '1';

wait for 20 ns;

end process;

end tb;

7. Design 4-bit Asynchronous up/down counter using HDL. Simulate it

using Xilinx/Altera Software and implement by Xilinx/Altera FPGA

Program for up/down counter :

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity up_down_counter is

port (

clk : in std_logic;

reset : in std_logic;

up_down : in std_logic;

count : out std_logic_vector(3 downto 0)

);

end up_down_counter;

architecture behavioral of up_down_counter is

signal counter : unsigned(3 downto 0) := (others => '0');

begin

process(clk, reset)

begin

if reset = '1' then

counter <= (others => '0');

elsif rising_edge(clk) then

if up_down = '1' then

counter <= counter + 1;

else

counter <= counter - 1;

end if;

end if;

end process;

count <= std_logic_vector(counter);

end behavioral;

Test-Bench:
library ieee;
use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity tb_up_down_counter is

end tb_up_down_counter;

architecture test of tb_up_down_counter is

signal clk : std_logic := '0';

signal reset : std_logic := '0';

signal up_down : std_logic := '1';

signal count : std_logic_vector(3 downto 0);

component up_down_counter

port (

clk : in std_logic;

reset : in std_logic;

up_down : in std_logic;

count : out std_logic_vector(3 downto 0)

);

end component;

begin

uut: up_down_counter

port map (

clk => clk,

reset => reset,

up_down => up_down,

count => count

);

-- Clock generation (10 ns period)

clk_process : process

begin

while now < 200 ns loop

clk <= '0';

 wait for 5 ns;

clk <= '1';

wait for 5 ns;

end loop;

wait;

end process;

-- Stimulus

stim_proc: process

begin

-- Reset counter

reset <= '1';

wait for 10 ns;

reset <= '0';

-- Count up for 5 cycles

up_down <= '1';

wait for 50 ns;

-- Count down for 5 cycles

up_down <= '0';

wait for 50 ns;

-- Hold simulation

wait;

end process;

end test;