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Automata Theory and Formal
Languages
Express Learning Series
This page is intentionally left blank.
Automata Theory and Formal
Languages
Express Learning Series

Shyamalendu Kandar

Assistant Professor
Computer Science and Engineering
Haldia Institute of Technology, Haldia
and
Course Co-ordinator
HIT Center M.Tech- IT(CWE)
Jadavpur University
Copyright © 2012 Dorling Kindersley (India) Pvt. Ltd.
Licensees of Pearson Education in South Asia

No part of this eBook may be used or reproduced in any manner whatsoever without the publisher’s prior
written consent.

This eBook may or may not include all assets that were part of the print version. The publisher reserves
the right to remove any material present in this eBook at any time.

ISBN 9788131760772
eISBN 9789332510319

Head Office: A-8(A), Sector 62, Knowledge Boulevard, 7th Floor, NOIDA 201 309, India
Registered Office: 11 Local Shopping Centre, Panchsheel Park, New Delhi 110 017, India
 Dedication
To my parents,

Arun Kumar Kandar and Hirabati Kandar,

who have shown me the light of the universe and light of knowledge
&
My GURU in the field of technical education
Professor C. T. Bhunia
who is an inspiration in every step of my life
 About the Author

Shyamalendu Kandar is Assistant Professor of Computer Science and Engineering at the Haldia Insti-
tute of Technology, Haldia, West Bengal. He has passed B.Tech. in Computer Science from Vidyasagar
University in 2004 and M.Tech. in Information Technology (Courseware Engineering) from Jadavpur
University in 2006. His research interest is mainly in multimedia communication, image processing,
and automata theory. He has published a number of research papers in international journals and pre-
sented papers in international conferences.
Contents

About the Author VI

Foreword XI
Preface XIII
Acknowledgements XV

1. Finite State Machine 1

1.1 Basics of Automata 1
1.2 Finite State Machine 2
1.3 State Equivalence and Minimization of Machine 18
1.4 Incompletely Specified Machine and Minimal Machine 23
1.5 Merger Graph and Compatibility Graph 26
1.6 Finite Memory and Definite Memory Machine 38
1.7 Information Lossless Machine and Inverse Machine 52
1.8 Inverse Machine 60
What We Have Learned So Far 63
Solved Problems 64
Multiple Choice Questions 92
Exercises 93
Fill in the Blanks 98

2. Language and Grammar 100

2.1 Basic Terminology and Definitions 100
2.2 Grammar and Language 101
2.3 Chomsky Hierarchy 102
2.4 Examples 104
2.5 Context-sensitive Grammar 112
What We Have Learned So Far 113
Solved Problems 113
Multiple Choice Questions 114
Exercises 115
Fill in the Blanks 116
VIII Contents

3. Finite Automata 118

3.1 Basics About Finite Automata 118
3.2 Transitional System 121
3.3 Deterministic Finite Automata and Non-Deterministic
Finite Automata 123
3.4 NFA with Null Move 128
3.5 Dead State 133
3.6 Finite Automata with Output 134
3.7 Conversion of Moore To Mealy Machine by Tabular Format 138
3.8 Conversion of Mealy to Moore Machine by Tabular Format 140
3.9 Conversion of Moore to Mealy Machine by Transitional Format 144
3.10 Conversion of Mealy to Moore Machine by Transitional Format 147
3.11 Minimization of Finite Automata 151
3.12 Myhill-Nerode Theorem 155
What We Have Learned So Far 161
Solved Problems 162
Multiple Choice Questions 176
Exercises 177
Fill in the Blanks 180

4. Regular Expression 182

4.1 Basics of Regular Expression 182
4.2 Arden Theorem 186
4.3 Construction of Finite Automata Equivalent
to a Regular Expression 191
4.4 NFA With Є Move and Conversion to DFA
By Є – Closure Method 196
4.5 Equivalence of Two Finite Automata and Two
Regular Expressions 202
4.6 Construction of Regular Grammar from
a Regular Expression 205
4.7 Pumping Lemma and its Application 208
4.8 Closure Properties of Regular Set 214
What We Have Learned So Far 218
Solved Problems 218
Multiple Choice Questions 227
Exercises 228
Fill in the Blanks 230
 Contents IX

5. Context Free Grammar 232

5.1 Context Free Grammar: Definition and Examples 232
5.2 Derivation and Parse Tree 235
5.3 Ambiguity 239
5.4 Left Recursion and Left Factoring 243
5.5 Simplification of CFG 246
5.6 Normal Form 254
5.7 Constructing FA from Regular Grammar 262
5.8 Closure Properties of CFL 264
5.9 Pumping Lemma for CFL 265
5.10 Ogden’s Lemma for CFL 269
5.11 Decision Algorithms 269
What We Have Learned So Far 271
Solved Problems 272
Multiple Choice Questions 285
Exercises 286
Fill in the Blanks 288

6. Pushdown Automata 291

6.1 Basics of Pushdown Automata 291
6.2 Acceptance by a PDA 293
6.3 Examples 294
6.4 Deterministic PDA and Non-Deterministic PDA 308
6.5 Pushdown Automata from Context Free Grammar 311
6.6 Graphical Notation for PDA 316
What We Have Learned So Far 317
Solved Problems 318
Multiple Choice Questions 328
Exercises 329
Fill in the Blanks 330
7. Turing Machine 331
7.1 Basic of Turing Machine 331
7.2 Examples 333
7.3 Transitional Representation of Turing Machine 346
What We Have Learned So Far 347
Solved Problems 348
Multiple Choice Questions 352
Exercises 353
Fill in the Blanks 353
References 355
Index 357
This page is intentionally left blank.
 Foreword

The worth of a book is to be measured by what you can carry away from it.—James Bryce

In the history of science and technology, if any branch has ever changed the prospective face of the
world, it is nothing else but Computer Science and Engineering known as CSE microscopically in this
gradually becoming short and nano society(!) The subject of automata theory is an important compo-
nent of CSE, among others. It is said that it is “the study of abstract machine and the problems which
they are able to solve.” Thus, it is by right a primary and core part of CSE.

Many books on automata theory are available in the market and all these books have obvious attrac-
tions as well as drawbacks. Any attempt to author a book with authority to please everyone is next to
impossible. Even any academic exercise to attain the defined objectives and decisive targets deserves
commendation and encouragement. Thus, so I think the current book authored by Shyamalendu Kandar
is a definite scholastic exercise that I am sure will fulfill the aspirations of undergraduate students of
CSE and those of related interdisciplinary subjects. The book is written in easily understandable and
simple language and contains a large number of solved problems, MCQs and exercises.

I would like to congratulate Shyamalendu for this bold academic productivity. Shyamalendu feels
that he is a student of mine and, therefore, as a teacher I feel proud of him. I wish him ever growing
success in the days to come!

Last but not the least, I am a firm believer that “Good teachers are costly, but bad teachers cost more.”
Shyamalendu proves this by his present academic work that he belongs to the family of good teachers
who are costly by their own right and choice.

Good friends, good books and a sleepy conscience: this is the ideal life.—Mark Twain

Prof. Chandan Tilak Bhunia, SMIEEE

Director, BITM, Bolpur, West Bengal, India
and
Senior Associate, ICTP, Italy
 Foreword

Computer Science and Engineering is considered as a modern field of engineering education. It is

an emerging field of technical education and the theory of computation is a core subject of computer
science.
This book by Shyamalendu Kandar is written in a simple language, easily understood by undergradu-
ate students. It contains a large number of figures and many solved problems, exercises and multiple
choice questions with each chapter to help students in understanding and learning the subject. The main
feature of this book is that it is written in an interactive way. When a student goes through the book he
is in a classroom and a teacher is taking his/her class related to the subject matter. Difficult sections of
the subject are also explained lucidly in this book.
I congratulate Shyamalendu for writing this book. Shyamalendu is a student of mine and now working
as a lecturer in Computer Science Department of my institute. I am proud of him and wish him the best
of success!

Prof. M.M. Bag

Director, Haldia Institute of Technology
Haldia, West Bengal
 Preface

An engineer must ask ‘why’ not ‘how’. The Bachelor of Computer Science and Engineering is not only
about learning some application software and some programming languages but also about learning
how a programming language works, how a program is compiled and how input is converted to out-
put from the machine hardware level. The theoretical part of Computer Science includes Complexity
Analysis, Compiler Construction, verifying correctness of circuits and protocols etc. Automata Theory
is one of the core courses in the curriculum of Bachelor of Technology of Computer Science or Informa-
tion Technology under any university. It is said that Automata Theory is “the study of abstract machine
and the problems which they are able to solve”. This book is a part of series named Express Learning
Series which has a number of books designed as quick reference.
Students have to study the two parts subject in Automata Theory and Theory of Computation. Au-
tomata Theory contains Switching Theory, Machine Construction, Machine Checking and Minimiza-
tion whereas the Theory of Computation includes different types of languages and grammars according
to Chomsky Hierarchy. During my teaching career, I have felt that students need a complete book
containing both the sections, a large number of solved problems, multiple choice questions and useful
exercise to practice. This book is written to fullfill this requirement of students. It is written in simple
language keeping in mind the level of undergraduate students . The theory part is described with suitable
examples and useful diagrams. Solved problems are included to explain the theory. At the end of each
chapter a number of multiple choice questions related to the topic are which will help students preparing
themselves for competitive examinations like GATE, NET. The book contains 7 chapters.
Chapter 1 deals with finite state machine, machine construction, machine minimization which are the
main parts of automata theory. Chapter 2 describes different types of languages and grammar accord-
ing to the classification by Chomsky. This chapter is the root part of theory of computation. Chapter 3
deals with introduction of finite automata, deterministic and non-deterministic finite automata, mealy
machine, Moore machine and minimization of finite automata. Chapter 4 describes regular expressions
Arden’s Theorem, Pumping Lemma for Regular Expression. Chapter 5 deals with context free gram-
mar, simplification of context free grammar, different normal form. Chapter 6 deals with push down
automata, construction of push down automata directly from context free grammar. Chapter 7 describes
the Turing Machine.
I will appreciate suggestions for further improvement of the book. My mail address is shyamalen-
[email protected].
My dream in writing this book will be successful if the students are benefited from this book.

SHYAMALENDU KANDAR
This page is intentionally left blank.
 Acknowledgements

My journey of writing started with a personal pain that has now manifested itself in the form of this
book. For this, I wish to express thanks to my friend Madhumita in the words of Rabindranath Tagore,
‘your hurt is the touch of you and a gift to my life’. I am also indebted to Professor C. T. Bhunia for
inspiring me to write this book. When he left our institute on 3 November 2008, it was the saddest day
of my life. He was always engaged in creative work despite his busy schedule and he is my guru in the
field of technical education. This work is a small token of respect for the great man.

I want to express my gratitude to the Director of Haldia Institute of Technology, Professor M. M. Bag,
and my colleagues especially Subhankar Joarder, Arindam Giri, Ramkrishna Das. I am also thankful
to Milan Bera, Mrityunjay Maity, Tanuka Sinha and Bapida who are an integral part of the department.
I wish to express my heartfelt gratitude to Munmun Sarkar for constantly encouraging me during the
course of my writing. She regularly enquired about the progress of the book. I’m thankful to my friend
Sabyasachi Samantha, who is a lecturer in information technology, for providing necessary information
and support. Thanks are also due to my student Dipankar Dutta who helped me in selecting and solving
the problems. I am grateful to Pradeep Banerjee who helped me realise my dream of publishing a book.

Finally, my parents Arun Kumar Kandar and Hirabati Kandar deserve special mention for their con-
stant encouragement and support during the preparation of this book.

SHYAMALENDU KANDAR
This page is intentionally left blank.
 1
Finite State Machine

1.1 BASICS OF AUTOMATA

Q. What do you mean by formal language and automata theory (FLAT)?
Ans. Automata have some typical pronounceable symmetry with Automatic. In a computer all pro-
cesses appear to be done automatically. A given input is being processed in the CPU and an output is
generated. We are not concerned about the internal operation in the CPU. We are only concerned about
the given input and the received output. However, in reality the input is converted to ‘0’ and ‘1’ and
assigned to the process for which the input was given. It then performs some internal operation in its
electronics circuit and generates output in ‘0’ and ‘1’ format. The output generated in ‘0’ and ‘1’ format is
converted to user understandable format and we get the output. From the discussion it is clear that CPU
performs machine operations internally. In Automata we shall learn about how to design such machines.
The name of the subject is formal language and automata theory (FLAT). We have got a basic idea
about Automata theory. Now what is Formal language? Let discuss what language is. Language is a
communication medium through which two persons communicate. For each nation there is some lan-
guage to communicate like Hindi, English, Bengali, etc. Similarly for communicating with a computer
the user needs some language called programming language. C, C++, Java are some examples of pro-
gramming language. The characteristics of these types of languages are similar to English language and
easily understandable by user. However, computer does not understand English in statements. It only
understands binary numbers. Hence, they have a compiler that checks the syntax and acts as a converter
from English statement to binary numbers and vice versa. However, to design the compiler some logic is
needed. The logic can be designed by use of mathematics. For each language there is a grammar, which
is a constructor for any language. Similarly the languages that are used for computer programming rely
on grammar to construct them. These rules and grammar and the process to convert such grammar and
languages to machine format are the main objectives of this subject.
Q. Why FLAT is sometimes called “Theory of Computer Science”?
Ans. This subject is called “Theory of Computation” because it includes rules for constructing a
computer language and converts into machine format; i.e. the theory of computer science. Basically
formal language and automata theory and theory of computation are different names for a single subject
that covers all the aspects of the theoretical part of Computer Science.
2 Automata Theory and Formal Languages

1.2 FINITE STATE MACHINE

Q. Define synchronous and asynchronous circuit.
Ans. Synchronization is usually achieved by some timing device, e.g. clock. A clock produces
equally spaced pulses. These pulses are fed into a circuit in such a way that various operations of the
circuit take place with the arrival of appropriate clock pulses. Generally the circuits, whose operations
are controlled by clock pulses, are called Synchronous circuit.
The operation of asynchronous circuit does not depend on clock pulses. The operations in asynchro-
nous circuit are controlled by a number of completion and initialization signals. Here completion of one
operation is the initialization of the execution of next consecutive operation.
Q. Define combinational circuits and sequential circuits. In this respect describe the block
diagram of synchronous sequential circuit.
Ans. The circuits where the output depends only on the present input, i.e. output is the function of
only present input are called combinational circuits.
O/P ⫽ Func.(Present I/P).
The circuits where the output depends on the external input and the stored information at that time,
i.e., output is the function of external input and present stored information are called sequential circuits.
O/P ⫽ Func.(External I/P and present stored information).
Block diagram

Clk
I1 I1
…

Ip Combinational Iq
logic

y1 Y1

y2 Y2
…

yk Yk

Memory Devices

A synchronous sequential machine has finite number of inputs. If a machine has n number of input
variables, the input set consists of 2n distinct inputs called input alphabet I.
In the diagram the input alphabet is I={I1, I2, ……,Ip}.
 Finite State Machine 3

The number of outputs of a synchronous sequential machine is also finite.

Q. Design a sequential circuit which performs following.

A B O/P Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

The carry is added with the I/Ps in the next clock pulse.
Ans: Lets take two input strings X1=0111 and X2=0101.

0 1 1 1
1 1 0 0

0 1 0 1

Here the output at time ti is a function of the inputs X1 and X2 at the time ti and of the carry generated
for the input at ti−1.
O/P =func.( I/P at ti and carry generated for the input at ti−1),
therefore, this is a sequential circuit.
The table above illustrates the two types of cases arisen. These are:
i. Producing carry ‘0’
ii. Producing carry ‘1’
We have to consider this as the O/P depends of the carry also.
Lets consider the cases as two states A for(i) and B for (ii). A table is constructed for the inputs X1
and X2. This is called state table.

Present state (PS) Next state (NS), O/P(Z)

X1X2 00 01 11 10
A A,0 A,1 B,0 A,1
B A,1 B,0 B,1 B,0

This tabular form can be represented more clearly by a graphical notation. This is called state graph or
state diagram

11/0

01/0,
A B 11/0,
10/1
00/0,
01/1, 00/1
. 10/1
4 Automata Theory and Formal Languages

For designing a circuit we need only ‘0’ and ‘1’ i.e., boolean values. Hence the states A and B must be
assigned boolean numbers. As there are only two states A and B so only one digit boolean value is suf-
ficient. Lets assign A as ‘0’ and B as ‘1’.
By assigning these boolean values to A and B the modified table become.

Next State (Y) Out put

Present X1X2 00 01 11 10 00 01 11 10
State(y)
0 0 0 1 1 0 1 0 1
1 0 1 1 1 1 0 1 0

Where the function for next state Y = X1X2 + X1y + X2y, and
the function for output Z = X ′1X ′2y + X ′1X2y ′ + X1X ′2y ′ + X1X2y
= X1 ⊕ X2 ⊕ y.
A digital circuit can easily be designed using the above functions. This is the circuit for full binary
adder.

Z = X ¢1X ¢2y + X ¢1X2y ¢ + X1X ¢2y ¢ + X1X2y

Y = X1X2 + X1y + X2y

X1 X2 y

D Flip
Flop

Q. Design a full binary substractor.

Ans. The truth table for a substractor is as follows:
 Finite State Machine 5

A B O/P Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Lets assign two input strings X1=1010 and X2=0111.

1 0 1 0
0 0 1 1

0 1 1 1

Here the output at time ti is a function of the inputs X1 and X2 at the time ti and the borrow generated for
the input at ti−1.
O/P=func.( I/P at ti and carry generated for the input at ti−1).
Therefore, this is a sequential circuit.
In the above table, two types of cases are arisen. These are:
i. Producing Borrow ‘0’
ii. Producing Borrow ‘1’
We have to consider the above as the O/P depends on the borrow too.
Lets consider the cases as two states S1 for(i) and S2 for (ii). The state table for the binary substractor
is constructed for the inputs X1 and X2:

NS (Y), O/P(Z)
PS X1X2 00 01 11 10
S1 S1,0 S2,1 S1,0 S1,1
S2 S2,1 S2,0 S2,1 S1,0

The state graph for binary substractor:

01/1

00/0, 00/1
11/0, S1 S2 01/0
10/1 11/1

10/0

State assignments:
For designing a digital circuit, S1 and S2 are converted into some digital numbers. Since there are only
two states, a 1 bit digital number which can produce two types of digital values – 0 or 1; is sufficient to
represent S1 and S2.
6 Automata Theory and Formal Languages

Lets assign S1 to 0 and S2 to 1.

The modified state table is as follows:

Next State (Y) Out put

Present X1X2 00 01 11 10 00 01 11 10
State(y)
0 0 1 0 0 0 1 0 1
1 1 1 1 0 1 0 1 0

Where the function for next state Y = X1 ′X2 + X1 ′y + X2y, and

The function for output Z = X ′1X ′2y + X ′1X2y ′ + X1X ′2y ′ + X1X2y.
The digital circuit designed from the above functions is:

Z = X′1X′2y + X′1X2y′ + X1X′2y′ + X1X2y

Y = X1′X2 + X1′ y + X2y

X1 X2 y

D Flip
Flop

Sequence Detector

Q. Design a two input two output sequence detector which generates an output ‘1’ every
time the sequence 1001 is detected. And for all other cases output ‘0’ is generated. Over-
lapping sequences are also counted.
Ans. Before designing this circuit some clarifications regarding sequence detector is needed.
Lets assign the input string as 1001001.
 Finite State Machine 7

We have to design the circuit in such a way that it will take one input at a time. The input can be either
‘0’ or ‘1’ (two types of input). The output will be also two types, either ‘0’ or ‘1’. The circuit can store
(memorize) the input string up to four clock pulses (ti−3 to ti).
If the input string is placed according to clock pulses, the output is as follows:

t1 t2 t3 t4 t5 t6 t7
I/P 1 0 0 1 0 0 1
O/P 0 0 0 1 0 0 1

The first input at t1 is 1 and as there is no input from ti−3 to ti the input sequence does not equal to 1001.
So the output will be 0. Similar cases occur for the inputs upto t3.
However, at time t4 the input from ti−3 to ti becomes 1001, hence the output ‘1’ is produced at time t4.
At time t5 and t6 the input string from ti−3 to ti are 0010 and 0100, respectively. Therefore, the output ‘0’
is produced. At t7 clock pulse the input string is 1001, hence output ‘1’ is produced. As the output ‘1’ at
t4 is overlapped from t1 to t4 and from t4 to t7, this is called overlapping condition.

1001001

In this case the state diagram is to be drawn first according the following process:

0/0

1/0 0/0 0/0

S1 S2 S3 S4
1/0

1/0

1/1

In state S1, input may be either ‘0’ or ‘1’. If given input ‘0’, there is no chance to get 1001. Hence it loops on S1
with output ‘0’. If the input is ‘1’, there is a chance to get 1001 then machine moves to S2 producing output ‘0’.
In S2 again the input may be either ‘0’ or ‘1’. If it is ‘1’, the input becomes 11. There is no chance
to get 1001 by taking previous inputs. But again there is a chance to get 1001 by considering the given
input ‘1’. Hence it will be in state S2. (If it goes to S1 then there will be loss of clock pulse, i.e. from S1
by taking input ‘1’, again it has to come to S2, i.e., one extra input, i.e. one clock pulse is needed and
hence the output will not be in right pattern). If the input is ‘0’, the input becomes 10 – by considering
the previous input and there is chance to get 1001, so it will come to S3.
In S3 if it gets input ‘0’, the input becomes 100 by considering the previous input and it has a chance
to get 1001, so it can shift to S4. But if it gets ‘0’, it has no chance to get 1001 considering the previous
input, but there is a chance to get 1001 by considering the given input ‘1’. So it will shift to S2 as we
know by getting ‘1’ in S1 the machine comes to S2.
In S4 if it gets ‘0’, the input will become 1000, but it does not match with 1001. Therefore, it has to
start from the beginning i.e., S1. As overlapping condition is accepted, hence from the last ‘1’ of 1001 if
it gets 001 only, it will give an output ‘1’. Therefore it will go to S2.
8 Automata Theory and Formal Languages

State table:
A state table can easily be constructed from the above state diagram.

PS NS, O/P
X 0 1
S1 S1,0 S2,0
S2 S3,0 S2,0
S3 S4,0 S2,0
S4 S1,0 S2,1

State assignment:
The states must be assigned to some binary numbers to make a digital circuit. This is called state as-
signment. As the number of states is four, only two digit number is sufficient to represent the four states
(22=4).
Lets assign
S1 to 00,
S2 to 01,
S3 to 11,
S4 to 10.

After doing this state assignment the state table becomes

PS (y1y2) NS (Y1Y2) O/P (z)

X 0 1 0 1
00 00 01 0 0
01 11 01 0 0
11 10 01 0 0
10 00 01 0 1

The digital function can easily be derived from this state assignment table:
Y1 Y2 z

X X X
0 1 0 1 0 1
y1y2 y1y2 y1y2
Y1=X ′y2 00 0 0 00 0 1 00 0 0
Y2=X+ y1 ′y2
01 1 0 01 1 1 01 0 0
z=Xy1y2 ′
11 1 0 11 0 1 11 0 0
10 0 0 10 0 1 10 0 1
 Finite State Machine 9

Y1 and Y2 are next states, which are the memory elements. These will be fed back to the input as state y1
and y2 with some delay by D flip flop.
The circuit diagram for this sequence detector will be

Y2 y2
D

clk

X
Y1 y1
D
z = Xy1y2′

Q. Design a two input two output sequence detector which generates an output ‘1’ every
time the sequence 1010 is detected. And for all other cases output ‘0’ is generated. Over-
lapping sequences are also counted.
Ans. The input string 1010100 is placed according to clock pulses as given below

t1 t2 t3 t4 t5 t6 t7
I/P 1 0 1 0 1 0 0
O/P 0 0 0 1 0 1 0

And the state diagram for the output is as follows:

1/0

0/0 1/0 0/0 1/0

S1 S2 S3 S4

1/0 0/1

0/0
10 Automata Theory and Formal Languages

State table:
A state table constructed from the above state diagram:

PS NS, O/P
X 0 1
S1 S1,0 S2,0
S2 S3,0 S2,0
S3 S1,0 S4,0
S4 S3,1 S2,0

State assignments:
The states must be assigned to some binary numbers to make a digital circuit. This is called state assign-
ment. As the number of states is 4, only two digit number is sufficient to represent the four states (22=4).
Lets assign
S1 to 00,
S2 to 01,
S3 to 11,
S4 to 10.

The state table after this state assignment

PS (y1y2) NS (Y1Y2) O/P (z)

X 0 1 0 1
00 00 01 0 0
01 11 01 0 0
11 00 10 0 0
10 11 01 1 0

The digital function can easily be derived from this state assignment table.
y1 y2 z

X 0 1
X
Y1 = X ′y1 ′y2 + Xy1y2 + X ′y1y2 ′ y1 y2 X 0 1 0 1
y1y2
Y2 = y1 ′y2 + y1 ′X + y1y2 ′ 00 0 1 y1y2
z = X ′y1y2 ′ 00 0 0
01 1 0 00 0 1
01 0 0
01 1 1
11 0 1 11 0 0
11 0 0
10 1 0 10 1 1 10 1 0
 Finite State Machine 11

The next states, Y1 and Y2, are the memory elements. These will be fed back to the input as state y1 and
y2 with some delay by D flip flop

Y1 y1
D

clk

X
z = X ¢y1y2 ¢
y2
D
y2

Binary Counter

Q. Design a Modulo 3 binary counter

Ans. The Modulo 3 Binary counter can count upto three. Binary representation of three is 11. It
can count 00, 01, 10, and 11. There will be an external input x, which will act as a control variable and
determine when the count should proceed. After counting three if it has to proceed, then it will come
back to 00 again.
The state diagram for Mod 3 binary counter:

0/0
S1
1/1 1/0

0/0
0/0
S4 S2

1/0
1/0

S3

0/0
12 Automata Theory and Formal Languages

The state table for Mod 3 binary counter:

PS NS, O/P
X=0 X=1
S1 S1,0 S2,0
S2 S2,0 S3,0
S3 S3,0 S4,0
S4 S4,0 S1,1

There are four states in the machine. Two bits are sufficient to assign four states into binary
number.
Lets assign
S1 to 00,
S2 to 01,
S3 to 10,
S4 to 11.

The state table after this state assignment:

PS (y2y1) NS (Y1Y2) O/P (z)

X 0 1 0 1
00 00 01 0 0
01 01 10 0 0
10 01 11 0 0
11 11 00 0 1

Designing By using Flip Flop (T Flip Flop and SR Flip Flop)

The excitation table for T Flip Flop:

Circuit from Changed to T

0 0 0
0 1 1
1 0 1
1 1 0

In state assignment, 00 is changed to 00 for input 0. Here y1 is changed from 0 to 0, so T1 will be 0. The
y2 is changed from 0 to 1, therefore T1 will be 0. The 00 is changed to 01 for input 1. Here y1 is changed
from 0 to 1, therefore T1 will be 1. The y2 is changed from 0 to 0, hence T1 will be 0. The excitation table
of the counter using T flip flop by this process:
 Finite State Machine 13

PS (y2y1) T 2T1
X=0 X=1
00 00 01
01 00 11
10 00 01
11 00 11

T1 = X,
T2 = Xy1,
z = Xy1y2.

The circuit diagram for the above:

1 1
T1 T2
0 0

The excitation table for SR Flip Flop:

Circuit from Changed to S R

0 0 0 --
0 1 1 0
1 0 0 1
1 1 -- 0

In state assignment, the 00 is changed to 00 for input 0. Here y1 is changed from 0 to 0, hence R1 will
be don’t care and S1 will be 0. The y2 is changed from 0 to 0, hence R2 will be don’t care and S2 will be
0. In state assignment table, 00 is changed to 01 for input 1. Here y1 is changed from 0 to 1, therefore
R1 will be 0 and S1 will be 1. The y2 is changed from 0 to 0, hence R2 will be don’t care and S2 will be 0.
The excitation table of the counter using SR flip flop:

PS (y2y1) X=0 X=1

S1R1 S2R2 S1R1 S2R2
00 0 -- 0 -- 1 0 0 --
01 -- 0 0 -- 0 1 1 0
10 0 -- -- 0 1 0 -- 0
11 -- 0 -- 0 0 1 0 1

S1 = Xy1', R1 = Xy1,
S2 = Xy1y2', R2 = Xy1y2.
14 Automata Theory and Formal Languages

The circuit diagram for the above:

S1 0 y ¢1 S2 0 y ¢2
X

y1 y2
R1 1 R2 1

y1 y2

Q. Design a Modulo 8 binary counter.

Ans. Modulo 8 Binary counter can count upto eight from 000 to 111. There will be an external input
x, which will act as a control variable and determine when the count should proceed. After counting
eight if it has to proceed, then it will come back to 000 again.
The state diagram for Mod 8 binary counter:

0/0

S0
1/1 1/0
0/0

S1 S1 0/0

1/0 1/0

0/0
S6 S2

0/0

1/0 1/0

S5
S3
1/0 0/0
S4
0/0 1/0

0/0

The state table for Mod 8 binary counter:

 Finite State Machine 15

PS NS, O/P
X=0 X=1
S0 S0,0 S1,0
S1 S1,0 S2,0
S2 S2,0 S3,0
S3 S3,0 S4,0
S4 S4,0 S5,0
S5 S5,0 S6,0
S6 S6,0 S7,0
S7 S7,0 S0,1

State assignment:
There are eight states in the machine. The three bits are sufficient to assign eight states into binary
number (23=8).
Lets assign S1 to 000, S2 to 001, S3 to 010, S4 to 011, S5 to 100, S6 to 101, S7 to 101, S8 to 111.

NS (Y1Y2) O/P (z)

PS(y3y2y1)
X 0 1 0 1
000 000 001 0 0
001 001 010 0 0
010 010 011 0 0
011 011 100 0 0
100 100 101 0 0
101 101 101 0 0
101 101 111 0 0
111 111 000 0 1

The excitation table of the counter using T flip flop:

T 3T2T1
PS(y3y2y1)
X=0 X=1
000 000 001
001 000 011
010 000 001
011 000 111
100 000 001
101 000 011
101 000 001
111 000 111
16 Automata Theory and Formal Languages

T1 = X, T2 = Xy1, T3 = Xy1y2, z = Xy1y2y3.

The circuit diagram for the above:

z
1 1 1
T1 T2 T3
0 0

The excitation table of the counter using SR flip flop:

X=0 X=1
PS(y3y2y1)
S1R1 S2R2 S3R3 S1R1 S2R2 S3R3
000 0 – 0 – 0 – 1 0 0 – 0 –
001 – 0 0 – 0 – 0 1 1 0 0 –
010 0 – – 0 0 – 1 0 – 0 0 –
011 – 0 – 0 0 – 0 1 0 1 1 0
100 0 – 0 – – 0 1 0 0 – – 0
101 – 0 0 – – 0 0 1 1 0 – 0
110 0 – – 0 – 0 1 0 – 0 – 0
111 – 0 – 0 – 0 0 1 0 1 01

S1=Xy1', R1=Xy1,
S2=Xy1y2', R2=Xy1y2,
S3=Xy1y2y3', R3=Xy1y2y3.

The circuit diagram for the above:

X S1 0 y ¢1 S2 0 y ¢2 S3 0 y ¢3

R1 1 y1 R2 1 y2 y3
R3 1

z
y1 y2 y3

Q. What do you mean by finite state machine?

Ans. Finite state machine can be defined as a type of machine whose past histories can affect its fu-
ture behavior in a finite number of ways. To clarify, consider for example of binary full adder. Its output
 Finite State Machine 17

depends on the present input and the carry generated from the previous input.
It may have a large number of previous input histories but they can be divided into two types: (i)
Input combination that produces carry; (ii) Input combination that produces no carry.
Implying the past histories can affect the future behavior in a finite number of ways (here 2).
Q. What are the capabilities and limitations of finite-state machine?
Ans. Let a finite state machine have n states. Let a long sequence of input be given to the machine.
The machine will progress starting from its beginning state to the next states according to the state tran-
sitions. However, after some time the input string may be longer than n, the number of states. As there
are only n states in the machine, it must come to a state it was previously been in and from this phase
if the input remains the same the machine will function in a periodically repeating fashion. From here
a conclusion that ‘for a n state machine the output will become periodic after a number of clock pulses
less than equal to n’ can be drawn.
States are memory elements. As for a finite state machine the number of states is finite, so finite
number of memory elements are required to design a finite state machine.

S1 S2 Sn
I1
I2I3…….In᎑1

Limitations:
(a) No finite state machine can be produced for an infinite sequence.
Lets consider the design of a finite state machine which receives a long sequence of 1. The machine
will produce an output 1, when the input string length will be equal to [p(p+1)]/2, where p=1,2,3,…,
and 0 for all other cases.
Therefore for p = 1, [p(p + 1)]/2 = 1. In first place there will be o/p 1.
For p = 2, [p(p + 1)]/2 = 3. In third place there will be o/p 1.
For p = 3, [p(p + 1)]/2 = 6. In sixth place there will be o/p 1.
For this type of machine the input output form is as follows:

Time t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15

I/P 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
O/P 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1

Here the output does not become eventually periodic after a certain number of clock pulses. Hence from
this type of sequence no finite state machine can be produced.

(b) No finite state machine can multiply two arbitrary large binary numbers.
Lets consider multiplying two binary numbers given that are input serially to a finite state machine
for multiplication. The inputs are given to the machine with least significant bit (LSB) first then the
other bits. Suppose, to multiply 2m ´ 2m, where m>n (n is the number of states of the Machine), the result
will be 22m.
18 Automata Theory and Formal Languages

The 2m is represented by one 1 followed by m number of ‘0’s (Simlarly 23=1000). Hence the inputs
are given to the machine from t1 to tm + 1 time. Throughout the time the machine produces ‘0’. At tm + 2
times the input stops and the machine produce output 0 followed by 1 from tm + 2 to t2m time.

In the time period tm + 1 to t2m, no input is given to the machine, but the machine produces outputs. As
m > n, according to the definition of Finite State machine the output must be periodic and the period
must be < m. As we are not getting any repeating output sequence, therefore Binary Multiplication of
two arbitrary large binary numbers is not possible to design by using finite state machine.

t2m+1 t2m ... tm+1 tm ... t2 t1 time

1 0 0 0 First number
1 0 0 0 Second number
1 0 … 0 0 … 0 0 Result

1.3 STATE EQUIVALENCE AND MINIMIZATION OF MACHINE

Q. What do you mean by state equivalence and state distinguishable? Give an example to
clarify this.
Ans. Two states Si and Sj of machine M are said to be equivalent if they produce same output se-
quences for all input string applied to the machine M, considering Si and Sj as initial states.
Two states Si and Sj of machine M are said to be distinguishable if there exists a minimum length
input sequence which when applied to the machine M, considering Si and Sj as the initial states, produce
different output sequence. (Input string is always applied on initial state)
The sequence that distinguishes those two states is called distinguishing sequence for the pair Si and
Sj.
If two states Si and Sj are distinguished for the input string of length k, then Si and Sj are called k
distinguishable. The k is the minimum number of the length of the string for which the states produce
different output. If two states are k distinguishable then they are (k–1) equivalent for k=k to 1.
The table given below elucidates the concept

NS, z
PS
x=0 x=1
A E,0 C,0
B F,0 C,1
C E,0 A,0
D F,0 A,1
E A,0 D,0
F D,0 E,1

Consider the previous example.

 Finite State Machine 19

The states A and C give same output (here 0) for the input string of length 1 (Either 0 or 1). Hence
A and C are 1 Equivalent.
States A and B give different output for input string of length 1 (For input string length 0, means for
no input – outputs are same; but for length 1, in case of input 1 they produce different outputs). There-
fore, A and B are 1 distinguishable.
Let check for string length 2. String length 2 means it gives four types of combinations 00, 01, 11
and 10.

PS 00 01 11 10
A 00(A) 00(A) 00(A) 00(E)
B 00(D) 01(E) 10(A) 10(A)
C 00(E) 00(D) 00(C) 00(E)
D 00(D) 01(E) 10(C) 10(C)
E 00(E) 00(C) 01(A) 00(F)
F 00(D) 01(A) 10(D) 10(A)

The A and E are 2 distinguishable, since they produce different output for 11. Distinguishing sequence
for A and E is 11.
Q. Define equivalent partition. Prove that equivalent partition is unique.
Ans. Equivalent partition of a machine M can be defined as a set of maximum number subsets of
states where states which reside in same subset are equivalent for any input given to the states. The
states which reside in different subsets are distinguishable for some input.

Proof:
Suppose for a machine M there exist two equivalent partitions P1 and P2, where P1 ≠ P2. As P1 ≠ P2,
there must exist atleast two states Si and Sj, which are in the same block of one partition (Let P1) and
different blocks in other partition(Let P2). As they are in different blocks in P2, there must exist an input
sequence which distinguishes Si and Sj. Hence they cannot be in the same block of P1. Therefore, our
assumption is wrong. For a single machine here cannot exist two equivalent partitions.
Hence, from here we can conclude that Equivalent partition is unique, i.e. P1 ≡ P2.
Q. Find the equivalent partition for the machine given below. From here minimize the above
machine.

NS, z
PS
x=0 x=1
A E,0 C,0
B F,0 C,1
C E,0 A,0
D F,0 A,1
E A,0 D,0
F D,0 E,1
20 Automata Theory and Formal Languages

Ans. For string length 0 (i.e. for no input) there is no output, Hence all the states are equivalent.
P0 = (ABCDEF).
Consider for string length 1 (i.e. two inputs 0 or 1). For 0, for all states output is 0. For 1 we
get different output for (ACE) and (BDF). States A and B are 1 distinguishable. The A and C are 1
equivalent.
Therefore,
P1=[(ACE) (BDF)].

Consider for string length 2 (i.e. four types of input 00, 01, 11, and 10)

PS 00 01 11 10
A 00(A) 00(A) 00(A) 00(E)
C 00(E) 00(D) 00(C) 00(E)
E 00(E) 00(C) 01(A) 00(F)
B 00(D) 01(E) 10(A) 10(A)
D 00(D) 01(E) 10(C) 10(C)
F 00(D) 01(A) 10(D) 10(A)

For A and C, outputs are same for 00, 01, 11, and 10. However, E has different output for 11. For B, D,
and F outputs are same for all inputs.
P2 = [(AC)(E)(BDF)].

Consider for string length 3 [i.e. eight types of input combinations]. Hence it will be difficult to find
output sequences and the equivalent partitions, as the length of input string increases.
It will be easier to check for the next states.
We know P1 = [(ACE) (BDF)].
Lets rename (ACE) as set S1 and (BDF) as set S2.

For ACE with input 0, the next states are (EEA). Both A and E belong to set S1. For input 1, the next
states are (CAD). Here A and C belong to set S1, but D belongs to set S2. Therefore, the set (ACE) will
be divided as (AC) and (E) for input string length 2.
For (BDF) with input 0, the next states are (FFD). Both F and D belong to same set S2. For input
1, the next states are (CAE). All of these belong to same set S1. So (BDF) cannot be divided for input
string length 2.
The partition of states becomes:
P2=(AC)(E)(BDF) (Same result obtained with considering output).

Lets check for input string length 3.

For (AC) with input 0, the next states are (EE). Both the next states belong to single set. For input 1,
the next states are (AC). Both the next states belong to single set. So (AC) cannot be divided for input
string length 3.
(E) is a set of single state. So (E) cannot be divided.
For (BDF) with input 0, the next states are (FFD). All of them belong to single set. With input 1, the
next states are (CAE). The C and A belong to one set in P2 and E belongs to another set in P2. Hence
 Finite State Machine 21

(BDF) will be divided as (BD) and (F) for input string length 3.
The partition of states becomes:
P3 = (AC)(E)(BD)(F).

Lets check for input string length 4.

For (AC) with input 0, the next states are (EE), belong to single set. For input 1, the next states are
(AC), belong to single set. Hence (AC) cannot be divided for input string length 4.
The (E) is a set of single state. Hence (E) cannot be divided.
For (BD) with input 0 and 1, the next states are (FF) and (AC), respectively. (FF) belong to a single
set and (AC) also belong to a single set. Hence (BD) cannot be divided. As (F) is a single state, it cannot
be divided.
The partition of states becomes
P4 = (AC)(E)(BD)(F).
As P3 and P4 consist of same partitions, P3 = (AC)(E)(BD)(F) is the equivalent partition for the
machine M.

Minimization:
We know that equivalent partition is unique. So P3 = (AC)(E)(BD)(F) is the unique combination. Here
each single set represents one state of the minimized machine.
Lets rename these partitions for simplification.
Rename (AC) as S1, (E) as S2, (BD) as S3, and (F) as S4.

The AC with input 0, goes to (EE) with output 0, hence there will be a transaction from S1 to S2 with
output 0. E with input 0, goes to A producing output 0. A belongs to set S1 in the minimized machine,
Hence there will be a transaction from S2 to S1 with output 0. By this process, the whole table of the
minimized machine is constructed.
The minimized machine is as follows:

NS, z
PS
x=0 x=1
S1(AC) S2,0 S1,0
S2(E) S1,0 S3,0
S3(BD) S4,0 S1,1
S4(F) S3,0 S2,1

Q. Find the equivalent partition for the machine given below. From here minimize the above
machine.

NS, z
PS
x=0 x=1
A B,0 H,1
22 Automata Theory and Formal Languages

B C,0 G,1
C B,0 F,1
D F,1 C,1
E B,1 C,1
F B,1 B,1
G C,1 B,1
H D,1 A,1

Ans. For string length 0 (i.e. for no input) there is no output, hence all the states are equivalent. It is
called 0-equivalent. Expressed as
P0 = (ABCDEFGH).
For string length 1, there are two types of inputs — 0 and 1. The states A, B, and C give output 0 for
input 0 and states D, E, F, G, and H give output 1 for input 0. All the states give output 1 for input 1.
Therefore, the states in the set P0 is divided into (ABC) and (D, E, F, G, and H). Written as
P1 = [(ABC) (DEFGH)].

Here A and F are 1 distinguishable because they produce different outputs for input string length 1. For
input string length 2, check the distinguishability by next state combination. The states A, B, and C for
input 0 produce next states B, C, and B, respectively, and produce next states H, G, and F for input 1.
BCB belong to same set, and HGF also belong to same set. Hence ABC cannot be partitioned for input
string length 2.
The states DEFGH for input 0, produce next states F, B, B, C, and D, respectively, and produce next
states C, C, B, B, and A for input 1. The B, B, and C belong to same set but F and D belong to different
sets. Hence the set (DEFGH) is portioned into (DH) and (EFG). The new partition becomes
P2 = {(ABC)[(DH)(EFG)]}.

The states D and G are 2 distinguishable, because they produce different outputs for input string
length 2.
The states A,B, and C for input 0 produce next states B,C, and B respectively and produce next states
H,G,F for input 1. BCB belong to same set, but H and G, F belong to different set. Hence the set (ABC)
is partitioned into (A) and (BC).
The states B and H produce next states C and D, respectively for input 0 and produce next states G
and A for input 1. C and D belong to different sets hence the set (BH) is divided to (B) and (H).
The states E, F, and G produce next states B, B and C for input 0 and next states C, B, and B for input
1. Both B and C belong to same set, so the set (EFG) cannot be partitioned.
The new partition becomes
P3 = {[(A)(BC)]{[(D) (H)] (EFG)}}.

Here A and B are 3 distinguishable, because they produce different outputs for input string length 3.
By this process we will get P4 also as
P4 = {[(A)(BC)] {[(D)(H)] (EFG)}}.

As P3 and P4 consist of same partitions, therefore P3={[(A)(BC)]{[(D)(H)](EFG)}} is the equivalent

partition for the machine M.
 Finite State Machine 23

Minimization:
We know that equivalent partition is unique. Therefore P3 = {[(A)(BC)]{[(D)(H)] (EFG)}} is the unique
combination. Here each single set represents one state of the minimized machine.
Lets rename these partitions for simplification.
Rename (A) as S1, (BC) as S2, (D) as S3, (H) as S4 and (EFG) as S5.

State (A) with input 0 goes to (B), Hence there will be transaction from S1 to S2 with input 0. The (A)
with input 1 goes to (H), hence there will be transaction from S1 to S4 with input 1. The (BC) with input
0 goes to (BC) for input 0. There will be a transaction from S2 to S2 for input 0. State (BC) with input 1
goes to (FG). There will be transaction from S2 to S5 for input 1.
By this process the whole table of the minimized machine is constructed.
The minimized machine becomes

NS, z
PS
x=0 x=1
S1(A) S2, 0 S4, 1
S2(BC) S2, 0 S5, 1
S3(D) S5, 1 S2, 1
S4(H) S3, 1 S1, 1
S5(EFG) S2, 1 S2, 1

1.4 INCOMPLETELY SPECIFIED MACHINE AND MINIMAL MACHINE

Q. Define incompletely specified machine? How an incompletely specified machine can be
simplified? Simplify the following incompletely specified machine.

PS 00 01 11 10
A _, _ B,0 C,1 _, _
B A,0 B,1 _,0 C,_
C D,1 A,_ B,0 D,1
D _,0 _, _ C,0 B,1

Ans. In real life, for all states for all inputs, the next state or outputs or both are not mentioned. For
such types of machines, where for all states for all inputs the next state, or output or both are not men-
tioned, those types of machines are called incompletely specified machine.
In the previous machine for state A for 00 input no next state and outputs are specified. Hence the
previous machine is an example of incompletely specified machine.
24 Automata Theory and Formal Languages

Simplification:
An incompletely specified machine can be simplified by the following steps:
(a) If next state is not mentioned for a state, for a given input, put a temporary state T in that place.
(b) If output is not mentioned, make it blank.
(c) If next state and output are not mentioned, put a temporary state T in next state place and nothing
in output place.
(d) Add the temporary state T in the present state column, putting T as next state and no output for
all inputs.
By following the previous steps, the simplification of the previous incompletely specified machine is
as follows:

NS, Z
PS
00 01 11 10
A T, _ B,0 C,1 T, _
B A,0 B,1 T,0 C,_
C D,1 A,_ B,0 D,1
D T,0 T, _ C,0 B,1
T T,_ T,_ T,_ T,_

Q. Simplify the following incompletely specified machine.

NS, Z
PS
I1 I2 I3
A C,0 E,1 __
B C,0 E, _ __
C B, _ C,0 A, _
D B,0 C, _ E, _
E __ E,0 A, _

Ans. Put a temporary state T in the next state place, where next states are not specified. If the output
is not mentioned, need to put any output.
As a temporary state T is considered, so T is put in the present state column with next states T for all
inputs with no output.
The simplified machine becomes

NS, Z
PS
I1 I2 I3
A C,0 E,1 T, _
B C,0 E, _ T, _
 Finite State Machine 25

C B,_ C,0 A, _
D B,0 C,_ E, _
E T, _ E,0 A, _
T T, _ T,_ T, _

Q. Define Minimal machine. What is the difference with it with minimum machine? Give an
example.
Ans. Minimal machine is the minimum of the machines obtained by minimizing an incompletely
specified machine.
In an incompletely specified machine, for all states and for all inputs, the next state, or output or
both are not mentioned. At the time of minimizing the incompletely specified machine different persons
can take the not mentioned next states or outputs according to their choice. Therefore there is a great
possibility to get different equivalent partitions for a single machine. But we know equivalent parti-
tion is unique for a given machine. It is not possible to find a unique minimized machine for a given
incompletely specified machine most of the times. Therefore our aim must be to find a reduced machine
which not only covers the original machine but also has a minimal (least of the minimum) number of
states. This type of machine is called minimal machine, i.e. it is the minimum of the machines obtained
by minimizing an incompletely specified machine.
Example: Lets consider the following incompletely specified machine:

NS, z
PS
x=0 x=1
A E,1 D,0
B E,0 C,1
C A,0 B, _
D A,0 D,1
E A, _ B,0

In this machine C with input 1 output is not specified and same for E with input 0. There are two types
of outputs occur in the machine. Hence the unspecified outputs can be any of the followings: (a) (B, 0
A, 0); (b) (B, 0 A, 1); (c) (B, 1 A, 1); (d) (B, 1 A, 0).

For (a) the machine and its equivalent partition is

NS, z
PS
x=0 x=1
A E,1 D,0 P0=(ABCDE)
B E,0 C,1 P1=(ABD) (CE)
C A,0 B,0 P2=(A)(B)(D)(CE)
D A,0 D,1
E A,0 B,0
26 Automata Theory and Formal Languages

For (b) the machine and its equivalent partition is

NS, z
PS
x=0 x=1 P0=(ABCDE)
A E,1 D,0
P1=(AE)(BD)(C)
B E,0 C,1
P2=(AE)(B)(D)(C)
C A,0 B,0
P3=(A)(E)(B)(D)(C)
D A,0 D,1
E A,1 B,0

For (c) the machine and its equivalent partition is

NS, z
PS
x=0 x=1
A E,1 D,0 P0=(ABCDE)
B E,0 C,1 P1=(AE)(BCD)
C A,0 B,1
D A,0 D,1
E A,1 B,0

For (d) the machine and its equivalent partition is

NS, z P0 = (ABCDE)
PS
x=0 x=1 P1 = (A)(BCD)(E)
A E,1 D,0
P2 = (A)(B)(CD)(E)
B E,0 C,1
P3 = (A)(B)(C)(D)(E)
C A,0 B,1
D A,0 D,1
E A,0 B,0

In cases (b) and (d), the number of equivalent partitions are 5, equals to the number of states of the
machine, i.e. machine constructed from the equivalent partitioned obtained in cases (b) and (d) and the
original machines for cases (b) and (d) are the same.

1.5 MERGER GRAPH AND COMPATIBILITY GRAPH

Q. What is Merger graph?
Ans. Merger graph of a machine M of n states is an undirected graph defined as follows.
 Finite State Machine 27

1. Merger graph consists of n number of vertices, where n is the number of states of the machine.
That is in other words each states of the machine represent one vertex.
2. There is an undirected arc between a pair of vertices (states) if the outputs do not conflict for
those pair of states.
(a) The arc will be an uninterrupted arc if the next states of the two states [Vertices] do not con-
flict.
(b) The arc will be an interrupted arc if the next states of the states [Vertices] conflict. The conflicting next
states will be placed in the interrupted portions.

3. There will be no arc between the two vertices if the outputs of the pair of states conflict.
Q. Develop the Merger graph for the following machine.

PS NS, z
I1 I2 I3 I4
A E,1 B, 0 _, _ E, 0
B _, _ _, _ _, _ C, 0
C D, 1 F, 0 A, 0 _, _
D _, _ B, 1 _, _ _, _
E _, _ _, _ A, 1 A, 0
F B, 1 C, 1 E, 1 _, _

Ans. In the above machine there are six states. Therefore, number of vertices of the Merger Graph
is six, namely A, B, C, D, E, and F.
Lets consider two vertices A and B. In the state table for A and B for input I1, outputs are 1 and don’t
care. It is treated as same output (Don’t care can be either 0 or 1). Same for I2, I3, and I4 the outputs do
not conflict. (If the outputs are don’t care, consider it same with the other) Therefore, an undirected arc
is drawn between A and B.
For input I4, A produces next state E and B produces next state C. Hence the undirected arc between
A and B is an interrupted arc and EC is placed in the interrupted portion.

Consider A and C. The outputs do not conflict for inputs I1, I2, I3, and I4. An undirected arc is drawn
between A and C. The next states produced by A and C for input I1 are D and E, i.e. conflicting. For
input I2 the next states are B and F – also conflicting. The arc is an interrupted arc and (BF) and (DE) is
placed in the interrupted portion.
Consider A and D. For input I2, A and D produce conflicting outputs – 0 for A and 1 for B. So no arc
can be drawn between A and D.
Consider A and E. For all the inputs they produce same outputs. An undirected arc is drawn between
A and E. The A and E produce next states E and A, respectively, for input I4. Hence the arc is an inter-
rupted arc and (EA) is placed in the interrupted portion.
Consider A and F. The A and F produce conflicting outputs (0 for A, 1 for F) for input I2. Hence no
arc can be drawn between A and F.
28 Automata Theory and Formal Languages

By this process, an uninterrupted arc is drawn between B and C.

An uninterrupted arc is drawn between B and D.
An interrupted arc is drawn between B and E and AC is placed in the interrupted portion.
An uninterrupted arc is drawn between B and F.

For input I2, C and D produce conflicting outputs. No arc can be drawn between C and D.
For input I3, C and E produce conflicting outputs. No arc can be drawn between C and E.
For input I3, C and F produce conflicting outputs. No arc can be drawn between C and F.

The D and E produce same outputs and same next states for all the inputs. An uninterrupted arc is drawn
between D and E.
The D and F produce same outputs for all the inputs but conflicting next states (B and C) for input I2.
An interrupted arc is drawn between D and F and BC is placed in the interrupted portion.
The E and F produce same output for all the inputs but conflicting next states (A and E) for input I3.
An interrupted arc is drawn between E and F and AE is placed in the interrupted portion.
The final Merger graph is

×
(CE)

F B

(AE)

(AC)
(AE)
(BF)
(DE)

E (BC)
C

The A and B are connected by an uninterrupted, undirected arc. In the interrupted portion CE is
placed. The connection between A and B will be uninterrupted if C and E are connected by unin-
terrupted arc. But there is no arc between C and E. So there will be no arc between A and B. CE is
crossed therefore.
The A and C are connected by uninterrupted undirected arc. In the interrupted portion DE and BF are
placed. The A and C will be connected by uninterrupted arc if B, F and D, E are connected.
 Finite State Machine 29

E D

A C

B F

If either ED or BF is not connected, there will be no arc between A and C. But here ED and BF are
connected.
Q. Develop the Merger graph for the following machine.

PS NS, z

I1 I2 I3
A E, 0 B, _ C, _
B _, _ D,_ B, 0
C E, _ D, _ C, 0
D C, 0 _, _ B, 1
E C, 0 _, _ B, 1

Ans. Number of states of the machine is 5. So number of vertices of the Merger graph is 5. Let name
them in the name of the states.

Consider two vertices A and B. The states A and B produce same outputs for all the inputs but dif-
ferent next states for input I2 (conflicting states BD) and for input I3 (conflicting states BC). Hence
an interrupted undirected arc is drawn between A and B and (BC), (BD) is placed in the interrupted
portion.
Consider A and C. The two states produce same outputs for all the inputs. However, A and C produce
conflicting next states (BD) for input I2. Therefore, between A and C an undirected interrupted arc is
drawn and (BD) is placed in the interrupted portion.
Consider A and D. The states produce same outputs for all the inputs. But they produce conflicting
next states (BC) and (EC) for inputs I1 and I3, respectively. Therefore an undirected interrupted arc is
drawn between A and D and (BC)(EC) is placed in the interrupted portion.
Consider A and E. The states produce same outputs for all the inputs. But they produce conflicting
next states for input I1 and I3. The conflicting next states are (CE) and (BC). An interrupter arc is drawn
between A and E and (CE)(BC) is placed in the interrupted portion.
Consider B and C. They produce same outputs for all the inputs but conflicting next state pair (BC)
for input I3. Hence an interrupted arc is drawn between B and C placing (BC) in the interrupted portion.
Consider B and D. No arc is drawn between B and D as they produce different outputs for input I3.
Consider B and E. No arc is drawn between B and E as they produce different outputs for input I3.
30 Automata Theory and Formal Languages

Consider C and D. These states produce different outputs for input I3. Therefore no arc is drawn
between C and D.
Consider C and E. These states produce different outputs for input I3. Therefore no arc is drawn
between C and E.
Consider D and E. They produce same outputs and same next state combination for all the inputs.
Therefore an uninterrupted arc is drawn between D and E.

The Merger graph for the above machine:

A
(EC)
(BC) (BC)
(BD)

E B

(EC) (BD)
(BC)
(BC)

D C

Between C and E there is no arc. Hence the combinations (EC)(BC), placed between A,D and A,E is
crossed off. Now there is no connection between A and E, and A and D. There is no arc between B and
D. Hence the next state combination (BC)(BD) and (BD),placed between A,B and A,C, respectively is
crossed off.
Q. Define compatible pair and implied pair. What do you mean by a compatibility graph?
Ans.
Compatible Pair: Two states say Si and Sj are said to be compatible, if both of them give same output
strings for all input strings applied to the machine separately, considering Si and Sj as the initial states.
(In the sense of Merger Graph, two states are said to be compatible if there exists an uninterrupted
arc between the two states.)

Implied Pair: Two states Si and Sj are said to be implied on Sp and Sq, if and only if (Sp, Sq) is compat-
ible then only (Si, Sj) is compatible. (Sp, Sq) is said to be the implied pair of (Si, Sj).

Si ( SpSq) Sj
 Finite State Machine 31

Compatibility Graph: Compatibility graph is a directed graph constructed as follows:

(1) Number of vertices of the compatibility graph corresponds to the number of compatible pairs
obtained from the machine.
(2) A directed arc is drawn between two compatible pairs (vertices) say from (Si, Sj) to (Sp, Sq)
[Where (Si, Sj) ≠ (Sp, Sq)], if (Sp, Sq) is the implied pair for (Si, Sj).

SiSj SpSq

Q. Define closed compatibles and closed covering. How to find a minimal machine from a
given compatibility graph of a machine?
Ans. A Subgraph of a compatibility graph is called closed, if for every vertex in the subgraph, all
outgoing arcs and the terminal vertices of the arcs also belong to the subgraph. The pair of states belongs
to the subgraph as terminal vertices are called closed compatible. If a subgraph is closed, and if every
state of the machine is covered by atleast one vertex of the subgraph of a compatibility graph, then the
subgraph forms a closed covering of the machine.
To find a minimal machine we need to find the subgraphs that closed cover the machine. Then we
need to find the subgraph that contains less number of vertices and, which can generate a simpler ma-
chine. The states of the minimal machine are the vertices of the subgraph. From these states the transi-
tion functions are constructed. By this process a minimal machine of the given machine is constructed.
[There is no easy method to find minimal closed covering. It will be choose manually]
Q. Draw a compatible graph for the following machine. Hence find the minimal machine.

PS NS, z

I1 I2 I3 I4
A E, 1 C, 1 _, _ B, 1
B _, _ _, _ D, 0 D, 1
C _, _ _, _ E, 0 _, _
D C, 0 B, 1 B, 0 _, _
E A, 0 F, 1 _, _ D, 0
F C, 1 _, _ _, _ _, _

Ans: To find the Compatible pairs we need to construct the Merger graph of the machine first. The
Merger graph of the machine:
32 Automata Theory and Formal Languages

A
(CE) (BD)

F B

(DE)

(BD)
E C

(AC) (BE)
(BF) D

The pair of states which are connected by undirected arcs (Not Crossed in the interrupted portion) are
compatible pairs. The compatible pairs of the given machine are (AB), (AC), (AF), (BC), (BD), (BF),
(CE), (CF), and (DE). Therefore in the compatibility graph there are nine vertices.

In the given machine,

The (BD) is implied pair for (AB). Hence a directed arc is drawn from (AB) to (BD).
The (CE) is implied pair for (AF). Hence a directed arc is drawn from (AF) to (CE).
The (DE) is implied pair for (BC). Hence a directed arc is drawn from (BC) to (DE).
The (BD) is implied pair for (BD). As (Si,Sj) ≠ (Sp,Sq), no arc is drawn from (BD) to (BD)
The (AC) and (BF) are implied pair for (DE). The two directed arcs are drawn from (DE) to (AC)
and (BF).
The compatibility graph for the given machine:

AB

AC AF

BC
CF

CE BD

BF DE
 Finite State Machine 33

Minimal machine:
The subgraph (AC), (DE), (BF) or (AB), (BD), (AF), (CE) or (AF), (CE), (BC), and (DE) are closed
subgraphs of the compatibility graph and forms a closed cover of the machine (Here every state of the
machine is covered by atleast one vertex of the subgraph). Among them, the subgraph (AC), (DE), and
(BF) contains less number of vertices. In the minimal machine the states are (AC), (BF), and (DE). Let
rename them as S1, S2, and S3, respectively. The minimal machine becomes

PS NS, z

I1 I2 I3 I4
S1(AC) S3, 1 S1, 1 S3, 0 S2, 1
S2 (BF) S1, 1 _, _ S3, 0 S3, 1
S3 (DE) S1, 0 S2, 1 S2, 0 S3, 0

Q. Draw a compatible graph for the following machine. Hence find the minimal machine.

PS NS, z
I1 I2 I3 I4

A _, _ D, 0 D, 0 C, _
B A, 1 _, _ _, _ D, _
C B, 1 C, 0 E, 0 _, _
D E, 1 C, 0 _, _ D, 0
E _, _ _, _ _, _ A, 1

Ans: To find the compatible pairs of a machine, we need to construct the Merger the graph first. Ac-
cording to the rules of the construction of Merger Graph the following graph is constructed.

(AC) (CD)

E (AD) B

(CD)
(CD) (AB)
(DE)
(AE)

D C
(BE)
Exploring the Variety of Random
Documents with Different Content
I thought he d not been in the world throughout
That durst have wrought England such unright.’

VI
But ever they sighèd, and said, alas!
Unto King Harry this answer againe:
‘He is a proud Scott that will robb us all
Were we twenty shipps and he but one.’

VII
The King looket over his left shouldèr,
Amongst his lords and barrons so free:
‘Have I never a lord in all my realme
Will fetch yond traitor unto me?’

VIII
‘Yes, that dare I!’ says my lord Charles Howard,
Neere to the King wheras he did stand,
‘If that Your Grace will give me leave,
My self will perform what you command.’

IX
‘Thou shalt have six hundred men,’ saith our King,
‘And chuse them out of my realme so free;
[Moreover] mariners and ship boyes,
To guide the great ship on the sea.’

X
‘I’le goe speake with Sir Andrew,’ says my Lord Howard;
‘Upon the sea if he be there;
 Upon the sea, if he be there;
I will bring him and his ship to shore,
Or before my prince I will ne’er come neere.’

XI
The first of all my Lord did call,
A noble gunner he was one;
This man was three score yeares and ten,
And Peter Simon was his name.

XII
‘Peter,’ says he, ‘I must sayle to the sea,
To seek out an enemy; God be my speed!
Before all others I have chosen thee;
Of a hundred gunners thou’st be my head.’

XIII
‘My lord,’ says he, ‘if you’ve chosen me
Of a hundred gunners to be the head,
You may hang me at your maine-mast tree
If I miss my mark past three pence bread[1137].’

XIV
The next of all my lord he did call,
A noble bowman he was one;
In Yorkshire was this gentleman borne,
And William Horsley was his name.

XV
‘Horsley,’ says he, ‘I must sayle to the sea,
To seek out an enemy; God be my speede!
Before all others I have chosen thee;
Of a hundred bowemen thou’st be my head.’

XVI
‘My lord,’ says he, ‘if you’ve chosen me
Of a hundred bowemen to be the head,
Hang me at your main-mast tree
If I miss my mark past twelve pence bread.’

XVII
With pikes, and gunnes, and bowmen bold,
This noble Howard is gone to the sea
On the day before Midsummer-even,
And out at Thames’ mouth saylèd they.

XVIII
They had not saylèd dayès three
Upon their journey they took in hand,
But there they met with a noble ship,
And stoutely made it both stay and stand.

XIX
‘Thou must tell me thy name,’ says Charles my lord Howard,
‘Or who thou art, or from whence thou came,
Yea, and where thy dwelling is,
To whom and where thy ship does belong.’

XX
‘My name,’ says he, ‘is Henery Hunt,
With a pure hart and a penitent mind;
I and my ship they doe belong
Unto the New-castle that stands upon Tyne.’—

XXI
‘Now thou must tell me, Henery Hunt,
As thou hast saylèd by day and by night,
Hast thou not heard of a stout robbèr?
Men calls him Sir Andrew Barton, Knight.’

XXII
But ever he sighèd, and said, ‘Alas!
Full well, my lord, I know that wight;
He has robb’d me of my merchants-ware,
And I was his pris’ner but yesternight.

XXIII
‘As I was sayling upon the sea,
And a Bourdeaux voyage as I did fare,
He claspèd me to his archèborde[1138],
And robb’d me of all my merchants-ware.

XXIV
‘And I am a man both poor and bare,
Every man will have his own of me;
And I am bound towards London to fare,
To complain unto my prince Henrye.
 XXV
‘That shall not need,’ says my Lord Howard;
‘If thou canst let me this robber see,
For every penny he hath taken thee fro’
Thou shall be rewarded a shilling,’ quoth he.

XXVI
‘Now God forfend,’ says Henery Hunt,
‘My lord, you sho’ld work so far amisse!
God keep you out of that traitor’s hands!
For you wot full little what man he is.

XXVII
‘He is brasse within, and steele without,
And beams he bears in his topcastle stronge;
His ship hath ordinance clean round about;
Besides, my lord, he is very well mann’d.

XXVIII

‘He hath a pinnace is dearlye dight[1139],

Saint Andrew’s cross, that is his guide[1140];
His pinnace bears nine-score men and more,
With fifteen cannons on every side.

XXIX
‘Were you twenty ships, and he but one,
Either in archbord or in hall[1141],
He wo’ld overcome you everye one,
 An if his beams they doe down fall.’

XXX
‘This is cold comfort,’ says my Lord Howard,
‘To welcome a stranger thus to the sea;
I’le bring him and his ship to shore,
Or else into Scotland he shall carry me.’

XXXI
‘Then, my lord, you must get a noble gunner;
One that can set well with his e’e,
And sink his pinnace into the sea,
And soon then overcome will he be.

XXXII
‘And when that you have done all this,
If you chance Sir Andrew for to board,
Let no man to his topcastle go;
And I will give you a glass[1142], my lord,

XXXIII
‘And then you need to fear no Scot,
Whether you sayle by day or by night;
And to-morrow, by seven of the clocke,
You shall meete with Sir Andrew Barton, Knight.’

XXXIV
The merchant set Lord Howard a glass
So well apparent in his sight
 So well apparent in his sight
That on the morrow by seven of the clock
He spy’d Sir Andrew Barton, Knight.

XXXV
Lord Howard he swore a mighty oath
When he saw his hache-bords dearly dight;
‘Now by my faith and by my troth,
Yonder proud Scott is a worthy wight.

XXXVI

‘Take in your ancients[1143] and your standards,

Yea, that no man shall them see,
And put me forth a white willow wand,
As merchants use to sayle the sea.’

XXXVII

But they stirr’d[1144] neither top nor mast,

But Sir Andrew they passèd by.—
‘What English are yonder,’ said Sir Andrew,
‘That can[1145] so little curtesye?

XXXVIII
‘I have been admiral over the sea
[Methinketh] more then these yeeres three;
There is never an English nor Portingall dog,
Can pass this way without leave of me.

XXXIX
‘But now yonder pedlars, they are pass’d,
Which is no little grief to me:
Fetch them backe,’ sayes Sir Andrew Barton,
‘They shall all hang at my maine-mast tree.’

XL
With that the pinnace it shot off,
That my Lord Howard might it well ken;
It strokè down my lord’s fore-màst,
And kill’d fourteen of my lord his men.

XLI
‘Come hither, Simon!’ says my Lord Howard,
‘Look that thy words be true thou said;
I’le hang thee at my maine-mast tree
If thou miss thy mark past three pence bread.’

XLII
Simon was old, but his hart it was bold;
He tooke downe a piece, and laid it full low;
Chaine yeards nine he put therein,
Besides other great shot less and moe.

XLIII
With that he let his gun-shot go;
So well he settled it with his e’e,
The first sight that Sir Andrew saw,
He saw his pinnace sunk in the sea.

XLIV
When Sir Andrew saw his pinnace sunk,
Lord! in his heart he was not well!
‘Cut my ropes! it is time to be gone!
I’le goe fetch yond pedlars back mysell!’

XLV
When my Lord Howard saw Sir Andrew loose,
Lord! in his heart that he was faine!
‘Strike on your drums! spread out your ancients!
Sound out your trumpets! sound out amain!’

XLVI
‘Fight on, my men!’ says Sir Andrew Barton;
‘Weate[1146], howsoever this geare[1147] will sway[1148],
It is my Lord Admiral of England
Is come to seek me on the sea.’

XLVII
Simon had a sone; with shot of a gun—
Well Sir Andrew might it ken—
He shot it in at the middle deck,
And killed sixty more of Sir Andrew’s men.

XLVIII
[Bold] Hunt came in at the other side,
And at Sir Andrew he shot then;
He drove down his fore-mast tree,
And kill’d eighty more of Sir Andrew’s men.
 XLIX
‘I have done a good turne,’ sayes Henery Hunt;
‘Sir Andrew is not our King’s friend;
He hoped t’ have undone me yesternight,
But I hope I have quit him well in the end.’

L
‘Ever alas!’ sayd Sir Andrew Barton,
‘What sho’ld a man either thinke or say?
Yonder false thief is my strongest enemy,
Who was my prisoner but yesterday.

LI
‘Come hither to me, thou Gourden good,
And be thou ready at my call,
And I will give thee three hundred pound
If thou wilt let my beames downe fall.’

LII

With that hee swarm’d[1149] the main-mast tree,

Soe did he it with might and maine;
But Horsley, with a bearing arrow[1150],
Stroke the Gourden through the braine.

LIII
And he fell into the hatches againe,
And sore of his wound that he did bleed;
Then word went through Sir Andrew’s men,
 How that the Gourden he was dead.

LIV
‘Come hither to me, James Hamilton,
Thou’rt my sister’s son, I have no more;
I will give thee six hundred pound
If thou wilt let my beames downe fall.’

LV
With that he swarm’d the main-mast tree,
Soe did he it with might and main:
Horsley, with another broad arrow,
Strake the yeaman thoro’ the brain.

LVI
That he fell downe to the hatches againe;
Sore of his wound that hee did bleed,
Covetousness gets no gaine,
It is very true, as the Welshman said.

LVII
But when he saw his nephew slaine,
Lord! in his heart he was not well!
‘Go fetch me downe my armour of proof,
For I will to the topcastle mysell.

LVIII
‘Go fetch me downe my armour of proof,
For it is gilded with gold so cleere;
 g g ;
God be with my brother, John of Barton!
Amongst the Portingalls he did it weare.’

LIX
But when he had his armour of proof,
And on his body he had it on,
Every man that lookèd at him
Said, Gun nor arrow he need fear none.

LX
‘Come hither, Horsley!’ says my Lord Howard,
‘And look your shaft that it goe right;
Shoot a good shoote in the time of need,
And for thy shooting thou’st be made knight.’

LXI
‘I’le do my best,’ sayes Horsley then,
‘Your Honour shall see before I goe;
If I sho’ld be hang’d at your maine-mast tree,
I have in my ship but arrows two.’

LXII
But at Sir Andrew he shot then;
He made so sure to hit his mark;
Under the spole[1151] of his right arme
He smote Sir Andrew quite thro’ the heart.

LXIII
Yet from the tree he wo’ld not start
Yet from the tree he wo ld not start,
But he cling’d to it with might and main;
Under the collar then of his jacke[1152],
He stroke Sir Andrew thoro’ the brain.

LXIV
‘Fight on, my men!’ says Sir Andrew Barton,
‘I am hurt, but I am not slain;
I’le lay me downe and bleed a-while,
And then I’le rise and fight again.

LXV
‘Fight on, my men!’ says Sir Andrew Barton,
‘These English dogs they bite so lowe;
Fight on for Scotland and Saint Andrew
While that you hear my whistle blowe!’

LXVI
But when they co’ld not hear his whistle,
Says Henery Hunt, ‘I’le lay my head
You may board yonder noble ship, my lord,
For I know Sir Andrew he is dead.’

LXVII
With that they boarded this noble ship,
So did they it with might and main;
They found eighteen score Scots alive,
Besides the rest were maim’d and slaine.

LXVIII
Lord Howard took a sword in his hand,
And so smote off Sir Andrew’s head;
The Scots stood by did weepe and mourne,
But never a word they spoke or sayd.

LXIX
He caused his body to be taken downe,
And over the hatch-bord cast into the sea,
And about his middle three hundred crownes:
‘Wheresoever thou lands, it will bury thee!’

LXX
With his head they sayl’d into England againe,
With right good will and force and main,
And on the day before New-Year’s Even
Into Thames’ mouth they came againe.

LXXI
Lord Howard wrote to King Henry’s grace,
With all the newes hee co’ld him bring:
‘Such a New Year’s gift I have brought to your Grace
As never did subject to any King.

LXXII
‘For merchandise, yea and manhood,
The like is nowhere to be found;
The sight of these wo’ld do you good,
For you have not the like in your English ground.’
 LXXIII
When the King heard tell that they were come,
Full royally he welcomed them home;
Sir Andrew’s ship was his New-Year’s gift;
A braver ship you never saw none.

LXXIV
Now hath our King Sir Andrew’s ship,
Beset with pearles and precyous stones;
And now hath England two ships of war,
Two ships of war, before but one.

LXXV
‘Who holpe to this?’ says King Henrye,
‘That I may reward him for his paine.’—
‘Henery Hunt, and Peter Simon,
William Horsley, and I the same.’—

LXXVI
‘Harry Hunt shall have his whistle and chaine,
And all his jewels whatsoe’er they be,
And other rich gifts that I will not name,
For his good service he hath done me.

LXXVII
‘Horsley, right thou’st be a knight,
Lands and livings thou shalt have store;
Howard shall be Earl of Nottingham,
And so was never Howard before.
 LXXVIII
‘Now, Peter Simon, thou art old;
I will maintaine thee and thy son;
Thou shalt have five hundred pound all in gold
For the good service that thou hast done.’

LXXIX

With that King Henrye shifted his room[1153];

In came the Queene and ladyes bright;
Other arrands they had none
But to see Sir Andrew Barton, Knight.

LXXX
But when they saw his deadly face,
His eyes were hollow in his head;
‘I wo’ld give a hundred pound,’ says his Grace,
‘The man were alive as he is dead!

LXXXI
‘Yet for the manful part he hath play’d,
Both here at home and beyond the sea,
His men shall have half-a-crowne a day
Till they come to my brother, King Jamie.’

FOOTNOTES:
[1137] three pence bread = the breadth of a threepenny piece.
[1138] archèborde = hatch-board.
[1139] dearlye dight = expensively fitted or ornamented.
[1140] guide = guidon, signal flag.
[1141] hall = hull.
[1142] glass = a lantern to guide the man-of-war’s course by the
merchantman’s.
[1143] ancients = ensigns.
[1144] stirr’d = moved, lowered.
[1145] can = ken, know.
[1146] Weate = wit ye, know.
[1147] geare = business, fighting.
[1148] sway = go, turn out.
[1149] swarm’d = climbed.
[1150] bearing arrow = a long arrow for distant shooting.
[1151] spole = shoulder, épaule.
[1152] jacke = jacket, short coat of mail.
[1153] shifted his room = made place.
131. The ‘George-Aloe’
 I
The George-Aloe, and the Sweepstake, too,
With hey, with hoe, for and a nony no,
O, there were two Merchant-men, a sailing for Safee
And alongst the Coast of Barbarye.

II
The George-Aloe came to anchor in the bay,
With hey, &c.
But the jolly Sweepstake kept on her way,
And alongst, &c.

III
They had not sayl’d but leagues two or three,
With hey, &c.
But they met with a French Man-of-War upon the Sea,
And alongst, &c.

IV
‘All haile, all haile, you lusty Gallants all!
With hey, &c.
Of whence is your fair Ship, and whither do ye call?’
And alongst, &c.

V
‘We are Englishmen, and bound for Safee,’—
With hey, &c.
‘Ay, and we are Frenchmen, and war upon the sea,
Ay, and we are Frenchmen, and war upon the sea,
And alongst, &c.

VI
‘Amaine, Amaine, you English dogs, hail!’—
With, hey, &c.
‘Come aboard you French swads[1154], and strike down your sayle,’
And alongst, &c.

VII
They laid us aboard on the Starboard side,
With hey, &c.
And they threw us into the Sea so wide,
And alongst, &c.

VIII
When tidings to the George-Aloe came,
With hey, &c.
That the jolly Sweepstake by a Frenchman was ta’en,
And alongst, &c.

IX
‘To top, to top, thou little Cabin-boy,
With hey, &c.
And see if this French Man-of-War thou canst descry,’—
And alongst, &c.

X
‘A Sayle, a Sayle, under our lee!
With he &c
 With hey, &c.
Yea, and another that is under her obey!’
And alongst, &c.

XI
‘Weigh anchor, weigh anchor, O jolly Boat-swain!
With hey, &c.
We will take this Frenchman, if we can,’
And alongst, &c.

XII
We had not sayl’d leagues two or three,
With hey, &c.
But we met the French Man-of-War upon the Sea,
And alongst, &c.

XIII
‘All haile, All haile, you lusty Gallants hail!
With hey, &c.
Of whence is your faire Ship, and whither do ye sayl?’
And alongst, &c.

XIV
‘O, we are Merchant-men and bound for Safee,’—
With hey, &c.
‘Ay, and we are Frenchmen, and war upon the sea,
And alongst, &c.

XV
‘Amaine, Amaine, you English Dogges, hail!’—
With hey, &c.
‘Come aboard, you French rogues, and strike down your sayl!’
And alongst, &c.

XVI
The first good shot that the George-Aloe shot,
With hey, &c.
He made the Frenchman’s heart sore afraid,
And alongst, &c.

XVII
The second shot the George-Aloe did afford,
With hey, &c.
He struck their main-mast over the board,
And alongst, &c.

XVIII
‘Have mercy, have mercy, you brave English Men!’—
With hey, &c.
‘O, what have you done with our merry Brethren?’—
As they sayl’d in Barbarye?

XIX
‘We laid them aboard the starboard side,
With hey, &c.
And we threw them into the Sea so wide,’—
And alongst, &c.

XX
‘Such mercy as you have shewed unto them,
With hey, &c.
Then the like mercy shall you have again,’—
And alongst, &c.

XXI
We laid them aboard the larboard side,
With hey, &c.
And we threw them into the Sea so wide,
And alongst, &c.

XXII
Lord, how it grieved our hearts full Sore,
With hey, &c.
To see the drowned Frenchmen to swim along the shore!
And alongst, &c.

XXIII
Now gallant Seamen I bid you all adieu,
With hey, &c.
This is the last Newes I can write to you,
To England’s Coast from Barbarye.
 FOOTNOTES:
[1154] swads = peascods, a cant term for soldiers.
132. The ‘Golden Vanity’
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