FLIP FLOPS, JK FLIP FLOP, D FLIP FLOP, LATCH

What is Flip-Flop?

Flip-flop is a basic digital memory circuit, which stores one bit of information. Flip flops are the
fundamental blocks of most sequential circuits. It is also known as a bistable multivibrator or a
binary or one-bit memory. Flip-flops are used as memory elements in sequential circuits. The
output is obtained in a sequential circuit from the Flip-flopscombinational circuit or flip-flop or
both. The state of flip-flops changes at the active state of clock pulses and remains unaffected
when the clock pulse is not active. In particular, clocked flip flops serve as memory elements in
synchronous sequential Circuits and unclocked flip-flops (i.e., latches) serve as memory
elements in asynchronous sequential circuits.

What is Latch ?

Latch is an electronic device, which changes its output immediately based on the applied input. It
is used to store either 1 or 0 at any specified time. It consists of two inputs namely “SET” and
RESET and two outputs, which are complement to each other.
Different Types of Flip-Flops

S-R Flip Flop

This stands for Set-Reset Flip Flop. It has two inputs: Set (S) and Reset (R), and two outputs: Q
and Q’ (not Q). When S is turned on, the output Q becomes 1. When R is turned on, Q becomes
0. If both S and R are 0, the flip-flop keeps its last state. However, having both S and R as 1 at
the same time is usually avoided because it can lead to unpredictable behavior.

J-K Flip Flop

This flip-flop is like an improved S-R flip-flop. It has two inputs, J and K, and two outputs, Q
and Q’. When J is 1 and K is 0, the output becomes 1. When J is 0 and K is 1, the output
becomes 0. If both J and K are 0, it keeps its previous state. The special feature is when both J
and K are 1 – this makes the flip-flop switch its state, turning 1 to 0 or 0 to 1.

It is one kind of sequential logic circuit which stores binary information in bitwise manner. It
consists of two inputs and two outputs. Inputs are Set(J) & Reset(K) and their corresponding
outputs are Q and Q’. JK flipflop has two modes of operation which are synchronous mode and
asynchronous mode. In synchronous mode, the state will be changed with the clock(clk) signal,
and in asynchronous mode, the change of state is independent from its clock signal. Let’s see its
diagram structure.
The JK flip flop diagram above represents the basic structure which consists of Clock (CLK),
Clear (CLR), and Preset (PR).

Below is the circuit diagram of JK Flip Flop. Two 3-input NAND gates are used in place of the
original two 2-input AND gates. The outputs at Q and Q’ are coupled to each gate’s third input.
Since the two inputs are now interlocked, the SR flip-flop’s cross-coupling enables the
previously invalid condition of (S = “1”, R = “1”) to be employed to perform the “toggle action”.
In a circuit “set”, the bottom NAND gate interrupts the J input coming from the “0” position of
Q’. In the “RESET” state, the top NAND gate interrupts the K input coming from the 0 positions
of Q. We can use Q and Q’ to control the input because they are always different. The flip flop is
toggled according to the truth table when both inputs “J” and “K” are set to 1.

Truth Table of JK FLIP FLOP

In a circuit “set”, the bottom NAND gate interrupts the J input coming from the “0” position of
Q’. In the “RESET” state, the top NAND gate interrupts the K input coming from the 0 positions
of Q. We can use Q and Q’ to control the input because they are always different. The flip flop is
toggled according to the truth table when both inputs “J” and “K” are set to 1.
A JK flip-flop is a kind of sequential logic circuit that keeps track of binary data. Its
characteristic table shows how the output (Qn+1) changes using inputs (J & K) along with the
last state (Qn).

Let’s break down the characteristic table. There are four states to understand:

1. J = 0, K = 0 (No Change): Here, the output Q(n+1) stays the same. This means the next
state (Q(n+1)) is just like the current one (Qn).

2. J = 0, K = 1 (Reset State): In this case, the next state is reset to 0 (Q(n+1) = 0), no matter
what the current state is (Qn).

3. J = 1, K = 0 (Set State): Now, the next state gets set to 1 (Q(n+1) = 1), again, no matter
what’s happening in the current state (Qn).
 4. J = 1, K = 1 (Toggle State): In this state, the output Q(n+1) toggles. So if the current state
is set (Qn = 1), it will change to 0 (Q(n+1) = 0). If it’s reset (Qn = 0), then it flips to 1
(Q(n+1) = 1).

T Flip Flop

The T stands for “Toggle.” This flip-flop has one input T and two outputs Q and Q’. When T is
0, nothing changes. But when T is 1, the flip-flop switches its state. If Q was 1, it becomes 0, and
if it was 0, it becomes 1. This is useful for making counters or dividing frequencies in digital
circuits.

Applications of JK Flip-Flop

 Counters: Counters are very essential components for the application of frequency
dividers and event sequencers where there is a need of storing and propagating the count
value. We can design binary synchronous and asynchronous counters using JK-flipflop.

 Shift Registers: For data storage and manipulation, serial-to-parallel or parallel-to-serial

data conversion the shift registers are widely used. Registers can store and shift the
binary data in a sequential manner. We can design it by JK-flipflops.

 Memory Units: JK-flipflop itself act as a memory unit to store binary information. By
making a sequential chain of JK-flipflops we can use it even as RAM.

Advantages of JK Flip-Flop

 Versatility: As discussed above, JK-flipflops can be used as a basic memory element or

a primary building block of further complex memory design. It is very much adaptive as
it can be operated in both synchronous and asynchronous modes.

 Toggle Functionality: The application which are required to get output as its
complement of input that also can be developed by JK-flipflops as when J=K=1 it
triggers toggle state which gives output which is complement with it’s each clock pulse.
  Error Detection and Correction: We can use a complex circuit built by JK-flipflops
which can detect and correct information during data-transmission.

Disadvantages of JK Flip-Flop

 Complexity: Compared to other types of flipflops(D,T, SR), JK flipflop requires

additional logic gates to implement which consumes extra memory resources and
increases complexity to operate.

 Propagation Delay: This is the major problem present in JK-FF. Propagation delay
results a timing delay in certain application which are time-flow sensitive.

 Race Problem: This issue arises when the clock input’s timing pulse isn’t given enough
time to turn “Off” before the output Q’s state is altered.

D Flip Flop

The D stands for “Data” or “Delay.” It has one input D and two outputs Q and Q’. This flip-flop
is simpler to use. Whatever value is on the D input (0 or 1) gets copied to the Q output when the
flip-flop is triggered. It’s often used to store data briefly or to synchronize signals in digital
systems.

D flip flop is an electronic devices that is known as “delay flip flop” or “data flip flop” which is
used to store single bit of data.

 D flip flops can be either synchronous or asynchronous.

 The clock signal is required for the synchronous version of D flip flops but not for the
asynchronous one.

 The D flip flop has two inputs, data and clock input which controls the flip flop.

 When clock input is high, the data is transferred to the output of the flip flop.

 When the clock input is low, the output of the flip flop is held in its previous state.
Block Diagram of D Flip Flop

A D flip-flop is created by modifying an SR flip-flop. The S input is connected to the D input,

and the R input is connected to the inverted D input. As a result, a D flip-flop functions similarly
to an SR flip-flop, but with complementary inputs, preventing any possibility of an invalid
intermediate state. One major issue with the SR flip-flop is the race around condition, which is
eliminated in the D flip-flop due to the inverted inputs. The circuit diagram of the D flip-flop is
shown

Working of D Flip Flop

D flip flop consist of a single input D and two outputs (Q and Q’). The basic working of D Flip
Flop is as follows:

 When the clock signal is low, the flip flop holds its current state and ignores the D input.
  When the clock signal is high, the flip flop samples and stores D input.

 The value that was previously fed into the D input is reflected at the flip flop’s Q output.
o If D = 0 then Q will be 0.
o If D = 1 then Q will be 1.

 The Q’ output of the flip flop is complemented by the Q output.

o If Q = 0 then Q’ will be 1.
o If Q = 1 then Q’ will be 0.

Advantages of D Flip Flop

 D flip flop is very simple to design.

 The computation speed of D flip flop is very fast compared to other flip flops.

 D flip flop requires very few components to design which makes it simple to understand.

Note: D flip flops are glitch prone. When input varies fast, flip flop output may glitch. Digital
circuit glitches are hard to identify and fix.

Application of D Flip Flop

D flip flop has numerous applications in digital system is described as follows:

 Memory: D flip flop is used to create memory circuit for holding the data.

 Registers: D flip flop is used to create register, which can hold data in digital system. By
using the D flip flop the designer can built any size of register as per the requirement.

 Counters: D flip flops are used to create the counters which counts the number of event
occurred in the digital system.

 Synchronous System: D flip flop is having in developing the synchronous system.

Difference Between Flip-Flop and Latch

Given Below are the Difference Between Flip-Flop and Latch

Flip-Flop Latch
Flip-flop is a bistable device i.e., it has two stable Latch is also a bistable device whose states
states that are represented as 0 and 1. are also represented as 0 and 1.
It checks the inputs but changes the output only at It checks the inputs continuously and
times defined by the clock signal or any other responds to the changes in inputs
control signal. immediately.
It is a edge triggered device. It is a level triggered device.
Gates like NOR, NOT, AND, NAND are building
These are also made up of gates.
blocks of flip flops.
They are classified into asynchronous or
There is no such classification in latches
synchronous flipflops.
These can be used for the designing of
It forms the building blocks of many sequential
sequential circuits but are not generally
circuits like counters.
preferred.
Flip-flop always have a clock signal Latches doesn’t have a clock signal
Flip-flop can be build from Latches Latches can be build from gates
ex:D Flip-flop, JK Flip-flop ex:SR Latch, D Latch