Controller Area Network (CAN) Standard

Embedded Systems CMP 445 Spring 2011 Computer Engineering Cairo University

Outline
Introduction
Brief History Design Objectives CAN Architecture

Basic Concepts

Brief History
1986 CAN v1.0 by Robert Bosch GmbH. 1991 CAN v2.0 by Bosch. 1993 ISO 11898 CAN 1993 Mercedes S-class first car with CAN 2003 ISO 11898-1, 11898-2 revised CAN with physical layer characteristics 2008 US OBD-II automotive diagnostic standard mandates use of CAN

Design Objectives
Reliable communication
To deal with bit errors

Fault tolerance
To deal with hardware faults

Low development cost

Low cost components, interconnect, and programming

Data rates up to 1Mbps (a big deal in the 1980s) Expandability

Open systems, nodes can be added with no reconfiguration cost

ISO 11898: Architecture

Transceiver implements most of the PhL Controller implements Phy signaling and DLL Controller can be integrated or separate Application is not part of the standard

Physical CAN Bus Connection

CAN is designed for data communication over a short distance. CAN protocol does not specify what medium to use for data communication. Using a shielded or unshielded cable is recommended for a short distance communication. A typical CAN bus setup using a cable is shown.
node 1
CAN_H

node 2

node 3

node n

RT (120

RT = 120
CAN_L

A typical CAN bus setup using cable

The Physical Layer

Physical signal specifications
Electrical specifications Bit encoding Bit timing Bit synchronization

The Data-Link Layer

Logical Link Control
Message acceptance filtering Overload notification (flow control) Error recovery management

Medium Access Control

Message framing Arbitration Error detection Frame coding (Bit-stuffing)

Basic Concepts
Acceptance Filtering Bus Arbitration Bit Synchronization Error Detection and Signaling Fault Confinement Bus Length vs. Bit Rate

Acceptance Filtering

Broadcast system: all nodes can hear a transmission To avoid wasting processing power listening to uninteresting transmissions
Nodes implement a filter, to pass on messages based on their identification which usually represent their content all other messages are ignored.

Bus Arbitration
Physical Characteristics
NRZ Coding Scheme Differential Signaling

CSMA Collision Detection Contention Resolution

NRZ Coding
Non-Return-to-Zero NRZ encoding scheme
0 and 1 are encoded as a voltage levels A transition in signal level occurs only when a 0 is followed by 1 or vice-versa.

Differential Signaling
1 encoded as recessive 0 encoded as dominant

CSMA
Carrier Sense Multi-Access Every node must sense the channel and make sure it is idle for a minimum period of time (intermission period) before starting a frame transmission. Avoids collision with on-going transmissions Problem: if two node start transmitting at the exact same time

Collision Detection
CAN bus behaves like an AND gate. If any node writes a dominant bit 0, the bus will have a dominant state 0. Otherwise, the bus will have a recessive state 1. Each transmitting node samples the bus during each bit. If written sampled, a collision is detected

Contention Resolution
Frame starts with an 11-bit id field transmitted most significant bit first A node detecting a collision (bus dominant while transmitting recessive) stops Messages with low binary value id win Losing node retries after bus is idle

Synchronization
No global clock signal, nodes use local oscillators Local bit time vary slightly from nominal bit time Periodic errors accumulate and synch is lost

Synchronization Mechanism
A receiver synchronizes to the transmitter clock by detecting transitions and compensating local clock Hard synchronization with first recessive-to-dominant edge (=dominant Start Of Frame (SOF)bit) after bus idle Continuous re-synchronization at every recessive-todominant edge transition

Bit Stuffing
NRZ has not enough edges for resynchronization After 5 consecutive bits with same polarity (dominant or recessive), a bit with complementary polarity will be inserted Receiver filters the complementary bit away

Nominal Bit Time

The inverse of the nominal bit rate is the nominal bit time. A nominal bit time is divided into four segments
Nominal bit time

sync_seg

prop_seg

phase_seg1

phase_seg2

Sample point

sync_seg Segment
A synchronized receiver expects a falling edge transition to occur only within this segment. When the receiver is slower the falling edge will tend to occur earlier in phase_seg2 of the previous bit time. When the receiver is faster the falling edge will tend to occur later in the prop_seg or phase_seg1 of the same bit time.

prop_seg Segment
Equals twice the sum of the signals propagation time on the CAN bus line, the input comparator delay, and the output driver delay. A transmitter expects acknowledgement bit to arrive from a synchronized receiver right after prop_seg

CAN Message Bit Timing

Clock of receiver B is shifted by prop_seg/2 Acknowledgement bit will arrive right after prop_seg The sampling must occur within the remaining phase segments

phase_seg1 and phase_seg2

Used for compensating for edge phase errors phase_seg1 can be lengthened to compensate for a fast receiver, when an edge occurs after the sync_seg and before the sample point phase_seg2 can be shortened to compensate for a slow receiver, when an edge occurs after the sample point and before the sync_seg of the next bit

Sample Point
At the end of phase_seg1 segment. Users can choose to take three samples instead of one.
A majority function determines the bit value when three samples are taken. Each sample is separated by half time quantum from the next sample.

The time spent on determining the bit value is the information processing time.

Time Quantum (TQ)

A fixed time unit for measuring the length of segments within the bit time
sync_seg = 1 TQ 1 TQ prop_seg 8 TQ 1 TQ phase_seg1 8 TQ max(phase_seg1, IPT) phase_seg2 8

Derived from local oscillator by division over a prescale value

Resynchronization Jump Width

The maximum amount by which phase_seg1 can be lengthened (in case of fast receiver) or phase_seg2 can be shortened (in case of slow receiver). 1 TQ SJW min(4, phase_seg1) TQ

Bus Length vs. Signaling Rate

The nominal bit time should be long enough to allow the signal has to propagate to the most remote node and back again (round trip) before the bit is sampled Propagation velocity (0.10.2 m/ns); depends on cable and node impedance Further consideration include: transceiver delay, sample time tolerance, etc.
Bus Length (m) 40 100 200 500 1000 Signaling Rate (Kbps) 1000 500 250 100 50

<

Setting the CAN Timing Parameters

Nominal bit time (NBT)
The worst-case value for tPROP_SEG is
NBT = 1 / bitrate (1) (2) (3) tPROP_SEG = 2 (tBUS + tTX + tRX)

In units of time quantum,

In the absence of bus errors, bit stuffing guarantees a maximum 12-bit between resynchronization edges. The accumulated phase errors are due to the tolerance in the CAN system clock. This requirement can be expressed as (2 f) 12 NBT < tSJW (4) where, f is the largest absolute relative error in oscillator frequency (usu. < 0.5%)

prop_seg = round_up (tPROP_SEG TQ)

Procedure for Determining the Optimum Bit Timing Parameters

1. Determine the NBT = 1/bitrate (eq. 1) 2. Determine the minimum tPROP_SEG (eq. 2) 3. Choose a prescale factor to generate the CAN system clock frequency. The chosen clock frequency must make the NBT an integral multiple of TQ, where 8 NBT/TQ 25 4. Calculate the prop_seg duration (eq. 3) If the resultant value is greater than 8, go back to Step 3 and choose a lower CAN system clock frequency.

Procedure for Determining the Optimum Bit Timing Parameters

5. phase_seg1 + phase_seg2 = (NBT/TQ) - (prop_seg value+1)
If < ceil(IPT/TO) +1 , go back to Step 3 and select a higher CAN system clock frequency.

6. Determine phase_seg1 and phase_seg2 to satisfy the following constraints

8 phase_seg1 1 8 phase_seg2 max( ceil(IPT/TQ), phase_seg1) To maximize SJW, phase_seg2 = phase_seg1 or phase_seg1+1

7. Determine the resynchronization jump width (SJW)

SJW = min (4, phase_seg1)

8. Calculate the oscillator tolerance (eq. 4).

Example: Problem
Calculate the CAN bit segments for the following constraints:
Bit rate = 1 Mbps Bus length = 25 m Bus propagation delay = 5 10-9 sec/m Output driver plus input comparator propagation delay = 150 ns at 85oC CPU oscillator frequency = 24 MHz IPT = 2 TQ

Find the oscillator frequency error tolerance

Example: Solution
1. 2.
3. 4. 5. 6. 7. 8.

NBT = 1/1 Mbps = 1 s Physical delay of the CAN bus = 25 5 = 125 ns tPROP_SEG = 2 (125 + 150) = 550 ns A prescaler of 1 for 24 MHz gives a time quantum of 41.67 ns. Prop_seg = round_up (550 ns 41.67) = 14 > 8. Set prescaler to 2. Then one time quantum is 83.33 ns and one bit time is 12 time quanta. The new prop_seg = 7. NBT prop_seg1 sync_seg = 12 7 1 = 4. phase_seg1 = 2, phase_seg2 = 4 phase_seg1 phase_seg2 = 2 SJW = min (4, phase_seg1) SJW = 2 f < SJW (2 12 NBT) = 2 (2 12 12) = 0.69% The oscillator tolerance is 0.69%.

 Example 13.2 Calculate the CAN bit segments for the following constraints: Bit rate = 500 Kbps Bus length = 50 m Bus propagation delay = 5 10-9 sec/m CAN transceiver plus receiver propagation delay = 150 ns at 85oC CPU oscillator frequency = 16 MHz Solution: Step 1 Physical delay of the bus = 50 5 10-9 sec/m = 250 ns tPROP_SEG = 2 (250 + 150) = 800 ns Step 2 Use 2 as the prescaler. The resultant TQ is 125 ns. A normal bit time is 2 ms. Quanta per bit = 2,000 /125 = 16 Step 3 Prop_seg = round_up (800 125) = 7. Step 4 Subtract 7 and 1 from 16 time quanta per bit gives 8. Since this number is even and greater than 4, divide it by 2 and assign it to phase_seg1 and phase_seg2.

 Step 5 RJW = min (4, phase_seg1) = 4 Step 6 From equation 13.6, f < RJW (2 12 NBT) = 4 (24 16) = 1.04%

In summary,
Prescaler Nominal bit time Prop_seg Sync_seg Phase_seg1 Phase_seg2 RJW Oscillator tolerance =2 = 16 =7 =1 =4 =4 =4 = 1.04%

CAN DLL Protocol

Types of CAN Messages Frame Format

Types of CAN Messages (1 of 2)

Data frame Remote frame Error frame Overload frame

Types of CAN Messages (2 of 2)

Two states of CAN bus
Recessive: high or logic 1 Dominant: low or logic 0

Data Frame
A data frame consists of seven fields: start-offrame, arbitration, control, data, CRC, ACK, and end-of-frame.
Interframe space or overload frame

Interframe space Start of Arbitration Control frame field field

Data Frame

Data field CAN Data frame

CRC field

ACK field

End of frame

Start of Frame
A single dominant bit to mark the beginning of a data frame. All nodes have to synchronize to the leading edge caused by this field.

Arbitration Field
There are two formats for this field: standard format and extended format.
Interframe space Start of frame (a) standard format Arbitration field Start of frame Control field r1 DLC Arbitration field 11 bit Identifier RTR Control field IDE r0 DLC

11-bit identifier SRR IDE 18-bit identifier RTR r0

(b) extended format

The identifier of the standard format corresponds to the base ID in the extended format. The RTR bit is the remote transmission request and must be 0 in a data frame. The SRR bit is the substitute remote request and is recessive. The IDE field indicates whether the identifier is extended and should be recessive in the extended format. The extended format also contains the 18-bit extended identifier.

Control Field
Contents are shown in figure 13.4. The first bit is IDE bit for the standard format but is used as reserved bit r1 in extended format. r0 is reserved bit. DLC3DLC0 stands for data length and can be from 0000 (0) to 1000 (8).
Arbitration field IDE/r1 r0 Control Field Data field or CRC field DLC1 DLC0 DLC3 DLC2

reserved bits

Data length code

Figure 13.4 Control field

Data Field
May contain 0 to 8 bytes of data

CRC Field
It contains the 16-bit CRC sequence and a CRC delimiter. The CRC delimiter is a single recessive bit.
Data or Control field CRC field ACK

CRC sequence Figure 13.5 CRC field

CRC delimiter

ACK Field
Consists of two bits The first bit is the acknowledgement bit.
This bit is set to recessive by the transmitter, but will be reset to dominant if a receiver acknowledges the data frame.

The second bit is the ACK delimiter and is recessive.

Remote Frame
Used by a node to request other nodes to send certain type of messages Has six fields as shown in Figure 13.7
These fields are identical to those of a data frame with the exception that the RTR bit in the arbitration field is recessive in the remote frame.
Interframe space Start of frame Remote frame Interframe space or overload frame arbitration Control field field CRC field ACK field End of frame

Figure 13.7 Remote frame

Error Frame
This frame consists of two fields.
The first field is given by the superposition of error flags contributed from different nodes. The second field is the error delimiter.

Error flag can be either active-error flag or passive-error flag.

Active error flag consists of six consecutive dominant bits. Passive error flag consists of six consecutive recessive bits.

The error delimiter consists of eight recessive bits.

Data frame Interframe space or Overload frame error delimiter

Error frame

error flag Superposition of error flags

Figure 13.8 Error frame

Overload Frame
Consists of two bit fields: overload flag and overload delimiter Three different overload conditions lead to the transmission of the overload frame:
Internal conditions of a receiver require a delay of the next data frame or remote frame. At least one node detects a dominant bit during intermission. A CAN node samples a dominant bit at the eighth bit (i.e., the last bit) of an error delimiter or overload delimiter.

Format of the overload frame is shown in Figure 13.9. The overload flag consists of six dominant bits. The overload delimiter consists of eight recessive bits.
End of frame or Error demiliter or Overload delimiter Overload flag Superposition of overload flags Figure 13.9 Overload frame Overload frame Overload delimiter Interframe space or Overload frame

Interframe Space (1 of 2)

Data frames and remote frames are separated from preceding frames by the interframe space. Overload frames and error frames are not preceded by an interframe space (higher priority)

Frame

Interframe space

Frame

Intermission

bus idle

Interframe space for non error-passive nodes or receiver of previous message

Interframe Space (2 of 2)
The intermission subfield consists of three recessive bits. During intermission no node is allowed to start transmission of the data frame or remote frame. The period of bus idle may be of arbitrary length. After an error-passive node has transmitted a frame, it sends eight recessive bits following intermission (lower priority), before starting to transmit a new message or recognizing the bus as idle.
Interframe space Suspend Transmission Frame Bus Idle

Frame Intermission

Interframe space for error-passive nodes

Bit Stream Encoding

The frame segments including start-of-frame, arbitration field, control field, data field, and CRC sequence are encoded by bit stuffing. Whenever a transmitter detects five consecutive bits of identical value in the bit stream to be transmitted, it inserts a complementary bit in the actual transmitted bit stream. The remaining bit fields of the data frame or remote frame (CRC delimiter, ACK field and end of frame) are of fixed form and not stuffed. The error frame and overload frame are also of fixed form and are not encoded by the method of bit stuffing. The bit stream in a message is encoded using the non-return-to-zero (NRZ) method. In the non-return-to-zero encoding method, a bit is either recessive or dominant.

Errors (1 of 3)
Error handling
CAN recognizes five types of errors.

Bit error
A node that is sending a bit on the bus also monitors the bus. When the bit value monitored is different from the bit value being sent, the node interprets the situation as an error. There are two exceptions to this rule:
A node that sends a recessive bit during the stuffed bit-stream of the arbitration field or during the ACK slot detects a dominant bit. A transmitter that sends a passive-error flag detects a dominant bit.

Errors (2 of 3)
Stuff error
Six consecutive dominant or six consecutive recessive levels occurs in a message field.

CRC error
CRC sequence in the transmitted message consists of the result of the CRC calculation by the transmitter. The receiver recalculates the CRC sequence using the same method but resulted in a different value. This is detected as a CRC error.

Errors (3 of 3)
Form error
Detected when a fixed-form bit field contains one or more illegal bits

Acknowledgement error
Detected whenever the transmitter does not monitor a dominant bit in the ACK slot

Error Signaling
A node that detects an error condition and signals the error by transmitting an error flag
An error-active node will transmit an active-error flag. An error-passive node will transmit a passive-error flag.

Fault Confinement
A node may be in one of the three states: error-active, errorpassive, and bus-off. A node keeps count of receive and transmit errors (REC, TEC) An error-active node will transmit an active-error frame (dominant) when detecting an error. An error-passive node will transmit a passive-error frame (recessive) when detecting an error. A bus-off node is not allowed to take part in bus communication.