North South University

Department of Electrical & Computer Engineering

LAB REPORT
Course Name: CSE231L
Experiment Number: 7

Experiment Name: LAB-07-A: Introduction to Flip-Flops and Shift Registers

LAB-7B: BCD to Seven Segment Decoder

Experiment Date: 27/12/2020

Report Submission Date: 04/01/2021
Section: 3

Student Name: Zahid Hasan Score

Student ID: 1911509

Remarks:
 LAB-07-A: Introduction to Flip-Flops and Shift Registers
Objectives:
• Learn about the concept of states in digital logic and how Flip-Flop circuits can
be used to store state information.
• Understand the internal logic of J-K Flip-Flops and implement one using basic
logic gates.
• Understand the relationship between J-K, T and D Flip-Flops and observe the
characteristics of all three.
• Implement a shift register using D Flip-Flops and analyze its operation.

Apparatus:

• Trainer board
• 1 x IC 7402 2-input NOR gates
• 1 x IC 7411 3-input AND gates
• 1 x IC 7404 Hex Inverter (NOT gates)
• 2 x IC 7474 (D Flip-Flop)

Theory:
Flip-Flop:
A flip flop is an electronic circuit with two stable states that can be used to store
binary data. The stored data can be changed by applying varying inputs. Flip-
flops and latches are fundamental building blocks of digital electronics systems
used in computers, communications, and many other types of systems. Flip-
flops and latches are used as data storage elements. It is the basic storage
element in sequential logic. The basic unit for storage is flip flop. A flip-flop
maintains its output state either at 1 or 0 until directed by an input signal to
change its state.
D Flip-Flop:
D flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas, D latch operates with enable signal. That means, the output of D flip-flop is
insensitive to the changes in the input, D except for active transition of the clock signal.
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0,
the output is reset.
 Figure: D flip-flop using JK flip-flop
T Flip-Flop
T flip-flop is the simplified version of JK flip-flop. It is obtained by connecting the
same input ‘T’ to both inputs of JK flip-flop. It operates with only positive clock
transitions or negative clock transitions. When T=0 there is no change in the
output. When T=1 the output switch to the complement state (ie) the output
toggles.

Figure: T flip-flop using JK flip-flop

JK Flip-Flop:
JK flip-flop is the modified version of SR flip-flop. It operates with only positive
clock transitions or negative clock transitions. This circuit of JK Flip-Flop has
two inputs J & K and two outputs Q(t) & Q(t)’.
When K input is low and J input is high the Q output of flip-flop is set.
When K input is high and J input is low the Q output of flip-flop is reset.
When both the inputs K and J are low the output does not change
When both the inputs K and J are high it is possible to set or reset the Flip-flop
and the output toggle on the next positive clock edge.
Registers:
In order to store multiple bits of information, we require multiple flip-flops. The
group of flip-flops, which are used to hold (store) the binary data is known as
register. The register is used to perform different types of operations. For
performing the operations, the CPU use these registers. The faded inputs to the
system will store into the registers. The result returned by the system will store
in the registers.

Figure: Right Shift Register using D flip-flops

Circuit Diagram:

Figure F1: Constructing a Master slave JK Flip-Flop using AND and NOR gates.
Data Table:
Experiment-1:
Table 01: J-K Flip-Flop using AND and NOR gates.

J K Q Q’

1 0 1 0

0 0 1 0

0 1 0 1

0 0 0 1

1 1 1 0

1 0 1 0

1 0 1 0

1 1 0 1

Experiment-2:
Table 02: T and D Flip-Flops using J-K Flip-Flops.

T Q D Q
0 No Change 0 0

1 Toggle 1 1

Table F.2.1 Table F.2.2

Table 03: Right shift register using D Flip-Flops.

 States Input Output

Initial State X XXXX

T1 1 1XXX
T2 0 01XX
T3 1 101X
T4 0 0101

Question and Answer:

Experiment-2:
Difference between T and D Flip-Flops.
ANS:
T Flip-Flop D Flip-Flop
T stands for toggle D stands for data
T Flip-Flop is a one terminal D Flip-Flop is a one terminal
combination of JK Flip-Flop combination of SR flipflop
T Flip-Flop which gives toggles output D Flip-Flop is a data flipflop which
for input 1;and it stores 0 for input 1 store either 0 or 1 when inout 0 or 1;
which mean what ever the input ; the
output is same as input(stores)
Experiment-3:
Q-01: Why we need shift registers
ANS:
Shift Registers are used for data storage or for the movement of data and are
therefore commonly used inside calculators or computers to store data such as
two binary numbers before they are added together, or to convert the data
from either a serial to parallel or parallel to serial format.
Shift register is used as Parallel to serial converter, which converts the parallel
data into serial data. It is utilized at the transmitter section after Analog to
Digital Converter ADC block.
Shift register is used as Serial to parallel converter, which converts the serial
data into parallel data. It is utilized at the receiver section before Digital to
Analog Converter DAC block.
Shift register along with some additional gates generate the sequence of zeros
and ones. Hence, it is used as sequence generator.
Shift registers are also used as counters. There are two types of counters based
on the type of output from right most D flip-flop is connected to the serial
input. Those are Ring counter and Johnson Ring counter.
Q-02: If the output of last D Flip-Flop is connected to the input of first one.
ANS:
If the output of last D Flip-Flop is connected to the input of the first one then the data
stored in the register will shift in a circle.

Discussion:
The overall lab experiment was about the internal structure of different flip-flops and
implementation of shift register using flip-flops.
At the beginning of the experiment, I constructed the Master-Slave JK Flip-Flop using
AND, OR and NOR gates. As well as I designed of it.
Using JK Flip-Flop IC, I also constructed the D flip-flop IC and T flip-flop IC. For D flip-
flop IC, one input line is from D input and other input line is from negation of D input.
For T flip-flop IC, both input lines are from T input.
As a last experiment, I constructed the right shift register using D flip-flop. It was Serial
In-Serial Out(SISO) Shift Register. Constructed Shift Register consists of four D flip-
flops, which are cascaded. That means, output of one D flip-flop is connected as the
input of next D flip-flop. All these flip-flops are synchronous with each other since, the
same clock signal is applied to each one.
During experiment, Logisim stopped working itself. So I had to restart iit.
Above all, from the experiment, I learned about the internal circuit structure of
different types of flip-flops and constructing shift register using flip-flop.
 LAB-7B: BCD to Seven Segment Decoder (0-15)
Objectives:
• We have to learn about various applications of decoder.
• We have to learn and understand the working of IC 7447.
• We have to learn about types of seven-segment display.

Equipment:

• Trainer board
• IC 7447, resistors, seven segment display
• Wires for connection

Theory:
A Digital Decoder IC, is a device which converts one digital format into another
and one of the most commonly used devices for doing this is called the Binary
Coded Decimal (BCD) to 7-Segment Display Decoder.
7-segment LED (Light Emitting Diode) or LCD (Liquid Crystal Display) type
displays, provide a very convenient way of displaying information or digital
data in the form of numbers, letters or even alpha-numerical characters.
Typically 7-segment displays consist of seven individual colored LED’s (called
the segments), within one single display package. In order to produce the
required numbers or HEX characters from 0 to 9 and A to F respectively, on the
display the correct combination of LED segments need to be illuminated and
BCD to 7-segment Display Decoders such as the 74LS47 do just that.
A Binary Coded Decimal (BCD) to 7-Segment Display Decoder such as the TTL 74LS47
or 74LS48, have 4 BCD inputs and 7 output lines, one for each LED segment. This allows
a smaller 4-bit binary number (half a byte) to be used to display all the denary numbers
from 0 to 9 and by adding two displays together, a full range of numbers from 00 to
99 can be displayed with just a single byte of eight data bits.
Circuit Diagram:

Figure: Displaying 0,5,12(C) by BCD to Seven Segment Decoder

Data Table:
Decimal Inputs output

D C B A a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

1 0 0 0 1 0 1 1 0 0 0 0

2 0 0 1 0 1 1 0 1 1 0 1

3 0 0 1 1 1 1 1 1 0 0 1

4 0 1 0 0 0 1 1 0 0 1 1

5 0 1 0 1 1 0 1 1 0 1 1

6 0 1 1 0 1 0 1 1 1 1 1

7 0 1 1 1 1 1 1 0 0 0 0

8 1 0 0 0 1 1 1 1 1 1 1

9 1 0 0 1 1 1 1 1 0 1 1

10 1 0 1 0 1 1 1 0 1 1 1

11 1 0 1 1 0 0 1 1 1 1 1

12 1 1 0 0 1 0 0 1 1 1 0

13 1 1 0 1 0 1 1 1 1 0 1

14 1 1 1 0 1 0 0 1 1 1 1

15 1 1 1 1 1 0 0 0 1 1 1

Task: Draw logic circuit diagram for the above truth table using 4 variable K-map Result will show as
Decimal numbers 0-9 and then A-F for (10-15) total 16 digits in 0-F serial order.
 Show your work on the K-Map and Functions Here Below.

For a: for b: for c:

1 0 1 1 1 1 1 1 1 1 1 0

1 0 1 1 1 0 1 0 1 1 1 1

1 0 1 1 0 1 0 0 0 1 0 0

1 1 1 1 1 1 0 1 1 1 1 1

For d: for e: for f:

1 0 1 1 1 0 0 1 1 0 0 0
0 1 0 1 0 0 0 1 1 1 0 1
1 1 0 1 1 1 1 1 1 0 1 1
1 1 1 0 1 0 1 1 1 1 1 1

For g:
0 0 1 1
1 1 0 1
0 1 1 1
1 1 1 1

Write down the Boolean Functions for each K map

a = D’CA+DC’B’+C’A’+DA’+D’B+CB
b = D’B’A’+D’BA+DB’A+C’A+D’C’
c = DC’+D’C+D’B’+D’A+B’A
d = CBA’+D’C’A’+C’BA+CB’A+DB’
e = BA’+DC+C’A’+DB
f = D’CB’+DC’+B’A’+CA’+DB
g = D’CB’+DC’+BA’+C’B+DA
Discussion:
The overall lab experiment was about the construction of BCD to Seven Segment
Decoder. This will show 0 to 15. For 10 to 15, it will show A, b, C, d, E, F respectively.
At the beginning of the experiment, I had to complete the data table with the values
of input lines A, B, C, D and output lines a, b, c, d, e, f, g.
Then for every output line, I had to find out the Boolean function using Karnaugh
map.
With the help of AND and OR logic gates, I designed the logic circuits for BCD to
Seven Segment Decoder as well as IC diagram. This decoder worked properly and
showed the outputs perfectly.
During experiment, Logisim worked perfectly.
From the experiment, I learned about the internal structure of the seven segment
display.