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Systematic design of three-stage op-amps using split-length compensation

Conference Paper in Midwest Symposium on Circuits and Systems · September 2011

DOI: 10.1109/MWSCAS.2011.6026314 · Source: IEEE Xplore

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 1

Systematic Design of Three-Stage Op-amps using

Split-Length Compensation
Vishal Saxena, Sakkarapani Balagopal and R. Jacob Baker
Electrical and Computer Engineering Department, Boise State University
Boise, ID 83725-2075.
Email: {vishalsaxena, sakkarapanibalagopal, jbaker}@boisestate.edu

Abstract—Over the past decade CMOS technology has been

continuously scaling which has resulted in sustained improvement
in transistor speeds. However, the transistor threshold voltages 1

do not decrease at the same rate as the supply voltage (VDD ). 1 2

1

Besides, the open-loop gain available from the transistors is 1 2

2
diminishing. This trend renders the traditional techniques, like
2
cascoding and gain boosting, less useful for achieving high DC
gain in nano-scale CMOS processes. Thus, horizontal cascading
(multi-stage) must be used in order to realize high-gain op-amps Figure 1. Illustration of the split-length NMOS and PMOS devices and the
in low-VDD processes. This paper presents a design procedure low-impedance nodes [4].
for op-amp design using split-length compensation. A reversed-
nested split-length compensated (RSLC) topology, employing
double pole-zero cancellation, is illustrated for the design of three-
stage op-amps. The RSLC topology is then extended to the design half plane (RHP) zero (which degrades the phase), and thus
of three-stage fully-differential op-amps. enhance the phase margin [3]. In nano-CMOS processes low-
Index Terms—CMOS Amplifiers, fully-differential, nano- voltage, high-speed op-amps can be designed by employing a
CMOS, Op-amp compensation, split-length, three-stage op-amps. split-length composite transistor for compensation instead of
using a common-gate transistor in the cascode stack [4]. Fig.
1 illustrates the splitting of an n-channel MOSFET (NMOS)
or a p-channel MOSFET (PMOS) to create a low impedance
I. I NTRODUCTION
internal node-A [4].

O PERATIONAL Amplifiers are an essential component

in the modern mixed-signal systems. They are utilized
in wide variety of circuits including data-converters, filters,
In two-stage op-amps employing split-length compensation,
pole splitting is achieved with a lower value of the compen-
sation capacitor (Cc ) and with a lower value of second-stage
voltage references and power management circuits. However, transconductance (gm2 ). This results in a much larger unity
continued scaling in CMOS processes has continuously chal- gain frequency (ωun ) attainable by the op-amp, with lower
lenged the established paradigms for operational amplifier (op- power consumption and a smaller layout, when compared to
amp) design. As the feature size of CMOS devices scales, the Miller compensated op-amps [4].
creating faster transistors, the supply voltage (VDD ) is reduced.
The higher speed due to CMOS scaling comes at a price of
III. S PLIT LENGTH COMPENSATION OF T HREE S TAGE
the reduction in transistor’s open-loop gain (gm .ro ). Further
O PAMPS
with device scaling, the threshold voltage of transistors doesn’t
scale well with VDD , resulting in lower headroom for analog Continued interest in the three-stage op-amp design has seen
design. In addition to these challenges, the process variations numerous three-stage op-amp design techniques [5], [6], [7].
become more pronounced leading to significant offsets in However, they exhibit either complex implementation or larger
op-amps due to the device mismatch [1], [2]. In order to power consumption when compared to the commonly used
meet the gain requirements of op-amp in nanoscale CMOS two-stage op-amps. This section provides a tutorial on the
processes and low supply voltage, three or higher stage op-amp design techniques, introduced by the author in [8], [9], which
topologies have become important. In this paper, we present a result in high-speed and low power three-stage op-amps.
systematic design methodology for split-length compensated
low-voltage three-stage op-amps. A. Multi-Stage Op-amp Biasing
Biasing is an important concern when designing multi-stage
II. S PLIT L ENGTH C OMPENSATION op-amps. If all the gain stages of the multi-stage op-amp are
It is well known that if the compensation current from not biased adequately with the intended overdrive voltages, the
the output node is fed back to the internal nodes, using a bias currents and hence the transconductances (gm ) and gains
current buffer structure, significant improvement in opamp of the amplifying stages remain undefined. This may worsen
performance can be achieved. These compensation methods the performance of the op-amp, consume larger current and
give rise to left-half plane (LHP) zero, instead of a right can even render the op-amp unstable in closed loop. Consider
 2

Figure 2. Biasing scheme for the three-stage op-amp, where all gain
stages are biased properly with known bias currents flowing in all branches
(compensation not shown here). Figure 3. A low-power, pole-zero canceled, class-AB, three-stage op-amp.

v
ic1 ≈ 1 sCc2+ R
1 c1
the three-stage op-amp topology illustrated in Fig. 2. Here diff-
Cc1 Cc2
amps are used for the internal gain stages, both of which are
v1 v2 C2 C3 vout
biased with the same reference, Vbiasn . In this topology, the gm1vs gm2v1 gm3v2
R1 C1 ic1 ic2 R2 Rc1 R3 Rc2
voltage levels of the nodes 1 and 2 are set to be approximately
equal to Vbiasp, due to symmetry in each of the diff-amps. v
ic 2 ≈ 1 sC out+ R
Thus the bias currents in all the three gain stage branches are c2 c2

well defined, and their gm ’s and the DC gains are precisely

Figure 4. Small signal analytical model for the RSLC three-stage op-amp.
fixed. A diff-amp is not used in the last stage due to its limited
output swing. Alternatively, if we had a common-source gain
stage as the second stage in the op-amp, the drain voltage C. Small Signal Analysis and Pole-Zero Cancellation
of transistors in second stage (node-2) will be set by the
contention between the PMOS current source and the NMOS The simplified small signal model for the RSLC three-stage
current sink. In this scenario, the voltage at node-2 will not op-amp is shown in Fig. 4. Here, gmc1 and gmc2 are the
bias correctly in the presence of large device mismatches. transconductances of transistor M2T and M1T respectively.
Rc1 and Rc2 are the impedance attached to the nodes fbr
and fbl respectively, which are both roughly equal to . Here,
gmk is the transconductance of the k th gain stage while and
B. Three-Stage Op-amp Compensation Ck are the resistance and capacitance respectively, attached
to the node-k in the op-amps (k =1, 2, 3). After applying
The split-length compensation scheme is applied to three- nodal analysis to the small signal model shown in Fig. 4, the
stage op-amp design. A reversed nested compensation topol- resulting transfer function can be written as [8].
ogy is used so that the output is not loaded by both of the
 
compensation capacitors, which results in a larger unity gain AOL 1 + b1 s + b2 s2
frequency (ωun ). Fig. 3 shows a reverse-nested split-length H(s) ≈    
compensated (RSLC), class-AB three-stage op-amp. A stack 1 + aa01 s 1 + aa21 s + aa31 s2 1 + aa43 s + a5 2
a3 s
of maximum three transistors is used to realize the low-VDD (1)
gain stages. In this topology an NMOS diff-amp is cascaded The DC gain AOL is equal to and the unity gain frequency is
with a PMOS diff-amp which is followed by a class-AB given as
gm1
output buffer. The PMOS diff-pair in second stage employs ωun = (2)
C c2
wider devices to increase the input common-mode range of
the second stage. A split-length diff-pair (SLDP) is used and the dominant pole is located at
for indirect compensation in order to achieve better supply 1
ωp 1 ≈ (3)
noise isolation [8]. A diff-amp is employed in the second gm3 R3 gm2 R2 R1 Cc2
stage to ensure that the third stage is ‘properly’ biased by
The pole-zero cancellation leads to the following design
symmetry. The compensation capacitor Cc1 is used to feedback
criterion
the compensation current ic1 from the output of the second
stage (node-2) to the output of the first stage (node-1) though CL Cc (CL + Cc2 ) Cc
Rc 1 ≈ , Rc2 ≈ 1 2
≈ 1 Rc 1 (4)
a common gate current buffer. Similarly, capacitor Cc2 is used gm3 Cc2 gm3 Cc2 Cc2
to feedback current ic2 from node-3 to node-1. Here, the bias Note that the design equations are independent of the parasitic
voltages Vpcas = VDD − 2VSG and Vncas = 2VGS are used nodal resistance and capacitance values. The pole-zero cancel-
to bias the floating current mirror. To ensure overall negative lation leads to real pole-zero doublets located at [8] (see Fig.
feedback in the circuit, the compensation capacitance must be 5)
connected across two nodes which move in opposite direction 1 gm3 Cc2
ωp 2 = ωz 1 ≈ = (5)
[8]. Rc 1 C c 1 C c1 C L
 3

jω
6) Select Cc1 and gm3 such that the pole-zero doublet
locations are outside ωun (Eq. 5,6).
7) Calculate R1c and R2c (Eq. 4).
8) If either of R1c or R2c is negative (not realizable),
σ
move the corresponding pole-zero doublet to a lower
− ω un frequency by changing the corresponding Cck and Rck .
Here, ωun may need to be reduced. Go to step 4.
Figure 5. Pole-zero plot for a typical split-length compensated three-stage 9) Simulate the design for frequency response and transient
opamp. settling. If the phase margin (φM ) needs to be increased,
go to step 4.
1 gm3 Cc2 ωp 2 10) Verify if the design meets desired specifications. If not,
ωp3 = ωz2 ≈ = = C
(6) modify the design using the following steps and go back
Rc2 C c2 Cc1 (CL + Cc2 ) 1 + CcL2 to step 2.
From Eq. 5 and 6, we can see that the non-dominant pole- a) Settling speed can be increased by increasing gm1
zero doublets appear close together in the frequency domain. or decreasing Cc2 .
The pole-zero doublets should be placed at a frequency higher b) Power can be reduced by decreasing gm3 or gm2 .
than the ωun of the op-amp, which results in the upper bound c) Layout area can be reduced by decreasing Cc1 ,
on ωun [8]  Cc2 or gm3 .
gm1 gm3 d) Slew-rate (SR) can be improved by increasing the
ωun ≤ (7)
C c1 C L bias current in the first stage or by using smaller
Cc ’s.
The location and quality factor of the parasitic conjugate poles
In order to simplify the design procedure, a MATLAB based
due to the loading of nodes fbl and fbr are given by
 toolkit has been developed [10]. The scripts in the toolkit
gm3 Cc2 gm2 R2 Cc2 use small-signal parameters of the transistors and the parasitic
(ωp4,5 ) ≈ (8) capacitances as input data to assist in design and pole-zero
CL C 1 C 2 C c1
compensation of the three-stage opamps. Fig. 6illustrates the
 ⎛ ⎞
frequency response of a RSLC three-stage opamp designed for
gm2 R2 ⎝ 1 ⎠ 67◦ phase-margin.
Q4,5 ≈ (9)
Rc1 Rc2 1 C1
+ 1 C2
R1 C2 R2 C1
Bode Diagram
The mirror poles in the diff-amps are located at a higher 100
Gm = 12.7 dB (at 1.4e+009 rad/sec) , Pm = 67.1 deg (at 4.18e+008 rad/sec)

frequency than the poles ωp1−5 . The phase margin for the
50
opamp can be approximated as
Magnitude (dB)

⎛ ⎞ 0

ωun
⎜ Q4,5 ⎟ -50
φM ≈ 90◦ − tan−1 ⎝  2 ⎠ (10)
-100
ωun
1− ω4,5
-150
0
It can be observed that the location of the parasitic poles and
hence the phase margin is dependent upon the choice of open- -90
Phase (deg)

loop gain in the second stage.

 The slew-rate
 for these opamps
I I
can be estimated as min CSSc 1 , CSSc 2 , where Issk are the diff- -180
1 2
amp tail currents. A detailed comparison of the RSLC opamps
-270
with the prior literature is provided in [8], [9]. 10
4
10
6
10
8
10
10

Frequency (rad/sec)

IV. D ESIGN P ROCEDURE Figure 6. Bode plot for the RSLC three-stage opamp design.
The design of three-stage opamp using split-length com-
pensation can be seen as a non-linear optimization of multiple The script also enables greater insight into the stability of
variables. We present an iterative design procedure to meet multi-pole and zero system using Nyquist stability plot (see
desired set of specifications: Fig. 7). Nyquist stability criterion captures the rich closed-
1) Start with initial specification of ωun , AOL , CL and SR. loop dynamics of the three-stage opamps, especially when
2) Distribute DC gain, AOL , across the stages as A1 , A2 uncanceled LHP zeros are located, which lead to transient
and A3 (where Ak = gmk rok ) settling artifacts not captured by the Bode plot.
3) Select the overdrive which will set VGS , fT and gm ro .
4) Select a value for gm1 . Select gm2 for the desired phase V. F ULLY-D IFFERENTIAL T HREE -S TAGE O PAMPS
margin (P M ) (Eq. 8,9). Fully-differential (FD), three-stage op-amps can be im-
5) Select Cc2 = ωgm1un
(Eq. 2). plemented by extending the design techniques presented in
 4

VDD VDD VDD VDD

Nyquist Diagram VCMFB1

1.5
Cc VCMFB1 Cc
vom1 vop1
1

20/2 20/2 vop1 vom1

vp vm Vbiasp
fbl fbr
0.5 20/2 20/2 Vbiasn
Imaginary Axis

0 Vbiasn First Stage

-0.5
VDD VDD VDD VDD

VCMFB2
-1
Cc VCMFB2 Cc
Cc1 Cc1
vom2 vop2
-1.5 R1c R1c
-1.5 -1 -0.5 0 0.5 1 1.5 vop2 vom2
Real Axis
vop1 fbr fbl vom1 Vbiasp
60/2 60/2
Vbiasn

Figure 7. Nyquist stability plot for a RSLC three-stage opamp design. Here
the phase margin (φM ) can be observed to be 67◦ . Vbiasn Second Stage

Unlabeled NMOS are 10/2.

Unlabeled PMOS are 22/2.
VDD VDD
VDD
Section IV. A FD op-amp requires the output common mode VDD 30/2
VCMFB3
30/2 VDD vop Vbiasp

level to be balanced by a common-mode feedback (CMFB)

vop2 vom2
loop. The first topology in the logical sequence is the one with 80/2 VDD VDD 80/2
Cc2 R2c VCM
vom R2c Cc2 vop
a single CMFB loop around all the three stages. Topologies fbl fbr VCMFB3

based upon this block diagram have been proposed in [11],

vom
[12], [13]. However, it is observed that the CMFB loop
50/2 50/2 Output Buffer
disturbs the biasing of the second and third stages as the (Third Stage)

common mode levels at node-1 and node-2 vary widely.

Additionally, such such topologies exhibit start-up problems. Figure 8. Fully-differential implementation of the split-length compensated
A robust three-stage opamp has individual CMFB loops for all three-stage op-amp along with the common-mode feedback circuits for each
of the gain stages.
the stages. However, it must be ensured that the common-mode
sensing circuitry does not load the internal gain stages. Fig. 8
shows the schematic of a fully-differential implementation of
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