🔹 Detailed Definitions

1. Register Transfer Language (RTL):

A symbolic language used to describe the operations in digital systems at the register level.
RTL specifies how data is moved between registers and what operations are performed on
that data during a clock cycle.
2. Data Representation:
Refers to the methods used to represent various data types (such as integers, real numbers,
and characters) in binary format within a computer system.
3. Register Transfer:
The process of transferring data from one register to another. It is usually controlled by
control signals that enable the source register to place data on the bus and the destination
register to load data from the bus.
4. Bus and Memory Transfer:
A bus is a shared communication path used to transfer data, addresses, and control signals.
Memory transfer refers to the read/write operations that move data between memory and
the CPU using the bus.
5. Data Representation – Fixed Point and Floating Point:
Fixed Point: Numbers represented with a fixed number of digits before and
after the decimal point. Suitable for integers or where precision is limited.
Floating Point: Represents real numbers using a mantissa and exponent,
allowing for a wider range of values with better precision.
6. Micro-operations:
Fundamental operations that operate on the data stored in registers. Types include:
Arithmetic (e.g., ADD, SUB)
Logical (e.g., AND, OR)
Shift (e.g., logical shift, arithmetic shift)
Control operations
7. Instruction Code:
A binary-coded command that specifies a particular operation to be performed by the CPU.
8. Computer Register:
A high-speed storage location inside the CPU used for temporary storage and quick access
during instruction execution.
9. Computer Instructions:
A set of machine language commands that a computer can execute. Each instruction
typically contains an operation code (opcode) and operand(s).
10. Instruction Cycle:
The sequence of steps a CPU follows to fetch, decode, and execute an instruction. It
consists of:
Fetch
Decode
Execute
11. Memory-Reference Instructions:
Instructions that refer to memory locations to fetch or store data. Examples: LDA (Load
Accumulator), STA (Store Accumulator).
12. Register-Reference Instructions:
These operate directly on the processor’s registers and do not involve memory addresses.
Example: CLA (Clear Accumulator), CMA (Complement Accumulator).
13. I/O and Interrupt:
Input/Output (I/O): Communication between CPU and external devices.
Interrupt: A mechanism by which an I/O device can interrupt the CPU to request service.
14. General Register Organization:
An arrangement where multiple general-purpose registers are interconnected via a
common bus, allowing flexibility in data manipulation.
15. Stack Organization:
A form of memory organization that uses a last-in-first-out (LIFO) approach. Operations are
controlled using stack pointer (SP).
16. Instruction Formats:
The layout of bits in an instruction. Formats include fields like opcode, operand(s), and
mode bits. Common formats are 0-address, 1-address, 2-address, and 3-address.
17. Addressing Modes:
Techniques to specify the operand for an instruction. Examples:
Immediate
Direct
Indirect
Register
Indexed
18. Data Transfer and Manipulation Instructions:
Instructions used to move data from one place to another or perform operations on the
data (e.g., MOV, ADD, SUB).
19. Program Control:
Instructions that alter the sequence of program execution, such as branching, jumping, or
calling subroutines.
20. Memory Hierarchy:
An arrangement of memory in levels based on speed, cost, and size. It includes:
Registers (fastest, smallest)
Cache
Main Memory (RAM)
Secondary Storage (HDD, SSD)
21. Main Memory:
The primary volatile memory that stores data and programs actively used by the CPU
during processing.
22. Auxiliary Memory:
Non-volatile memory used for long-term storage. Examples include hard disks, SSDs, and
optical drives.
23. Associative Memory:
Also known as content-addressable memory (CAM). It accesses data based on content
rather than specific memory addresses.
24. Cache Memory:
A small, high-speed memory between CPU and main memory that stores frequently
accessed instructions/data to reduce average access time.
25. Peripheral Devices:
External hardware connected to the computer to input, output, or store data (e.g.,
keyboard, mouse, printer).
 26. I/O Interface:
A set of circuits that manage the interaction between the CPU and external devices,
handling timing and control.
27. Asynchronous Data Transfer:
A type of data transfer that does not require a common clock signal. It uses control signals
like “request” and “acknowledge” to manage data flow.
28. Modes of Transfer:
Methods of transferring data between CPU and peripherals. Main modes:
Programmed I/O
Interrupt-driven I/O
Direct Memory Access (DMA)
29. Priority Interrupts:
A system where multiple interrupts are assigned priorities, and the highest priority interrupt
is serviced first.
30. Direct Memory Access (DMA):
A feature allowing peripherals to access memory directly without CPU intervention,
increasing data transfer speed.

🔹 RISC vs CISC Architecture

Feature RISC (Reduced Instruction Set CISC (Complex Instruction Set
Computer) Computer)

Instruction Set Uses a small, highly optimized set of Uses a large set of complex
instructions instructions

Instruction Fixed-length instructions (usually 32 Variable-length instructions

Length bits)

Execution Time Single-cycle execution for most Multiple cycles for many instructions
instructions

Complexity Simple hardware, more software- Complex hardware, more built-in

based optimization instruction capabilities

Memory Usage More instructions, less memory per Fewer instructions but each can use
instruction more memory

Compiler Role Compiler must handle more code Compiler has simpler job due to rich
optimization instruction set

Examples ARM, MIPS, SPARC x86, Intel 8086, VAX

Usage Used in mobile devices, embedded Used in desktops, laptops, and servers
systems

🔹 Differentiate Between (Detailed Table)

 Point of First Term Second Term
Topic Difference

Synchronous vs Clock Dependency Requires a common clock No common clock;

Asynchronous Data between sender and uses handshake signals.
Transfer receiver.

Speed Generally faster due to Slightly slower due to

synchronized timing. handshake mechanism.

Complexity Simpler implementation. More complex due to

control signals.

Use Case Suitable for short Used in I/O devices

distance, high-speed data with varying speeds.
transfer.

Register Stack vs Storage Medium Uses processor's internal Uses main memory
Memory Stack registers. (RAM).

Speed Faster access as it uses Slower compared to

internal registers. register stack.

Size Limited by number of Can store large data

registers. since memory is larger.

Cost More expensive. Cheaper and more

flexible.

Direct vs Indirect Addressing Address of operand is Address field contains

Addressing Mode directly specified. memory location of
operand address.

Number of One memory access to Two memory accesses:

Memory Accesses fetch operand. one for address, one
for operand.

Speed Faster as fewer memory Slower due to extra

accesses. level of addressing.

Example MOV A, 5000 (5000 is MOV A, @5000 (5000

address of operand) has address of
operand)

Instruction Cycle vs Definition Entire process of fetching, Only the phase where
Execution Cycle decoding, and executing instruction is executed.
an instruction.

Steps Included Fetch, Decode, Execute. Only Execution.

Role in CPU Describes full behavior Describes the action

per instruction. taken on data.

Timing Longer due to multiple Shorter as it is only

steps. one part.

Memory-Mapped Address Space I/O devices share Separate address

I/O vs Isolated I/O memory address space. space for I/O.
 Instruction Set Uses memory instructions Special I/O instructions
for I/O. are needed.

Hardware Simpler. More complex due to

Complexity different instruction
sets.

Flexibility More flexible and unified. More secure but

limited.

Main Memory vs Location Located outside the CPU. Lies between CPU and
Cache Memory main memory.

Access Time Slower. Much faster.

Size Larger. Smaller in size.

Cost Cheaper. More expensive per

byte.

Programmed I/O vs CPU Involvement CPU continuously checks CPU is interrupted only
Interrupt-driven I/O device status. when device is ready.

Efficiency Inefficient due to busy- Efficient as CPU does

waiting. other tasks meanwhile.

Implementation Simpler to implement. Requires interrupt

controller.

Example Polling a keyboard. Keyboard interrupt

handler.

📘 MOCK SEMESTER PAPER – COMPUTER ORGANIZATION

AND ARCHITECTURE
Section A (4 × 8 = 32 marks)
Each question has 3 sub-questions – Concept + Problem + Explanation/Application.

Q1. Register Transfer and Microoperations

(a) Define Register Transfer Language (RTL).
(b) Explain arithmetic microoperations with an example.
(c) Perform the arithmetic operation: A = (B + C) - D using register transfer notation.
Answer:
(a) Register Transfer Language (RTL):
RTL is a symbolic notation used to describe the operations in digital systems. It specifies the flow of
data between registers and the operations performed on the data. Example:

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R1 ← R2 + R3

This denotes that the contents of R2 and R3 are added, and the result is stored in R1.
(b) Arithmetic Microoperations:
These operations perform basic arithmetic functions like addition, subtraction, increment, decrement,
etc., between the contents of registers.
Example:

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R3 ← R1 + R2

This adds the contents of R1 and R2 and stores the result in R3.
(c) Register Transfer Notation:
Let the registers be A, B, C, D.
Step 1: T ← B + C
Step 2: A ← T - D
Combined:

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T ← B + C A ← T - D

Q2. Instruction Cycle and Types

(a) What are the phases of the instruction cycle?
(b) Explain memory-reference instructions with example.
(c) Given instruction ADD 300 , explain its execution.
Answer:
(a) Instruction Cycle Phases:

1. Fetch: Get instruction from memory.

2. Decode: Determine operation and addressing mode.
3. Execute: Perform the operation.
4. Interrupt (if any): Check and handle interrupts.
(b) Memory-Reference Instructions:
These are instructions that refer to memory locations. Example:

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LDA 200

Means load the content of memory address 200 into the accumulator.

(c) Execution of ADD 300 :

Fetch ADD 300

Decode: ADD operation, address = 300
Execute: AC ← AC + M[300]

Q3. Addressing and Instruction Format

(a) Define Addressing Modes.
(b) Explain indirect and immediate addressing with example.
(c) Given instruction: LDA (500) , Memory[500] = 800, Memory[800] = 25, find content of AC.

Answer:
(a) Addressing Modes:
They specify how to calculate the effective memory address of an operand. Common modes are
direct, indirect, immediate, register, indexed, etc.
(b)

Indirect: Address field refers to memory location that holds the effective address.
Example: LDA (500)
Immediate: Operand is part of instruction.
Example: LDA #25
(c)
Instruction: LDA (500)

Step 1: EA = M[500] = 800

Step 2: AC ← M[800] = 25
Answer: AC = 25

Q4. Memory Hierarchy

(a) Draw and explain memory hierarchy.
(b) Differentiate between associative and cache memory.
(c) A cache has hit ratio = 0.9, main memory access = 100 ns, cache = 10 ns. Find effective access
time.

Answer:

(a) Memory Hierarchy:

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Registers ↓ Cache Memory ↓ Main Memory ↓ Secondary/Auxiliary Memory

Fastest at top, largest capacity at bottom.

(b)

Aspect Cache Memory Associative Memory

Purpose Speed up access Content-based addressing

Access Method Address-based Content-based

(c)
EAT = (Hit ratio × Cache time) + (Miss ratio × Memory time)
= (0.9 × 10) + (0.1 × 100)
= 9 + 10 = 19 ns

Section B (2 × 14 = 28 marks)
Q5. Data Representation and Floating Point
(a) Explain normalized floating point representation.
(b) Represent -37.625 in IEEE 754 single precision.
(c) Perform fixed-point addition: A = 01101100, B = 10010110.

Answer:
(a) Normalized Floating Point:
It is a way to represent real numbers such that the mantissa begins with a non-zero digit. IEEE 754
single precision uses 32 bits:

1 bit: Sign
8 bits: Exponent (with bias 127)
23 bits: Mantissa (fraction)
(b) Convert -37.625:

Sign bit = 1
37.625 in binary = 100101.101
Normalized = 1.00101101 × 2^5
Exponent = 5 + 127 = 132 = 10000100

Mantissa = 001011010000... (23 bits)

IEEE 754: 1 10000100 00101101000000000000000
(c) Fixed Point Addition:
A = 01101100 (108)
B = 10010110 (2's comp = -106)
Result: 108 + (-106) = 2
= 00000010

Q6. Input-Output Organization

(a) Explain asynchronous data transfer.
(b) Compare programmed I/O and interrupt-driven I/O.
(c) A device interrupts CPU with priority levels 0–3. Draw and explain priority interrupt handling.

Answer:
(a) Asynchronous Data Transfer:
Data is transferred using handshake signals (ready/ack). Sender and receiver operate independently.
(b)

Feature Programmed I/O Interrupt I/O

CPU Involvement Polls device CPU interrupted

Efficiency Low High

(c) Priority Interrupt:

Draw priority encoder circuit.

Each device sends interrupt line

CPU checks priority
Highest priority serviced first
Lower priorities wait

MOCK SEMESTER PAPER – 2

Subject: Computer Organization and Architecture
Total Marks: 60
Time: 3 Hours

Section A (4 × 8 = 32 Marks)
Each question contains 3 parts – Concept Explanation, Numerical/Problem, and Application.

Q1. Bus and Memory Transfer

(a) What is the function of the system bus in a computer?

(b) Differentiate between synchronous and asynchronous data transfer.
(c) Describe with a block diagram how memory read and write operations occur via system bus.
Answer:
(a) The system bus is a communication channel that connects the major components of a computer. It
includes three types of buses:
 Data Bus: Carries actual data.
Address Bus: Carries memory addresses.
Control Bus: Carries control signals (e.g., Read/Write).
(b)

Synchronous Transfer: All devices share a common clock. Transfers occur at regular
intervals.
Asynchronous Transfer: No common clock; uses handshake signals for coordination (e.g.,
ACK , REQ ).
(c)

Memory Read: CPU places address on address bus → Control Bus sends “Read” → Memory
sends data on Data Bus.
Memory Write: CPU sends data and address → Control Bus sends “Write” → Memory
stores data.
(Include block diagram with CPU ↔ Memory via buses)

Q2. Microoperations

(a) Define shift microoperations and list their types.

(b) Explain arithmetic shift right and its use in signed numbers.
(c) Perform arithmetic shift right on 8-bit binary number: 11011010.
Answer:
(a) Shift microoperations transfer data bits within a register.
Types:

Logical shift
Arithmetic shift
Circular shift
(b) Arithmetic shift right: Used for signed binary numbers (2’s complement). It preserves the sign bit
while shifting. Equivalent to integer division by 2.

(c) 11011010 → Arithmetic shift right → 11101101

Q3. Instruction Codes and Registers

(a) Define instruction format and its components.

(b) What is the role of the Program Counter and Instruction Register?
(c) If PC = 300, IR = 1940 (Opcode = 5, Address = 940), explain fetch-decode-execute cycle.
Answer:
(a) Instruction Format includes:

Opcode: Operation to perform

Address Field: Location of operand
Mode Bits: Addressing method
(b)

Program Counter (PC): Holds address of next instruction

Instruction Register (IR): Holds current instruction being executed
(c)

Fetch: MAR ← PC = 300; IR ← M[300] = 1940

Decode: Opcode = 5 (ADD), Address = 940
Execute: AC ← AC + M[940]

Q4. Stack Organization

(a) Define stack and its operations.

(b) Explain register stack vs memory stack.
(c) Given stack: TOP → 35, 28, 19. Perform PUSH 42 and then POP.
Answer:
(a) A stack is a LIFO structure.

PUSH: Add item to stack

POP: Remove top item
(b)

Register Stack: Implemented with CPU registers. Fast but limited.

Memory Stack: Uses RAM and Stack Pointer (SP). Larger capacity.
(c)

PUSH 42: TOP → 42, 35, 28, 19

POP: Removes 42 → TOP → 35, 28, 19

Section B (2 × 14 = 28 Marks)
Each question includes concept explanation, detailed application, and problem.

Q5. Addressing Modes and Instruction Formats

(a) Explain various addressing modes with examples.

(b) Describe instruction formats based on architecture.
(c) Given a two-address instruction MOV R1, R2 where R1=35, R2=50. Convert to zero-address
instruction using stack and show execution.
Answer:
(a) Addressing Modes:
 Immediate: Operand in instruction (e.g., MOV A, #5)
Direct: Operand address in instruction (MOV A, 2000)
Indirect: Address points to another address (MOV A, (2000))
Register: Operand in register (MOV A, R1)
Indexed: Operand = Base + Index (MOV A, 1000(X))
(b)
Instruction formats differ by operand count:

0-address: Stack-based
1-address: Accumulator-based
2-address: Needs fewer instructions than 1-address
3-address: More flexibility but longer instruction
(c)
MOV R1, R2 (R1 = R2 = 50)
Zero-address using Stack:

PUSH 35
PUSH 50
POP T1, POP T2
T2 → T1
PUSH T1 → Stack: 50

Q6. Memory Hierarchy and Cache

(a) Explain memory hierarchy and its need.

(b) Describe cache memory operations, locality of reference, and mapping techniques.
(c) Given: Cache hit ratio = 0.85, cache access = 15 ns, main memory = 100 ns. Find Effective Access
Time.
Answer:
(a) Memory Hierarchy:

Registers > Cache > Main Memory > Secondary Storage

Needed for speed-cost balance. Faster memory is smaller and costlier.
(b) Cache Operations:

Stores frequently used data for faster access

Locality of Reference:
Temporal: Recently accessed → accessed again soon
Spatial: Nearby memory locations accessed soon
Mapping Techniques:
Direct Mapping
Associative Mapping
Set-Associative Mapping
(c)
Effective Access Time (EAT):
EAT = (Hit ratio × Cache time) + (Miss ratio × Memory time)
= (0.85 × 15) + (0.15 × 100)
= 12.75 + 15 = 27.75 ns
Higher associativity → fewer misses → better performance but more complexity.