BRAINWARE UNIVERSITY

School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

A sequential circuit is a circuit whose output depends not only on the circuit’s present inputs, but also
on the circuit’s present state, which is all the bits stored in the circuit. The circuit’s state in turn depends
on the past sequence of the circuit’s input values. In sequential circuits, the output signals are fed back
to the input side. A block diagram of a sequential circuit is shown in Figure below:-

It consists of a combinational circuit to which storage elements are connected to form a feedback path.
The storage elements are devices capable of storing binary information. The binary information stored
in these elements at any given time defines the state of the sequential circuit at that time. The
sequential circuit receives binary information from external inputs that, together with the present state
of the storage elements, determine the binary value of the outputs. These external inputs also
determine the condition for changing the state in the storage elements. The block diagram
demonstrates that the outputs in a sequential circuit are a function not only of the inputs, but also of
the present state of the storage elements. The next state of the storage elements is also a function of
external inputs and the present state. Thus, a sequential circuit is specified by a time sequence of
inputs, outputs, and internal states.

The difference between the combinational and sequential circuit is given below

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

There are two types of sequential circuits, and their classification is a function of the timing of their
signals.
Asynchronous sequential circuit:
A sequential circuit whose behavior depends upon the sequence in which the input signals change is
referred to as an asynchronous sequential circuit. The output will be affected whenever the input
changes. The commonly used memory elements in these circuits are time-delay devices. There is no
need to wait for a clock pulse. Therefore, in general, asynchronous circuits are faster than synchronous
sequential circuits. However, in an asynchronous circuit, events are allowed to occur without any
synchronization. And in such a case, the system becomes unstable. Since the designs of asynchronous
circuits are more tedious and difficult, their uses are rather limited. The memory elements used in
sequential circuits are flip-flops which are capable of storing binary information.
Synchronous sequential circuit:
A sequential circuit whose behavior can be defined from the knowledge of its signal at discrete instants
of time is referred to as a synchronous sequential circuit. In these systems, the memory elements are
affected only at discrete instants of time. The synchronization is achieved by a timing device known as
a system clock, which generates a periodic train of lock pulses. The outputs are affected only with the
application of a clock pulse.
Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

bit of information. The main difference between latches and flip-flops is that for latches, their outputs
are constantly affected by their inputs as long as the enable signal is asserted. In other words, when
they are enabled, their content changes immediately when their inputs change. Flip-flops, on the other
hand, have their content change only either at the rising or falling edge of the enable signal. This enable
signal is usually the controlling clock signal. After the rising or falling edge of the clock, the flip-flop
content remains constant even if the input changes. There are basically four main types of latches and
flip-flops: SR, D, JK, and T. The major differences in these flip-flop types are the number of inputs they
have and how they change state. For each type, there are also different variations that enhance their
operations.
Latch
Latches are basic storage elements that operate with signal levels (rather than signal transitions).
Latches controlled by a clock transition are flip-flops. Latches are level-sensitive devices. Latches are
useful for the design of the asynchronous sequential circuit. Latches are sequential circuit with two
stable states. These are sensitive to the input voltage applied and does not depend on the clock pulse.
Flip flops that do not use clock pulse are referred to as latch.
SR Latch
S-R latches i.e., Set-Reset latches are the simplest form of latches and are implemented using two
inputs: S (Set) and R (Reset). The S input sets the output to 1, while the R input resets the output to 0.
When both S and R inputs are at 1, the latch is said to be in an “undefined” state. They are also known
as preset and clear states. The SR latch forms the basic building blocks of all other types of flip-flops.
The below table represents the truth table of SR latch.

While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state,
with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is
forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

the Q output is forced low, and stays low when R returns to low.
To analyze the circuit of S-R Flip-flop Based on NOR Gates, we have to consider the fact that the output
of a NOR gate is 0 if any of the inputs are 1, irrespective of the other input. The output is 1 only if all of
the inputs are 0. The outputs for all the possible conditions as shown in the above table are described
as follows.
Case 1. For S = 0 and R = 0, the flip-flop remains in its present state (Qn). It means that the next state of
the flip-flop does not change, i.e., Qn+1 = 0 if Qn = 0 and vice versa. First let us assume that Qn= 1 and
Q'n= 0.Thus the inputs of NOR gate 2 are 1 and 0, and therefore its output Q'n+1 = 0. This output Q'n+1
= 0 is fed back as the input of NOR gate1, thereby producing a 1 at the output, as both of the inputs of
NOR gate 1 are 0 and 0; so Qn+1 = 1 as originally assumed. Now let us assume the opposite case, i.e.,
Qn = 0 and Q'n = 1. Thus the inputs of NOR gate 1 are 1 and 0, and therefore its output Q'n+1 = 0. This
output Qn+1 = 0 =0 is fed back as the input of NOR gate 2, thereby producing a 1 at the output, as both
of the inputs of NOR gate 2 are 0 and 0; so Q'n+1 = 1 as originally assumed. Thus we find that the
condition S = 0 and R = 0 do not affect the outputs of the flip-flop, which means this is the memory
condition of the S-R flip-flop.
Case 2. The second input condition is S = 0 and R = 1. The 1 at R input forces the output of NOR gate 1
to be 0 (i.e., Qn+1 = 0). Hence both the inputs of NOR gate 2 are 0 and 0 and so its output Q'n+1 = 1.
Thus the condition S = 0 and R = 1 will always reset the flip-flop to 0. Now if the R returns to 0 with S =
0, the flip-flop will remain in the same state.
Case 3. The third input condition is S = 1 and R = 0. The 1 at S input forces the output of NOR gate 2 to
be 0 (i.e., Q'n+1 = 0). Hence both the inputs of NOR gate 1 are 0 and 0 and so its output Qn+1 = 1. Thus
the condition S = 1 and R = 0 will always set the flip-flop to 1. Now if the S returns to 0 with R = 0, the
flip-flop will remain in the same state.
Case 4. The fourth input condition is S = 1 and R = 1. The 1 at R input and 1 at S input forces the output
of both NOR gate 1 and NOR gate 2 to be 0. Hence both the outputs of NOR gate 1 and NOR gate 2 are
0 and 0; i.e., Qn+1 = 0 and Q'n+1 = 0. Hence this condition S = 1 and R = 1 violates the fact that the
outputs of a flip-flop will always be the complement of each other. Since the condition violates the basic
definition of flip-flop, it is called the undefined condition. Generally this condition must be avoided by
making sure that 1s are not applied simultaneously to both of the inputs.
Case 5. If case 4 arises at all, then S and R both return to 0 and 0 simultaneously, and then any one of
the NOR gates acts faster than the other and assumes the state. For example, if NOR gate 1 is faster
than NOR gate 2, then Qn+1 will become 1 and this will make Q'n+1 = 0. Similarly, if NOR gate 2 is faster
than NOR gate 1, then Q'n+1 will become 1 and this will make Qn+1 = 0. Hence, this condition is
determined by the flip-flop itself. Since this condition cannot be controlled and predicted it is called the
indeterminate condition.

CLOCKED S-R FLIP-FLOP

Generally, synchronous circuits change their states only when clock pulses are present. The operation
of the basic flip-flop can be modified by including an additional input to control the behavior of the

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

circuit. Such a circuit is shown below:-

The circuit shown above consists of two AND gates. The clock input is connected to both of the AND
gates, resulting in LOW outputs when the clock input is LOW. In this situation the changes in S and R
inputs will not affect the state (Q) of the flip-flop. On the other hand, if the clock input is HIGH, the
changes in S and R will be passed over by the AND gates and they will cause changes in the output (Q)
of the flip-flop. This way, any information, either 1 or 0, can be stored in the flip-flop by applying a HIGH
clock input and be retained for any desired period of time by applying a LOW at the clock input. This
type of flip-flop is called a clocked S-R flipflop.
Such a clocked S-R flip-flop made up of two AND gates and two NOR gates is shown in Figure below:-

The logic symbol of the S-R flip-flop is shown below. It has three inputs: S, R, and CLK. The CLK input is
marked with a small triangle. The triangle is a symbol that denotes the fact that the circuit responds to
an edge or transition at CLK input.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

The circuit with all NAND gates is given below

Assuming that the inputs do not change during the presence of the clock pulse, we can express the
working of the S-R flip-flop in the form of the truth table shown here. Here, Sn and Rn denote the inputs
and Qn denotes the output during the bit time n. Qn+1 denotes the output after the pulse passes i.e. in
the bit time n + 1.
Case 1. If Sn = Rn = 0, and the clock pulse is not applied, the output of the fl ip-fl op remains in the
present state. Even if Sn = Rn = 0, and the clock pulse is applied, the output at the end of the clock pulse
is the same as the output before the clock pulse, i.e., Qn+1 = Qn. The first row of the table indicates
that situation.
Case 2. For Sn = 0 and Rn = 1, if the clock pulse is applied (i.e. CLK = 1), the output of NAND gate 1
becomes 1; whereas the output of NAND gate 2 will be 0. Now a 0 at the input of NAND gate 4 forces
the output to be 1 i.e. Q' = 1. This 1 goes to the input of NAND gate 3 to make both the inputs of NAND
gate 3 as 1, which forces the output of NAND gate 3 to be 0, i.e., Q = 0.
Case 3. For Sn = 1 and Rn = 0, if the clock pulse is applied (i.e., CLK = 1), the output of NAND gate 2
becomes 1; whereas the output of NAND gate 1 will be 0. Now a 0 at the input of NAND gate 3 forces
the output to be 1, i.e., Q = 1. This 1 goes to the input of NAND gate 4 to make both the inputs of NAND
gate 4 as 1, which forces the output of NAND gate 4 to be 0, i.e., Q' = 0.
Case 4. For Sn = 1 and Rn = 1, if the clock pulse is applied (i.e. CLK = 1), the outputs of both NAND gate
2 and NAND gate 1 becomes 0. Now a 0 at the input of both NAND gate 3 and NAND gate 4 forces the

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

outputs of
both the gates to be 1, i.e., Q = 1 and Q' = 1. When the CLK input goes back to 0 (while S and R remain
at 1), it is not possible to determine the next state, as it depends on whether the output of gate 1 or
gate 2 goes to 1 first.

Preset and Clear

Till now the flip-flops we discussed there when the power is switched on, the state of the circuit is
uncertain. It may come to reset (Q = 0) or set (Q = 1) state. But in many applications, it is required to
initially set or reset the flip-flop., i.e., the initial state of the flip-flop is to be assigned. This is done by
using the direct or asynchronous inputs. These inputs are referred to as preset (Pr) and clear (Cr) inputs.
These inputs may be applied at any time between clock pulses and is not in synchronism with the clock.
Such an S-R flip-flop containing preset and clear inputs is shown in Figure below.

From the above Figure, we see that if Pr = Cr = 1, the circuit operates according to the table of clocked
S-R flip-flop as we discussed just before.
If Pr = 1 and Cr = 0, the output of NAND gate 4 is forced to be 1, i.e., Q' = 1 and the flip-flop is reset,
overwriting the previous state of the flip-flop. If Pr = 0 and Cr = 1, the output of NAND gate 3 is forced
to be 1, i.e., Q = 1 and the flip-flop is set, overwriting the previous state of the flip-flop. Once the state
of the flip-flop is established asynchronously, the inputs Pr and Cr must be connected to logic 1 before
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

the next clock is applied. The condition Pr = Cr = 0 must not be applied, since this leads to an uncertain
state. The logic symbol of an S-R flip-flop with Pr and Cr inputs is shown in the side. Here, bubbles are
used for Pr and Cr inputs, which indicate these are active low inputs, which means that the intended
function is performed if the signal applied to Pr and Cr is LOW. The operation of the clocked S-R flip-
flop is shown in the table in below. The circuit can be designed such that the asynchronous inputs
override the clock, i.e., the circuit can be set or reset even in the presence of the clock pulse.

Characteristic Table of an S-R Flip-flop

From the name itself it is very clear that the characteristic table of a flip-flop actually gives us an idea
about the character, i.e., the working of the flip-flop. Now, from all our above discussions, we know that
the next state flip-flop output (Qn+1) depends on the present inputs as well as the present output (Qn).
So in order to know the next state output of a flip-flop, we have to consider the present state output
also. The characteristic table of an S-R flip-flop is given in the table below. From the characteristic table
we have to find out the characteristic equation of the S-R flip-flop.

Now we will find out the characteristic equation of the S-R flip-flop from the characteristic table with
the help of the Karnaugh map:-

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

From the Karnaugh map above we find the expression for Qn+1 as

CLOCKED D FLIP-FLOP
One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure
that inputs S and R are never equal to 1 at the same time. This is done in the D latch. The D flip-flop has
only one input referred to as the D (data) input & two outputs as usual Q and Q'. It transfers the data
at the input after the delay of one clock pulse at the output Q. So in some cases the input is referred to
as a delay input and the flip-flop gets the name delay (D) flip-flop. It can be easily constructed from an
S-R flip-flop by simply incorporating an inverter between S and R such that the input of the inverter is
at the S end & the output of the inverter is at the R end. We can get rid of the undefined condition, i.e.,
S = R = 1 condition, of the S-R flip-flop in the D flip flop.
The D flip-flop is either used as a delay device or as a latch to store one bit of binary information. The
truth table of D flip-flop is given in the table below. The structure of the D flip-flop is shown in Figure
below, which is being constructed using NAND gates.

Case 1. If the CLK input is low, the value of the D input has no effect, since the S and R inputs of the
basic NAND flip-flop are kept as 1.
Case 2. If the CLK = 1 and D = 1, the NAND gate 1 produces 0, which forces the output of NAND gate 3
as 1. On the other hand, both the inputs of NAND gate 2 are 1, which gives the output of gate 2 as 0.
Hence, output of NAND gate 4 is forced to be 1, i.e., Q = 1, whereas both the inputs of gate 5 are 1 and
the output is 0, i.e., Q' = 0. Hence, we find that when D = 1, after one clock pulse passes Q = 1, which
means the output follows D.
Case 3. If the CLK = 1, and D = 0, the NAND gate 1 produces 1. Hence both the inputs of NAND gate 3
are 1, which gives the output of gate 3 as 0. On the other hand, D = 0 forces the output of NAND gate 2
to be 1. Hence the output of NAND gate 5 is forced to be 1, i.e., Q' = 1, whereas both the inputs of gate
4 are 1 and the output is 0, i.e., Q = 0. Hence, we find that when D = 0, after one clock pulse passes Q =
0, which means the output again follows D. A simple way to construct a D flip-flop using an S-R flip-flop
is shown in Figure below. The logic symbol of a D flip-flop is shown in Figure below. A D flip-flop is most
often used in the construction of sequential circuits like registers.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Characteristic Table of a D Flip-flop

As we have already discussed the characteristic equation of an S-R flip-flop, we can similarly find out
the characteristic equation of a D flip-flop. The characteristic table of a D flip-flop is given in the table
below. From the characteristic table we have to find out the characteristic equation of the D flip-flop.

Now we will find out the characteristic equation of the D flip-flop from the characteristic table with the
help of the Karnaugh map:-

Hence, the characteristic equation of a D flip-flop is Qn+1 = D

J-K FLIP-FLOP
A J-K flip-flop has very similar characteristics to an S-R flip-flop. The only difference is that the undefined
condition for an S-R flip-flop, i.e., Sn = Rn = 1 condition, is also included in this case. Inputs J and K
behave like inputs S and R to set and reset the flip-flop respectively. When J = K = 1, the flip-flop is said
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

to be in a toggle state, which means the output switches to its complementary state every time a clock
passes. The data inputs are J and K, which are ANDed with Q' and Q respectively to obtain the inputs
for S and R respectively. A J-K flip-flop thus obtained is shown in Figure below.
An S-R flip-flop converted into a J-K flip-flop:-

A J-K flip-flop using NAND gates:-

Logic symbol of a J-K flip-flop:-

The TRUTH table for JK flip-flop is:-

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Case 1. When the clock is applied and J = 0, whatever the value of Q'n (0 or 1), the output of NAND gate
1 is 1. Similarly, when K = 0, whatever the value of Qn (0 or 1), the output of gate 2 is also 1. Therefore,
when J = 0 and K = 0, the inputs to the basic flip-flop are S = 1 and R = 1. This condition forces the flip-
flop to remain in the same state.
Case 2. When the clock is applied and J = 0 and K = 1 & the previous state of the flip-flop is reset (i.e.,
Qn = 0 and Q'n = 1), then S = 1 and R = 1. Since S = 1 and R = 1, the basic flip-flop does not alter the state
and remains in the reset state. But if the flip-flop is in set condition (i.e., Qn = 1 & Q'n = 0), then S = 1
and R = 0. Since S = 1 and R = 0, the basic flip-flop changes its state and resets.
Case 3. When the clock is applied and J = 1 and K = 0 and the previous state of the flip-flop is reset (i.e.,
Qn = 0 and Q'n = 1), then S = 0 and R = 1. Since S = 0 and R = 1, the basic flip-flop changes its state and
goes to the set state. But if the flip-flop is already in set condition (i.e., Qn = 1 and Q'n = 0), then S = 1
and R = 1. Since S = 1 and R = 1, the basic flip-flop does not alter its state and remains in the set state.
Case 4. When the clock is applied and J = 1 and K = 1 and the previous state of the flip-flop is reset (i.e.,
Qn = 0 and Q'n = 1), then S = 0 and R = 1. Since S = 0 and R = 1, the basic flip-flop changes its state and
goes to the set state. But if the flip-flop is already in set condition (i.e., Qn = 1 and Q'n = 0), then S = 1
and R = 0. Since S = 1 and R = 0, the basic flip-flop changes its state and goes to the reset state. So we
find that for J = 1 and K = 1, the flip-flop toggles its state from set to reset and vice versa. Toggle means
to switch to the opposite state.
Characteristic Table of a J-K Flip-flop
As we have already discussed the characteristic equation of an S-R flip-flop, we can similarly find out
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

the characteristic equation of a J-K flip-flop. The characteristic table of a J-K flip-flop is given in the table
below.

From the characteristic table we have to find out the characteristic equation of the J-K flip-flop. From
the Karnaugh map, we obtain Qn+1 = JQ'n + K'Qn., the characteristic equation.
Race-around Condition of a J-K Flip-flop
The inherent difficulty of an S-R flip-flop (i.e., S = R = 1) is eliminated by using the feedback connections
from the outputs to the inputs of gate 1 and gate 2 as discussed in JK flip-flop. Truth tables JK flip-flop
were formed with the assumption that the inputs do not change during the clock pulse (CLK = 1). But
the consideration is not true because of the feedback connections. Consider, for example, that the
inputs are J = K = 1 and Q = 1, and a pulse as shown in Figure below is applied at the clock input.

Consider, for example, that the inputs are J = K = 1 and Q = 1, and a pulse as shown above is applied at
the clock input. After a time interval Δt equal to the propagation delay through two NAND gates in
series, the outputs will change to Q = 0. So now we have J = K = 1 and Q = 0. After another time interval
of Δt the output will change back to Q = 1. Hence, we conclude that for the time duration of tp of the
clock pulse, the output will oscillate between 0 and 1. Hence, at the end of the clock pulse, the value of
the output is not certain. This situation is referred to as a race-around condition.
Generally, the propagation delay of TTL gates is of the order of nanoseconds. So if the clock pulse is of
the order of microseconds, then the output will change thousands of times within the clock pulse. This
race-around condition can be avoided if tp < Δt < T. Due to the small propagation delay of the ICs it may
be difficult to satisfy the above condition. A more practical way to avoid the problem is to use the
master-slave (M-S) configuration as discussed below.
Master-Slave J-K Flip-flop
A master-slave (M-S) flip-flop is shown in Figure below. Basically, a master-slave flip-flop is a system of
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

two flip-flops—one being designated as master and the other is the slave. From the figure below we
see that a clock pulse is applied to the master and the inverted form of the same clock pulse is applied
to the slave. When CLK = 1, the first flip-flop (i.e., the master) is enabled and the outputs Qm and Q'm
respond to the inputs J and K according to the truth table of Jk Flip Flop. At this time the second flip-
flop (i.e., the slave) is disabled because the CLK is LOW to the second flip-flop. Similarly, when CLK
becomes LOW, the master becomes disabled and the slave becomes active, since now the CLK to it is
HIGH. Therefore, the outputs Q and Q' follow the outputs Qm and Q'm respectively. Since the second
flip-flop just follows the first one, it is referred to as a slave and the first one is called the master. Hence,
the configuration is referred to as a master-slave (M-S) flipflop.

In this type of circuit configuration the inputs to the gates 5 and 6 do not change at the time of
application of the clock pulse. Hence the race-around condition does not exist. The state of the master-
slave flip-flop, shown in above Figure, changes at the negative transition (trailing edge) of the clock
pulse. Hence, it becomes negative triggering a master-slave flip-flop. This can be changed to a positive
edge triggering flip-flop by adding two inverters to the system—one before the clock pulse is applied to
the master and an additional one in between the master and the slave. The logic symbol of a negative
edge master-slave is shown in Figure below. The system of master-slave flip-flops is not restricted to J-
K master slave only. There may be an S-R master-slave or a D master-slave, etc., in all of them the slave
is an S-R flip-flop, whereas the master changes to J-K or S-R or D flip-flops.
T Flip-flop
With a slight modification of a J-K flip-flop, we can construct a new flip-flop called a T flip-flop. If the
two inputs J and K of a J-K flip-flop are tied together it is referred to as a T flip-flop. Hence, a T flip-flop
has only one input T and two outputs Q and Q'. The name T flip-flop actually indicates the fact that the
flip-flop has the ability to toggle. It has actually only two states—toggle state and memory state. Since
there are only two states, a T flip-flop is a very good option to use in counter design and in sequential
circuits design where switching an operation is required. The truth table of a T flip-flop is given below:-

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

If the T input is in 0 state (i.e., J = K = 0) prior to a clock pulse, the Q output will not change with the
clock pulse. On the other hand, if the T input is in 1 state (i.e., J = K = 1) prior to a clock pulse, the Q
output will change to Q' with the clock pulse. In other words, we may say that, if T = 1 and the device is
clocked, then the output toggles its state. The truth table shows that when T = 0, then Qn+1 = Qn, i.e.,
the next state is the same as the present state and no change occurs. When T = 1, then Qn+1 = Q'n, i.e.,
the state of the flip-flop is complemented. The circuit diagram of a T flip-flop and the block diagram of
the T flip-flop is shown below: -

Characteristic Table of a T Flip-flop

As we have already discussed the characteristic equation of a J-K flip-flop, we can similarly find out the
characteristic equation of a T flip-flop. The characteristic table of a T flip-flop is given below. From the
characteristic table we have to find out the characteristic equation of the T flip-flop Now we will find
out the characteristic equation of the T flip-flop from the characteristic table with the help of the

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Karnaugh map below:-

From the Karnaugh map, the Boolean expression of Qn+1 is derived as Qn+1 = TQ'n + T'Qn., , the
characteristic equation of a T flip-flop.
TRIGGERING OF FLIP-FLOPS
Flip-fl ops are synchronous sequential circuits. This type of circuit works with the application of a
synchronization mechanism, which is termed as a clock. Based on the specific interval or point in the
clock during or at which triggering of the flip-flop takes place, it can be classified into two different
types—level triggering and edge triggering. A clock pulse starts from an initial value of 0, goes
momentarily to 1, and after a short interval, returns to the initial value.
Level Triggering of Flip-flops
If a flip-flop gets enabled when a clock pulse goes HIGH and remains enabled throughout the duration
of the clock pulse remaining HIGH, the flip-flop is said to be a level triggered flip-flop. If the flip-flop
changes its state when the clock pulse is positive, it is termed as a positive level triggered flip-flop. On
the other hand, if a NOT gate is introduced in the clock input terminal of the flip-flop, then the flip-flop
changes its state when the clock pulse is negative, it is termed as a negative level triggered flip-flop. The
main drawback of level triggering is that, as long as the clock pulse is active, the flip-flop changes its
state more than once or many times for the
change in inputs. If the inputs do not change during one clock pulse, then the output remains stable.
On the other hand, if the frequency of the input change is higher than the input clock frequency, the
output of the flipflop undergoes multiple changes as long as the clock remains active. This can be
overcome by using either master-slave flip-flops or the edge-triggered flip-flop.
Edge-triggering of Flip-flops
A clock pulse goes from 0 to 1 and then returns from 1 to 0. The Figure below shows the two transitions
and they are defined as the positive edge (0 to 1 transition) and the negative edge (1 to 0 transition).
The term edge triggered means that the flip-flop changes its state only at either the positive or negative
edge of the clock pulse.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

EXCITATION TABLE OF A FLIP-FLOP

The truth table of a flip-flop is also referred to as the characteristic table of a flip-flop, since this table
refers to the operational characteristics of the flip-flop. But in designing sequential circuits, we often
face situations where the present state(PS) & the next state(NS) of the flip-flop is specified, and we have
to find out the input conditions that must prevail for the desired output condition. By present and next
states we mean to say the conditions before and after the clock pulse respectively. For example, the
output of an S-R flip-flop before the clock pulse is Qn = 1 and it is desired that the output does not
change when the clock pulse is applied.
Now from the characteristic table of an S-R flip-flop, we obtain the following conditions:
1. S = R = 0 (second row)
2. S = 1, R = 0 (sixth row).
We come to the conclusion from the above conditions that the R input must be 0, whereas the S input
may be 0 or 1 (i.e., don’t-care). Similarly, for all possible situations, the input conditions can be found
out. A tabulation of these conditions is known as an excitation table. The table below gives the
excitation table for S-R, D, J-K, & T flip-flops. These conditions are derived from the corresponding
characteristic tables of the flip-flops.

Conversion of an S-R Flip-flop to a D Flip-flop

The excitation tables of S-R and D flip-flops are given below from which we make the truth table given

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

From the above table, we make the Karnaugh maps for inputs S and R as shown in Figure below:-

Simplifying with the help of the Karnaugh maps, we obtain S = D and R = D'. Hence the circuit may be
designed as in Figure below:-

Conversion of an S-R Flip-fl op to a J-K Flip-flop

The excitation tables of S-R and J-K flip-flops, as we studied before, from which we make the truth table
given in below.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

From the above truth table, the Karnaugh map is prepared as shown in Figure below: -

Hence we get the Boolean expression for S and R as

S = JQ' & R = KQ
Hence the circuit may be realized as in below: -

Conversion of a D Flip-flop to an S-R Flip-flop

The excitation tables of S-R and D flip-flops, as we studied before, from which we make the truth table
given in below: -

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

From the above truth table, the Karnaugh map is prepared as shown in Figure above.
Hence, we get the Boolean expression for S and R as: - D = S + R'Q. Hence the circuit may be realized as
in below: -

REGISTERS
A register is a group of binary storage cells capable of holding binary information. A group of flip-flops
constitutes a register, since each flip-flop can work as a binary cell. An n-bit register, has n flip-flops and
is capable of holding n-bits information. In addition to flip-flops a register can have a combinational part
that performs data-processing tasks.
Register:
• A set of n flip-flops
• Each flip-flop stores one bit
• Two basic functions: data storage and data movement.
Shift Register: A register that allows each of the flip-flops to pass the stored information to its adjacent
neighbour.

Basic data movement operation in shift registers

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Shift Register
A shift register is a storage device that used to store binary data. When a number of flip flops are
connected in series it is called a register. A single flip flop is supposed to stay in one of the two stable
states 1 or 0 or in other words the flip flop contains a number 1 or 0 depending upon the state in which
it is. A register will thus contain
a series of bits which can be termed as a word or a byte. If in these registers the connection is done in
such a way that the output of one of the flip flop forms in input to other, it is known as a shift register.
The data in a shift register is moved serially (one bit at a time).
There are two ways to shift data into a register (serial or parallel) and similarly two ways to shift the
data out of
the register. This leads to the construction of four basic types of registers: -
1. Serial in/Serial out (SISO)
2. Serial in/Parallel out (SIPO)
3. Parallel in/Serial out (PISO)
4. Parallel in/Parallel out (PIPO)

Shift-right Register
A shift-right register can be constructed with either J-K or D flip-flops as shown in Figure 8.3. A J-K flip-
flop-based shift register requires connection of both J and K inputs. Input data are connected to the J
and K inputs of the left most (lowest order) flip-flop. To input a 0, one should apply a 0 at the J input,
i.e., J = 0 and K = 1 and vice versa. With the application of a clock pulse the data will be shifted by one
bit to the right. In the shift register using D flip-flop, D input of the left most flip-flop is used as a serial
input line. To input 0, one should apply 0 at the D input and vice versa.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Figure of Shift-right register (a) using D flip-flops, (b) using J-K flip-flops.
The clock pulse is applied to all the flip-flops simultaneously. When the clock pulse is applied, each flip-
flop is either set or reset according to the data available at that point of time at the respective inputs of
the individual flip-flops. Hence the input data bit at the serial input line is entered into flip-flop A by the
first clock pulse. At the same time, the data of stage A is shifted into stage B and so on to the following
stages. For each clock pulse, data stored in the register is shifted to the right by one stage. New data is
entered into stage A, whereas the data present in stage D are shifted out (to the right).

For example, consider that all the stages are reset and a logical input 1011 is applied at the serial input
line connected to stage A. The data after four clock pulses is shown in above Table.
Let us now illustrate the entry of the 4-bit number 1011 into the register, beginning with the right-most
bit. A 1 is applied at the serial input line, making D = 1. As the first clock pulse is applied, flip-flop A is
SET, thus storing the 1. Next, a 1 is applied to the serial input, making D = 1 for flip-flop A and D = 1 for
flip-flop B also, because the input of flip-flop B is connected to the QA output.
When the second clock pulse occurs, the 1 on the data input is “shifted” to the flip-flip-flop A and the 1
in the flip-flop A is “shifted” to flip-flop B. The 0 in the binary number is now applied at the serial input
line, and the third clock pulse is now applied. This 0 is entered in flip-flop A and the 1 stored in flip-flop
A is now “shifted” to flip-flop B and the 1 stored in flip-flop B is now “shifted” to flip-flop C. The last bit

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

in the binary number that is the 1 is now applied at the serial input line and the fourth clock pulse is
now applied. This 1 now enters the flipflop A and the 0 stored in flip-flop A is now “shifted” to flip-flop
B and the 1 stored in flip-flop B is now “shifted” to flip-flop C and the 1 stored in flip-flop C is now
“shifted” to flip-flop D. Thus, the entry of the 4-bit binary number in the shift-right register is now
completed.
From the third column of above Table we can get the serial output of the data that is being entered in
the register. We find that after the first, second, and the third clock pulses the output at the serial
output line i.e., QD is 0. After the fourth clock pulse the output at the serial output line is 1. If we want
to get the total data that we have entered in the register in a serial manner from QD, then we have to
apply another three clock pulses. After the fifth clock pulse we will gate another 1 at QD. After the sixth
clock pulse the output at QD will be 0 and after the seventh clock pulse the output at QD will be 1. In
this process of the fifth, sixth, and the seventh clock pulses if no data is being supplied at the serial input
line then the A, B, and C flip-flops will again be RESET with output 0.

Waveforms of 4-bit serial input shift-right register

Shift-left Register
A shift-left register can also be constructed with either J-K or D flip-flops as shown in Figure below. Let
us now illustrate the entry of the 4-bit number 1110 into the register, beginning with the right-most bit.
A 0 is applied at the serial input line, making D = 0. As the first clock pulse is applied, flip-fl op A is RESET,
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

thus storing the 0. Next a 1 is applied to the serial input, making D = 1 for flip-flop A and D = 0 for flip-
flop B, because the input of flip-flop B is connected to the QA output.
When the second clock pulse occurs, the 1 on the data input is “shifted” to the flip-flop A and the 0 in
the flipflop A is “shifted” to flip-flop B. The 1 in the binary number is now applied at the serial input line,
and the third clock pulse is now applied. This 1 is entered in flip-flop A and the 1 stored in flip-flop A is
now “shifted” to flip-flop B and the 0 stored in flip-flop B is now “shifted” to flip-flop C. The last bit in
the binary number that is the 1 is now applied at the serial input line and the fourth clock pulse is now
applied. This 1 now enters the flipflop A and the 1 stored in flip-flop A is now “shifted” to flip-flop B and
the 1 stored in flip-flop B is now “shifted” to flip-flop C and the 0 stored in flip-flop C is now “shifted” to
flip-flop D. Thus the entry of the 4-bit
binary number in the shift-right register is now completed.

Figure:- Shift-left register (a) using D flip-flops, (b) using J-K flip-flops.

Serial Input Serial Output Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 =
0. If an entry of a four bit binary number 1 1 1 1 is made into the register, this number should be applied
to Din bit with the LSB bit applied first. The D input of FF-3 i.e. D3 is connected to serial data input Din.
Output of FF-3 i.e. Q3 is connected to the input of the next flip-flop i.e. D2 and so on.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Block Diagram

Operation
Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the number to be entered
to Din. So Din = D3 = 1. Apply the clock. On the first falling edge of clock, the FF-3 is set, and stored word
in the register is Q3 Q2 Q1 Q0 = 1000.
Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock hits, FF-2 will set
and the stored word change to Q3 Q2 Q1 Q0 = 1100.
Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third negative clock
edge hits, FF-1 will be set and output will be modified to Q3 Q2 Q1 Q0 = 1110.
Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored word in the register
is Q3 Q2 Q1 Q0 = 1111.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Serial Input Parallel Output In such types of operations, the data is entered serially and taken out in
parallel fashion. Data is loaded bit by bit. The outputs are disabled as long as the data is loading. As soon
as the data loading gets completed, all the flip-flops contain their required data, the outputs are enabled
so that all the loaded data is made available over all the output lines at the same time. 4 clock cycles
are required to load a four bit word. Hence the speed of operation of SIPO mode is same as that of SISO
mode.
Block Diagram

Parallel Input Serial Output (PISO) Data bits are entered in parallel fashion. The circuit shown below is
a four bit parallel input serial output register. Output of previous Flip Flop is connected to the input of
the next one via a combinational circuit. The binary input word B0, B1, B2, B3 is applied though the
same combinational circuit. There are two modes in which this circuit can work namely - shift mode or
load mode.
Load mode
When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active they will pass B1, B2, B3
bits to the corresponding flip-flops. On the low going edge of clock, the binary input B0, B1, B2, B3 will
get loaded into the corresponding flip-flops. Thus parallel loading takes place.
Shift mode
When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive. Hence the parallel
loading of the data becomes impossible. But the AND gate 1,3 and 5 become active. Therefore the
shifting of data from left to right bit by bit on application of clock pulses. Thus the parallel in serial out
operation takes place.
Block Diagram

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Parallel Input Parallel Output (PIPO) In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the
data inputs D0, D1, D2, D3 respectively of the four flip-flops. As soon as a negative clock edge is applied,
the input binary bits will be loaded into the flip-flops simultaneously. The loaded bits will appear
simultaneously to the output side. Only clock pulse is essential to load all the bits. Block Diagram

Counters
Counting is frequently required in digital computers and other digital systems to record the number of
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

events occurring in a specified interval of time. Normally an electronic counter is used for counting the
number of pulses coming at the input line in a specified time period. The counter must possess memory
since it has to remember its past states. As with other sequential logic circuits counters can be
synchronous or asynchronous. As the name suggests, it is a circuit which counts.
Ripple Counter
A counter that follows the binary number sequence is called a binary counter. An n ‐bit binary counter
consists of n flip‐flops and can count in binary from 0 through 2 n - 1. Counters are available in two
categories: ripple counters and synchronous counters. In a ripple counter, a flip‐flop output transition
serves as a source for triggering other flip‐flops. In other words, the C input of some or all flip‐flops are
triggered, not by the common clock pulses, but rather by the transition that occurs in other flip‐flop
outputs. In a synchronous counter, the C inputs of all flip‐flops receive the common clock.
Binary Ripple Counter
A binary ripple counter consists of a series connection of complementing flip‐flops, with the output of
each flip‐flop connected to the C input of the next higher order flip‐flop. The flip‐flop holding the least
significant bit receives the incoming count pulses. A complementing flip‐flop can be obtained from a JK
flip‐flop with the J and K inputs tied together or from a T flip‐flop. A third possibility is to use a D flip‐
flop with the complement output connected to the D input. In this way, the D input is always the
complement of the present state, and the next clock pulse will cause the flip‐flop to complement. The
logic diagram of two 4‐bit binary ripple counters is shown in Fig. below. The output of each flip‐flop is
connected to the C input of the next flip‐flop in sequence.
The flip‐flop holding the least significant bit receives the incoming count pulses. The T inputs of all the
flip‐flops in (a) are connected to a permanent logic 1, making each flip‐flop complement if the signal in
its C input goes through a negative transition. The bubble in front of the dynamic indicator symbol next
to C indicates that the flip‐flops respond to the negative‐edge transition of the input. The negative
transition occurs when the output of the previous flip‐flop to which C is connected goes from 1 to 0.
The count starts with binary 0 and increments by 1 with each count pulse input. After the count of 15,
the counter goes back to 0 to repeat the count.
3-bit Ripple counter using JK flip-flop – Truth Table/Timing Diagram

In the 3-bit ripple counter, three flip-flops are used in the circuit. As here ‘n’ value is three, the counter
can count up to 23 = 8 values.i.e., 000,001,010,011,100,101,110,111. The circuit diagram and timing
diagram are given below.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

3 Bit Asynchronous Down Counter

• For the 3 bit counter, we require 3 flip flops and we can generate 23 = 8 state and
count(111 110 … 000).
• We can generate down counting states in an asynchronous down counter by two ways.

In this implementation, the clock pulse(of 50% duty cycle) is given to only the first FF. Thereafter, the
output of the first FF is feed as a clock to second FF and the output of the second FF is feed as the
clock for the third FF. But the complemented output is taken from each FF(i.e. same as Up counter
but output states are complemented). Here QA is LSB and QC is MSB.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Design of 3 Bit Asynchronous UP/DOWN Counter

It is used more than separate up or down counter.
1. In this a mode control input (say M) is used for selecting up and down mode.
2. A combinational circuit is required between each pair of flip-flop to decide whether to do
up or do down counting.
For n = 3, i.e for 3 bit counter –
Maximum count = 2n -1 and number of states are 2n.
Steps involve in design are :

Step 1 : Decision for Mode control input –

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

When M = 0, then Y= Q, therefore it will perform Up counting (As discussed above).

When M = 1, then Y= Q’ therefore it will perform Down counting (As discussed above).

Combinational circuit is required for deciding mode control (i.e., whether counter will perform Up
counting or Down counting). So, the all-possible combinations are –

K-map for finding output Y that will be given as clock to next FF.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Step 2 : Insertion of Combinational logic between every pair of FFs –

Case 1 – When M=0, then M’ =1.

Put this in Y= M’Q + MQ’= Q So Q is acting as clock for next FFs.
Therefore, the counter will act as Up counter.
Explanation of Up counter
• The 1st FF is connected to logic 1. Therefore, it will toggle for every falling edge.
• The 2nd FF input is connected to Q1. Therefore it changes its state when Q1= 1 and there
is falling edge of clock.
• Similarly, 3rd FF is connected to Q2. Therefore, it changes its state when Q2= 1 and there
is falling edge of clock.
• By this we can generate counting states of Up counter.
• After every 8th falling edge the counter is again reaching to state 0 0 0.
Therefore, it is also known as divide by 8 circuit or mod 8 counter.
Case 2 – When M=1, then M’ =0.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Put this in Y= M’Q + MQ’= Q’. So Q’ is acting as clock for next FFs. Therefore, the counter will act as
Down counter.
Explanation of Down counter
• The 1st FF is connected to logic 1. Therefore, it will toggle for every falling edge.
• The 2nd FF input is connected to Q’1. Therefore, it changes its state when Q’1= 1 and there
is falling edge of clock.
• Similarly, 3rd FF is connected to Q’2. Therefore, it changes its state when Q’2= 1 and there
is falling edge of clock.
• By this we can generate counting states of down counter.
• After every 8th falling edge, the counter is again reaching to state 0 0 0.
• Therefore, it is also known as divide by 8 circuit or mod 8 counter.

Modulus counters

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Synchronous counters
Design 3-bit synchronous up counter using JK flip flops.

Step 1: Find the number of flip flops.

A flip flop stores only one bit, hence for a 3 bit counter, 3 flip flops(n=3) are needed to design the
counter.

Number of states = 2n = 23 = 8 states (000, 001, 010, 011, 100, 101, 110, 111)

Step 2: Choose the type of flip flop.

Since the type of flip flop is given in the problem, let us use JK flip flops.

Step 3: Draw state diagram for the counter.

The state diagram for the counter is drawn as below.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Step 4: Obtain excitation table for the counter.

We know, the excitation table for JK flip flop is given by,

Now the excitation table for the 3-bit synchronous counter is determined from the excitation table of
JK flip flop. The excitation table is framed for 8 states of the counter. Since 3 flip-flops are used in the
design, the present state, next state and flip flop inputs for each flip flop are considered.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Step 5: Derive the flip flop input functions.

Using Karnaugh maps, the input functions for the 3 flip flops are derived. The present states are the
input for all the flip-flops. Since there are three inputs (QC, QB, QA), 8 cell K-map is used.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Step 6: Draw the logic diagram of the counter.

The logic diagram of the 3-bit synchronous counter is drawn as follows. Draw the 3 JK flip-flops. The
common clock pulse input is given to all the flip-flops. The inputs for each flip-flop are drawn as per the
logic functions derived in the previous step.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)

 BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125

[BES 00018] Class Note Applied Digital Logic Design

Explain the finite state machine.

A Finite State Machine (FSM) is a mathematical model of computation used to design both computer
programs and sequential logic circuits. It consists of a finite number of states, transitions between those
states, and inputs that trigger those transitions.

Key Components of a Finite State Machine:

1. States: Distinct modes or conditions in which the system can exist. One of them is the initial
state, and some may be accepting/final states (in the case of automata).
2. Transitions: Rules that determine how the FSM moves from one state to another based on
inputs.
3. Inputs: External signals or values that trigger transitions between states.
4. Outputs (optional): In Mealy and Moore machines, FSMs can also produce outputs:
o Mealy machine: Output depends on both the current state and the input.
o Moore machine: Output depends only on the current state.

2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)