Scribd
Upload
2 views6 pages

HDL report 3

The document contains HDL code for various exercises, including a Mealy zero detector and a state machine implementation. It outlines the structure of modules, state transitions, and the use of D flip-flops in the design. Additionally, it includes testbench code for simulation purposes.

Uploaded by

Mohamed Ahmed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
2 views6 pages

HDL report 3

The document contains HDL code for various exercises, including a Mealy zero detector and a state machine implementation. It outlines the structure of modules, state transitions, and the use of D flip-flops in the design. Additionally, it includes testbench code for simulation purposes.

Uploaded by

Mohamed Ahmed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 6

‫دمحم احمد حمودة‬

HDL report 3

Ex 5.22
a)

0 10 15 20 40 50 70 85

w
b)

Ex 5.23

a) b)
Ex 5 . 27

module Mealy_Zero_Detector (output reg y_out , input x_in , clock, reset );


reg [1: 0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always @ (posedge clock, negedge reset)
if (~reset) state <= S0;
else state <= next_state;
always @ (state, x_in)
case (state)

S0 : begin y_out = 0;
if (x_in) next_state = S1; else next_state = S0;
end

S1 : begin y_out = ~x_in;


if (x_in) next_state = S3; else next_state = S0;
end

S2: begin y_out = ~x_in;


if (~x_in) next_state = S0; else next_state = S2;
end

S3: begin y_out = ~x_in;


if (x_in) next_state = S2; else next_state = S0;
end

endcase
endmodule
Ex 5 . 28
module ex5_28_a (output reg A, input x, y, clk, reset);
parameter S0 = 1’b0, S1 = 1b’1;
reg state, next_state ;
assign A = state ;
always @ (posedge clk , negedge reset)
if (~reset) state <= s0; else state <= next_state;

always @ (state, x, y)

case (state)
S0:
case ({x, y})
2'b00, 2'b11: next_state = S0;
2'b01, 2'b10: next_state = S1;
endcase
S1:

case ({x, y})


2'b00, 2'b11: next_state = S1;
2'b01, 2'b10: next_state = S0;
endcase

endcase
endmodule

module ex5_28_b ( output A , input x , y , clk , reset);

wire y_xor_x , w ;

xor

G1 (y_xor_x , x , y ) , w
G1 G2
Y_xor_x
G2 (w , y_xor_x , A ) ;

DFF (A , w , clk , reset ) ; // D flip flop

endmodule
// rest of exercise 5.28 b
module DFF ( output reg Q , input D , clk , reset ) ;
always @ (posedge clk , negedge reset)

if (~reset) Q <= 0 ; else Q <= D ;


endmodule

module t_ex_5_28_c // testench

wire A1 , A2 ;

reg x , y , clk , reset ;

ex5_28_a Ma (A1 , x , y , clk , reset ) ;

ex5_28_b Mb ( A2 , x , y , clk , reset ) ;

initial #300 $finish;

initial begin clk = 1’b0 ;

repeat (20)

#10 clk = ~clk ;

end

initial fork

#5 reset = 1 ;

begin x = 0 ; y = 0 ; end // 00

#20 y = 1 ; //01

#35 begin x = 1 ; y = 0 ; end // 10

#50 y = 1 ; // 11

#65 reset = 0 ;

begin x = 0 ; y = 0 ; end // 00

#70 y = 1 ; //01

#85 begin x = 1 ; y = 0 ; end // 10

# 100 y = 1 ; // 11

join

endmodule
Ex 5 .30
Ex 5.35

module ex_5_35( output reg z , input x , y , clk , reset ) ;


reg [1:0] state, next_state ; // state = 2’bAB
always @ (state)
assign z = state[1] ; // z = A
parameter S0 = 2’b00 , S1 = 2’b01 , S2 = 2’b10 , S3 = s’b11 ;

always @ (posedge clk , negedge reset )


if (~rest ) state <= S0 ; else state <= next_state ;

always @ (state , x , y )
case (state )
S0:
case ( {x,y})
2’b00 , 2’b01 : next_state = S0 ;
2’b10 : next_state = S3 ;
2’b11 : next_state = S1 ;
endcase

S1 :
State table for circuit of
case ( {x,y}) exercise 5.6
2’b00 , 2’b01 : next_state = S0 ;
2’b10 , 2’b11 : next_state = S2 ;
endcase

S2 :
case ( {x,y})
2’b00 , 2’b01 : next_state = S0 ;
2’b10 : next_state = S3 ;
2’b11 : next_state = S1 ;
endcase

S3 :
case ( {x,y})
2’b00 , 2’b01 : next_state = S0 ;
2’b10 , 2’b11 : next_state = S3 ;
endcase

endcase
endmodule

You might also like