Weekly Report 15 (eInfochips-ASIC)

Task: Scan cell design, Scan architecture

Scan Cell Design:

˃ Scan cells are specialized storage elements used in Design for

Testability (DFT). The primary goal of using scan cells is to improve the
testability of a circuit by making internal states observable. These cells
form a scan chain to shift test data in and out during testing.

Why use Scan cell?

˃ Scan cells simplify the testing of sequential circuits by converting them

into a combinational-like structure for easier fault detection.
˃ They allow for test pattern generation (TPG) and fault diagnosis using
external test equipment.
˃ By applying scan design techniques, manufacturers can ensure high
fault coverage while reducing test time.

Types of Scan cell design:

˃ Muxed-D scan
˃ Clocked-scan
˃ Level-sensitive scan design (LSSD).

Muxed-D scan cell:-

˃ This scan cell is composed of a D flip-flop and a multiplexer. The

multiplexer uses a scan enable (SE) input to select between the data
input (DI) and the scan input (SI).
˃ In normal/capture mode, SE is set to 0. The value present at the data
input DI is captured into the internal D flip-flop when a rising clock
edge is applied.
˃ In shift mode, SE is set to 1. The SI is now used to shift in new data to
the D flip-flop while the content of the D flip-flop is being shifted out.
Clocked scan cell

˃ Structural testing: a more practical approach to select specific test

patterns based on circuit structural information and a set of fault
models. This approach is called structural testing.

˃ Functional testing: If the CUT is an N-input combinational logic circuit

we can apply all 2^n possible input patterns for testing faults.

˃ However, this example of applying all possible input test patterns to an

n-input combinational logic circuit also illustrates the basic idea of
functional testing.

˃ Structural testing: Internal Structure and connectivity

˃ Functional testing: Functional behavior and operational correctness

Level Sensitive Scan Design (LSSD) scan cell:-

˃ While muxed-D scan cells and clocked-scan cells are generally used for
edgetriggered, flip-flop-based designs, an LSSD scan cell is used for
level-sensitive, latch-based designs.
˃ This scan cell contains two latches, a master two-port D latch L1 and a
slave D latch L2. Clocks C, A, and B are used to select between the
data input D and the scan input I to drive +L1 and +L2.
˃ In order to guarantee race-free operation, clocks A, B, and C are
applied in a nonoverlapping manner.
˃ In designs where +L1 is used to drive the combinational logic, the
master latch L1 uses the system clock C to latch system data from the
data input D and to output this data onto +L1.
˃ In designs where +L2 is used to drive the combinational logic, clock B
is used after clock A to latch the system data from latch L1 and to
output this data onto +L2.
˃ Capture mode uses both clocks C and B to output system data onto
+L2.
˃ In shift mode, clocks A and B are used to latch scan data from the scan
input I and to output this data onto +L1 and then latch the scan data
from latch L1 and to output this data onto +L2, which is then used to
drive the scan input of the next scan cell.
˃ The major advantage of using an LSSD scan cell is that it allows us to
insert scan into a latch-based design.
Scan Architecture:

˃ Scan Architecture refers to the design and implementation of scan

chains within a digital circuit.
˃ A scan chain is a series of connected scan flip-flops (scan cells) that
allow test patterns to be shifted into the circuit and test results to be
shifted out.
˃ It effectively converts sequential circuits into a form that can be tested
like a combinational circuit during test mode.
˃ There are 3 types of scan architecture:
 Full scan design
 Partial scan design
 Random-access scan design

Full Scan Design

˃ In full-scan design, all storage elements are replaced with scan cells,
which are then configured as one or more shift registers (also called
scan chains) during the shift operation.
 ˃ As a result, all inputs to the combinational logic, including those driven
by scan cells, can be controlled and all outputs from the combinational
logic, including those driving scan cells, can be observed.

˃ The main advantage of full-scan design is that it converts the difficult

problem of sequential ATPG into the simpler problem of combinational
ATPG.

˃ There are 3 types of full scan design:

 Muxed-D full scan design
 Clocked full scan design
 LSSD full scan design

Muxed-D full scan design:-

 ˃ In shift mode, SE is set to 1, and the scan cells operate as a single scan
chain, which allows us to shift in any combination of logic values into
the scan cells.
˃ In capture mode, SE is set to 0, and the scan cells are used to capture
the test response from the combinational logic when a clock is applied.
˃ In general, combinational logic in a full-scan circuit has two types of
inputs: primary inputs (PIs) and pseudo primary inputs (PPIs). Primary
inputs refer to the external inputs to the circuit, while pseudo primary
inputs refer to the scan cell outputs.
˃ Similarly, the combinational logic in a full-scan circuit has two types of
outputs: primary outputs (POs) and pseudo primary outputs (PPOs).
Primary outputs refer to the external outputs of the circuit, while
pseudo primary outputs refer to the scan cell inputs.

Clocked Full-Scan Design

˃ This clocked full-scan circuit is tested using shift and capture

operations, similar to a muxed-D full-scan circuit.
˃ These two operations are distinguished by properly applying the two
independent clocks SCK and DCK during shift mode and capture mode,
respectively.
LSSD Full-Scan Design

˃ It is possible to implement LSSD full-scan designs, based on the

polarity-hold SRL design, using either a single-latch design or a double-
latch design.
˃ In single-latch design, the output port +L1 of the master latch L1 is
used to drive the combinational logic of the design. In this case, the
slave latch L2 is used only for scan testing.
˃ In this case, combinational logic driven by the master latches of the
first system clock C1 are used to drive the master latches of the
second system clock C2, and vice versa.
˃ In order for this to work, the system clocks C1 and C2 should be
applied in a nonoverlapping fashion.
˃ In LSSD double-latch design, in normal mode, the C1 and C2 clocks are
used in a nonoverlapping manner, where the C2 clock is the same as
the B clock.
˃ The testing of an LSSD full-scan circuit is conducted using shift and
capture operations, similar to a muxed-D full-scan circuit.

Partial Scan Design

 ˃ Partial Scan is a testability technique where only a subset of flip-flops is
included in the scan chain, unlike Full Scan, where all sequential
elements are included.
˃ This helps balance testability, area, and performance.
˃ The primary goal is to improve testability while reducing hardware
overhead, performance degradation, and test pattern generation
complexity.
˃ The three main techniques used in Partial Scan are:
1. Functional Partitioning Approach
2. Pipelined or Feed-Forward Partial Scan
3. Balanced Partial Scan

Functional Partitioning Approach

˃ In the functional partitioning approach, a circuit is viewed as being

composed of a data path portion and a control portion.
˃ Typically, because storage elements on the data path portion cannot
afford too much delay increase, especially when replaced with muxed-
D scan cells, they are left out of the scan cell replacement process.
˃ On the other hand, storage elements in the control portion can be
replaced with scan cells.
˃ This approach makes it possible to improve fault coverage while
limiting the performance degradation due to scan design.

Pipelined or Feed-Forward Partial Scan

˃ This technique removes all feedback loops in a sequential circuit by

converting selected storage elements into scan cells.
˃ The process transforms the Directed Cyclic Graph (DCG) of a
sequential circuit into a Directed Acyclic Graph (DAG), effectively
making the design feedback-free.
˃ Implementation:
1. Structure Graph Construction
 The circuit is represented as a graph, where vertices correspond to
storage elements, and directed edges represent combinational logic
paths.
 If the graph has cycles, it means the circuit has sequential feedback
loops that increase ATPG complexity.
2. Breaking Feedback Loops
 Flip-flops within feedback loops are selected and replaced with scan
cells to eliminate cyclic dependencies.
 The goal is to maintain minimal scan insertion while achieving a
feedback-free structure.
Balanced Partial Scan

˃ In the balanced partial-scan design approach, a target sequential depth

is used to further simplify the test generation process for the pipelined
or feed-forward partial-scan design.
˃ In this approach, additional vertices are removed from the structure
graph by replacing their corresponding storage elements with scan
cells so the target sequential depth is met.
˃ By keeping the sequential depth under a small limit, one can apply
combinational ATPG using multiple time frames to further increase the
fault coverage of the design.