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This document describes a Verilog module for a single-port RAM with a clock input, write enable signal, address input, and data input/output. The RAM has a size of 16x8 bits and allows writing data to a specified address or reading data from it based on the write enable signal. The RAM operation is triggered on the positive edge of the clock signal.

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Shah Henisha
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1 views

Spr

This document describes a Verilog module for a single-port RAM with a clock input, write enable signal, address input, and data input/output. The RAM has a size of 16x8 bits and allows writing data to a specified address or reading data from it based on the write enable signal. The RAM operation is triggered on the positive edge of the clock signal.

Uploaded by

Shah Henisha
Copyright
© © All Rights Reserved
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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module single_port_ram (

input wire clk,


input wire wr_enable,
input wire [3:0] addr,
input wire [7:0] w_data,
output reg [7:0] r_data
);
reg [7:0] ram [15:0]; // 16x8 RAM

always @(posedge clk) begin


if (wr_enable)
ram[addr] <= w_data;
else
r_data <= ram[addr];
end
endmodule

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