MODULE 2:

EMBEDDED SYSTEM
INTERFACING AND
PERIPHERALS
 Topics:
2

Communication devices
Serial Communication Standards and Devices
UART, HDLC and SPI.
Serial Bus Protocols
I2C Bus, CAN Bus and USB Bus (self-study).
Parallel communication standards
ISA, PCI and PCI-X Bus.
 Topics:
3

Memory devices and systems

ROM – Flash, EEPROM,
RAM – SRAM, DRAM,
Cache memory,
Memory mapping and addresses,
Memory management unit – DMA.
 Topics:
4

I/O Devices
Interrupts – Interrupt sources, recognizing an
interrupt,
ISR – Device drivers for handling ISR, Shared
data problem, Interrupt latency.
 References:
5

◻ Raj Kamal, Embedded Systems Architecture,

Programming and Design.
◻ K.V. Shibu, Introduction to Embedded Systems.
◻ Wayne Wolf, Computers as Components:
Principles of Embedded Computing System
Design.
◻ Online.
 What is a Bus in ES?
6

◻ A data connection between two or more

devices connected to the computer
◻ Used to connect major components
CPU
DMA {Direct memory access}
Memory modules
Peripheral devices, etc.
◻ Can be synchronous or asynchronous
 Synchronous bus
7

◻ Transmitter and receivers are synchronized of clock.

◻ Data bits are transmitted with synchronization of
clock.
◻ Devices should be at same speed.
◻ Character is received at constant Rate.
◻ Data transfer takes place in block.
◻ Used in high-speed transmission.
 Asynchronous bus
8

◻ Transmitters and receivers are not synchronized by

clock.
◻ Connect many devices with varying speeds
◻ Character may arrive at any rate at the receiver.
◻ Data transfer is character oriented.
◻ Start and stop bits are required to establish
communication of each character.
◻ Used in low-speed transmission.
 Different Buses
9

◻ Buses that work in sync with CPU and system clock

are called the local buses or system buses.
◻ Buses that work asynchronously with the CPU are
called the expansion buses.
Eg. The memory bus is a local bus while the ISA bus is
an expansion bus.
 What Does a Bus carry?
10

◻ Electrical Power.

◻ Control Signals.

◻ Memory Address.

◻ Data.
 Bus Communication for
11
networking
◻ Bus communication simplifies the number of
connections and provides a common way (protocol)
of connecting different or same type of I/O devices
 IO Bus
12

◻ I/O devices communicate with the processor

through an I/O bus, which is separate from the
memory bus that the processor uses to
communicate with the memory system.

◻ A bus has a fixed bandwidth that must be shared by

all the devices on the bus.
 Serial Bus
13

◻ Data is transmitted sequentially, one bit at a time,

over a single wire or pair of wires.
◻ Typically, slower for short distances compared to
parallel buses.
◻ Suitable for long-distance communication due to
reduced signal degradation and interference.
I²C, SPI, USB, RS-232,…
 Parallel Bus
14

◻ Multiple bits are transmitted simultaneously over

multiple wires.
◻ Shorter distances due to increased signal
interference with more wires.
◻ Make the system more complex and expensive.
PCI, SCSI (Small Computer System Interface), …
Local Bus
◻ A set of parallel
conductors, which
allow devices attached
to it to communicate
with the CPU.
◻ The bus consists of
three main parts:
Control lines, Address
lines, Data lines
 Bus Communication
16
Advantages
◻ It is easy to connect a device to the network.
◻ It is cheaper than other network options.
◻ The failure of one station does not affect the rest of
the network.
◻ No hubs or switches are required.
◻ Extensions can be made to the network.
◻ Multiple nodes can be installed without difficulty.
 Serial communication

17 Ref:- Raj Kamal, Embedded Systems Architecture, Programming and

Design
 Serial bus protocols
18

◻ I2C Bus – Inter-Integrated Circuit

◻ CAN Bus – Controller Area Network

◻ USB Bus – Universal Serial Bus

 Parallel communication

19
Ref:- Raj Kamal, Embedded Systems Architecture, Programming and
 Parallel communication standards
20

◻ ISA bus – Industry Standard Architecture

◻ EISA bus – Extended Industry Standard

Architecture

◻ PCI bus – Peripheral Component Interconnect

◻ PCI-X bus – Peripheral Component Interconnect

eXtended
 Serial Communication Standards
21
and Devices
Simplex, half-duplex, full-duplex
For parallel data transfer, data rate is bytes/sec &
for serial data communication it is bits/sec
Synchronous, Asynchronous & Isochronous
Transmission
 Simplex, half-duplex, full-duplex

22
 Serial & Parallel Transfer

23
 Synchronous & Asynchronous
Transmission

Fig: Synchronous
Transmission

24
Fig: Asynchronous
 Synchronous Transmission
• Efficiency is
comparatively very
high.
• Speed of data
transmission is very
high.
• No need to transmit
start and stop bit.
• In case of transmitting a
lot of data, this method
• Primary storage device is required.
is suitable.
• Comparatively expensive.
• Synchronization between the source and target is
25
required.
 Asynchronous Transmission
◻ No synchronization is
required between the
transmitter and receiver
devices. Sender can
directly transmit data, and
the receiver can receive
that data.
◻ The sender does not require
any primary storage device.
◻ Cost is very low to
implement this method.
◻ It is convenient while
• Data transmission speed is very transmitting a little amount
low.
of data.
• Efficiency is comparatively less.
26
 Isochronous Transmission
27

◻ Data is sent in a steady, time-dependent manner,

ensuring that information is delivered at regular
intervals.
◻ It is commonly used for time-sensitive applications,
such as audio, video, and real-time communications,
where maintaining consistent timing between data
packets is critical.
E.g. – USB (Universal Serial Bus); USB microphone or
webcam where data must be delivered continuously
without delay.
Voice over IP (VoIP), Streaming Applications,
Telecommunications
 Serial Communication Standards
28
and Devices
◻ UART - Universal Asynchronous
Receiver/Transmitter

◻ HDLC - High-level Data Link Control

◻ SCI - Serial Connect Interface

◻ SPI - Serial Peripheral Interface

SERIAL
COMMUNICATION
STANDARDS AND
DEVICES
UART, HDLC, SCI and SPI
 Bit rate & Baud rate
30

◻
 Bit rate & Baud rate
31

◻ Bit rate is also defined as per second travel number of

bits.
◻ It counts the number of bits traveled per second such as
Kbps, Mbps, Gbps, etc.

◻ Baud rate is also defined as per second number of

changes in signal.
◻ Baud Rate is used to determine the amount of
bandwidth required for signal transmission.
◻ It counts how many times the state of a signal is
changing.
 Bit rate & Baud rate
32

For example:
◻ A figure of 2400 bits per second means 2400 zeros

or ones can be transmitted in one second, hence the

abbreviation “bps”.
◻ A 2400 baud rate means that the channel can

change states up to 2400 times per second. Change

state refers to the actual state of the connection
(such as voltage, frequency, or phase level).
33
UART [Universal Asynchronous
Receiver/Transmitter]
K.V. Shibu, Introduction to Embedded Systems
Rajkamal, Embedded Systems Architecture,
Programming and Design
 Universal Asynchronous Receiver/
34
Transmitter
◻ UART uses only two wires to transmit data between devices.
◻ The transmitting UART converts parallel data into serial
form.
◻ Receiving UART, converts the serial data into parallel data.
◻ UARTs transmit data asynchronously.
◻ UART can operate in half duplex mode or full duplex mode,
depending upon the number of buffers used.
 Universal Asynchronous Receiver/
35
Transmitter
◻ UART reads the incoming bits at a
specific frequency known as the baud rate.

◻ Baud rate is a measure of the speed of data

transfer, expressed in bits per second (bps).

◻ Both UARTs must operate at about the same baud

rate.
 UART

36
 Data frame of UART
37
 Data frame of UART
38
 Configured to transmit and receive
39

◻ Both UARTs must also must be configured to

transmit and receive the same data packet structure.
 Steps of UART transmission
40

1. The transmitting UART receives data in parallel

from the data bus:
 Steps of UART transmission…
41

2. The transmitting UART adds the start bit, parity

bit, and the stop bit(s) to the data frame:
 Steps of UART transmission…
42

3. The entire packet is sent serially from the transmitting

UART to the receiving UART. The receiving UART
samples the data line at the pre-configured baud rate:
 Steps of UART transmission…
43

4. The receiving UART discards the start bit, parity

bit, and stop bit from the data frame:
 Steps of UART transmission…
44

5. The receiving UART converts the serial data back into

parallel and transfers it to the data bus on the receiving
end:
 Usage of UART
45

◻ Microcontroller Communication:
Communication between a microcontroller (like
Arduino or STM32) and a sensor, display, or other
peripheral devices.
◻ Debugging:
Using UART to output debugging information from a
microcontroller to a PC terminal, such as Arduino
Serial Monitor.
◻ Embedded Systems:
UART is commonly used in embedded systems for
interfacing components such as GPS modules,
Bluetooth modules, or GSM modems.
 Usage of UART
46

◻ PC Peripherals:
Connecting legacy peripherals like mice, modems, or
printers to a computer.
◻ Data Communication:
Communication between two microcontrollers for
exchanging data like sensor readings or control
commands.
◻ IoT Applications:
Connecting an ESP8266 or ESP32 Wi-Fi module to a
microcontroller using UART for wireless
communication in IoT projects.
 UART Example
47

◻ IoT Weather Monitoring System

• A microcontroller communicates with a GSM module
via UART to send temperature and humidity readings
to a remote server.
• Transmit Line (TX): Sends sensor data from the
microcontroller to the GSM module.
• Receive Line (RX): Receives acknowledgment or control
messages from the GSM module to the microcontroller.
• Baud Rate: Configured to match on both devices, such as
9600 bits per second.
 Advantages of UART
48

◻ Only uses two wires

◻ No clock signal is necessary
◻ Has a parity bit to allow for error checking
◻ The structure of the data packet can be changed as
long as both sides are set up for it
◻ Well documented and widely used method
 Disadvantages of UART
49

◻ The size of the data frame is limited to a maximum

of 9 bits
◻ Doesn’t support multiple slave or multiple master
systems
◻ The baud rates of each UART must be within 10%
of each other
50
51
HDLC (High-Level Data Link
Control)
Data Link control, Module 3, IIT Kharagpur
Rajkamal, Embedded Systems Architecture,
Programming and Design
 HDLC (High-Level Data Link
52
Control)
HDLC features
1. It is most widely accepted protocol. It offers a

high level of flexibility, adaptability, reliability and

efficiency.
2. Full duplex communication is possible.

3. It is Bit-oriented protocol i.e., use bits to stuff

flags occurring in data.

4. Flow control - adjust window size based on

receiver capability. Prevents data loss.

 HDLC (High-Level Data Link
53
Control)
◻ Standardized by the International Organization for
Standardization (ISO) under the ISO 3309 and ISO
4335 standards.
◻ HDLC has been widely adopted in various network
protocols and technologies, including ISDN
(Integrated Services Digital Network), PPP
(Point-to-Point Protocol).
◻ It provides reliable data transfer, efficient error
detection, and flow control, making it suitable for a
range of communication applications.
 Usage of HDLC:
54

WAN Protocol:
HDLC is extensively used in Wide Area Network (WAN)
communication for encapsulating data over serial links.
Routers in a WAN using HDLC to transmit data across leased
lines.
Telecommunications:
Used in telecom networks for communication between
exchanges and equipment.
HDLC is employed in ISDN (Integrated Services Digital
Network) and X.25 protocols.
Embedded Systems:
Facilitates communication between embedded devices in
industrial and automotive applications.
Used for reliable data transfer between controllers in a factory
automation system.
 HDLC Example:
55

◻ HDLC in a Router-to-Router Communication

• Scenario: Two routers in a WAN are connected via
a leased line.
• HDLC frames encapsulate the data packets being
transmitted.
• The receiving router verifies the integrity of frames
using error detection mechanisms in HDLC.
• Flow control ensures no data is lost during
transmission, even if one router temporarily cannot
process incoming data.
 HDLC Overview
◻ Defines three types of stations
Primary
Secondary
Combined
◻ Defines three types of data transfer mode
Normal Response mode [NRM]
Asynchronous Response mode [ARM]
Asynchronous Balanced mode [ABM]
◻ Three types of frames
Unnumbered or U-frame
Information or I-frame
Supervisory or S-frame
56
 HDLC – station configuration
57
 HDLC - Configuration
58

◻ HDLC also defines three types of configurations

for the three types of stations.
◻ The word configuration refers to the relationship
between the hardware devices on a link. Following
are the three configurations defined by HDLC:
Unbalanced Configuration
Balanced Configuration
Symmetrical Configuration
 Unbalanced Configuration
59

One station
controls the
other stations

Full-Duplex or Half-Duplex operation

Point to Point or Point to Multi-point networks
 Balanced Configuration
60

Full - Duplex or Half-Duplex operation

Peer-to-peer, with no strict master/slave relationship
Point to Point networks
 Symmetrical Configuration
61

◻ Not widely in use today.

Primary and secondary stations can alternate depending on the

context of the communication.
Communication between two nodes in a network where roles are
negotiated dynamically based on the data transfer direction.
 HDLC - Configuration
62

Configuration Primary/Secondar Example Usage

y Relationship
Unbalanced One primary station Point-to-multipoint
controls one or more connections.
secondary stations.
Balanced All stations have Point-to-point WAN
equal roles; links.
peer-to-peer
communication.
Symmetrical Stations can Dynamic node
alternate between communication.
primary and
secondary roles.
 HDLC Operational Modes
◻ Normal Response Mode (NRM)
Just an acknowledgment of a frame. NRM is only used
within an unbalanced configuration.
◻ Asynchronous Response Mode (ARM)
Secondary stations can initiate communication without
explicit permission from the primary station.
◻ Asynchronous Balanced Mode (ABM)
Fully symmetric mode, each station can function as both
the primary station and the secondary station.
◻ Point-to-point configurations often use NRM or ARM, while multipoint
configurations typically employ ABM to facilitate communication among
multiple stations.
63
 HDLC Operational Modes
64

Feature NRM ARM ABM

Primary and Primary and Peer-to-peer
Role of Stations
secondary secondary (equal roles)
Initiation of Only the Secondary can
Any station
Communicatio primary initiate
can initiate
n station occasionally
Point-to-mult Point-to-multip
Topology Point-to-point
ipoint oint
Legacy Modern
Usage mainframe Rarely used networks (e.g.,
systems WAN routers)
 Normal Response Mode(NRM)
65
 Asynchronous Balance
66
Mode(ABM)
 HDLC frame structure
67

FCS – Frame Check Sequence

Field
 Size of different fields
Field Name Size(in bits)
◻ Flag Field 8 bits
◻ Address Field 8 bits
◻ Control Field 8 or 16 bits
◻ Information Field or data Variable; Not used
in some frames
◻ Frame Check Sequence(FCS ) 16 or 32 bits
◻ Closing Flag Field 8 bits

68
 HDLC – Control field
format

69
 Three different classes of frames
70
used in HDLC
◻ Unnumbered frames, used for exchanging session
management and control information between
communicating devices.
◻ Information frames, which carry actual information. If
the first bit in control field is 0 it is identified as
I-frame.
◻ Supervisory frames, which are used for error and flow
control purposes and hence contain send and receive
sequence numbers. If first two bits of control field are 1
and 0 it is identified as S-frame.
 HDLC – Control field format
71

Poll/Final Bit (P/F)

◻ Recognized when it is set to 1, if set to 0 it is

ignored.
◻ Provide dialogue between the primary station and
secondary station.
Frame check Sequence field
◻ 16-bit or 32-bit cyclic redundancy check bits.

◻ Used for error detection.

 HDLC – Control field format
72

S-Frame
◻ Four types of S-frames are possible corresponding to
four values of ‘S’
◻ SS=00 corresponds to Receive Ready (RR) frames.
◻ SS=01 Reject (REJ) is used to request the
retransmission of frames.
◻ SS=10 corresponds to Receive not Ready (NRN)
frame and is used for flow control.
◻ SS=11 Selective Reject (SREJ) is used by a station
to request retransmission of specific frames.
 HDLC – Control field format
73

Unnumbered Format Commands and responses

(U-Frame)
◻ Used to extend the number of data link control
functions.
◻ Frames have 5 modifier bits,

Which allow for up to 32 additional commands and 32

additional response functions.
13 command functions and 8 response functions are
there.
74
SPI (Serial Peripheral Interface)

K.V. Shibu, Introduction to Embedded Systems

Rajkamal, Embedded Systems Architecture,
Programming and Design
 SPI - Serial Peripheral Interface
SD card modules, RFID card reader modules, and 2.4 GHz
wireless transmitter/receivers all use SPI to communicate with
microcontrollers.
◻ SCLK — Serial
Clock
◻ MOSI — Master
Output, Slave
Input
◻ MISO — Master
Input, Slave
Output
◻ SS/CS — Slave
Select/Chip Select
75
 SPI - Data Transmission
76

Shift register
• Size – multiple of 8
• Data in & out
• LS/MS bit configuration register
 SPI - Data Transmission
77

Data Transmission (Full-Duplex)

• On each clock pulse:
• Data is transmitted from the master to the slave via
MOSI.
• Data is transmitted from the slave to the master via
MISO.
• The shift registers in both devices simultaneously
shift out data (MOSI) and shift in data (MISO), bit by
bit.
Data Format
•Data is sent in frames (usually 8 bits, but configurable).
•Transmission is determined by the SPI mode (clock polarity
and phase).
 Animation 1 shows data shifted out of Microchip A into
Microchip B, and from Microchip B into Microchip A.

Animation 2 shows a virtual 4-channel oscilloscope trace of an SPI

transaction between two microchips. Created with Mathematica by
Mark Hughes
78
 Multislave SPI configuration
79
 Daisy-Chain Method
80
 Multislave
Feature Daisy-Chain Method
Configuration
Each slave has its own
Wiring Single CS line for all slaves.
CS line.
Master Pin Increases with the Minimal; one CS pin
Usage number of slaves. required.
Limited by the number
Scalability Highly scalable.
of CS pins.
Latency increases with the
Latency No additional latency.
number of slaves.
Simple to manage and More complex due to data
Complexity
debug. shifting.
Slave Independent operation Failure of one slave affects
Dependency of slaves. others.
Application Suitable for Suitable for interconnected
81Suitability independent devices. devices or chained data.
 SPI Modes of Operation
82

◻ Master device to generate the clock signal and

distribute it to the slave to synchronize the data
between master and slave.
◻ Master and slave have to agree on certain
synchronization protocols.
two features of the clock i.e., the Clock Polarity (CPOL or
CKP) and Clock Phase (CPHA).
◻ Clock Polarity (CPOL) determines the
state/polarity of the clock.
◻ Clock Phase (CPHA) determines the clock
transition i.e., rising (LOW to HIGH) or falling
(HIGH to LOW), at which the data is transmitted.
 SPI Modes of Operation
83

◻ Clock generated by the Master

◻ CPOL = 0 (LOW); SCK is LOW when idle and
toggles to HIGH during active state (during a
transfer).
◻ CPOL = 1 (HIGH); SCK is HIGH during idle and
LOW during active state.
◻ CPHA = 0; the data is sampled on the rising edge of
the clock.
◻ CPHA = 1; Data is sampled on the falling edge.
 SPI Modes of Operation
84

CPOL CPHA Data

SPI Data
(Clock (Clock Shifting
Mode Sampling
Polarity) Phase) Out
Falling
Mode 0 0 (Idle Low) 0 Rising Edge
Edge
Falling Rising
Mode 1 0 (Idle Low) 1
Edge Edge
1 (Idle Falling Rising
Mode 2 0
High) Edge Edge
1 (Idle Falling
Mode 3 1 Rising Edge
High) Edge
 Usages of SPI
Sensor Interfacing
Interface sensors with microcontrollers or processors.
A temperature sensor (e.g., MAX6675) communicating temperature
data to a microcontroller in a smart thermostat.
Memory Devices
Interfacing non-volatile memory devices like EEPROMs, Flash
memory, and SD cards.
An SD card storing data in a data logger application using SPI
communication.
Display Modules
Connects microcontrollers to graphical or character-based
displays.
An OLED display module (e.g., SSD1306) connected to a
microcontroller for displaying graphical information in a wearable
85 device.
 Usages of SPI
Motor Control
For interfacing motor driver ICs.
A DRV8711 motor driver IC controlled by a microcontroller
using SPI in an industrial robotic arm.
Audio Applications
For streaming audio data between devices.
An audio codec chip (e.g., TLV320) communicating with a
microcontroller in a digital audio player.
Gaming Devices
Connects gaming controllers and peripherals to the main
processor.
Interfacing a joystick module with a microcontroller in a
gaming console.
86
 Example: SPI-Based Data Logger
87

▪ A data logger for monitoring environmental

conditions is designed using SPI-based
components:
▪ Microcontroller: Acts as the SPI master.
▪ Temperature Sensor: A MAX31855 thermocouple
sensor provides temperature readings.
▪ SD Card Module: Stores the temperature data.
▪ OLED Display: Displays real-time temperature
readings.
 Advantages of Using SPI
88

o Simplicity: Relatively easy to implement and use.

o Speed: Can achieve high data transfer rates.
o Full-duplex: Allows for simultaneous transmission
and reception of data.
o Flexibility: Supports various clocking modes and
data formats.
 Disadvantages of SPI
89

o Requires More Pins for Multiple Slaves.

o No Built-In Error Checking or Acknowledgment.
o Short Communication Range.
o Signal Complexity for Multiple Slaves.
 Aspect UART SPI HDLC
Communicatio
Asynchronous Synchronous Synchronous
n Type
Full/Half Half-duplex or
Full-duplex Full-duplex
Duplex Full-duplex
Clock Signal Not required Required Required
4 or more
2 or more (Data
Data Lines 2 (Tx, Rx) (MOSI, MISO,
and Clock lines)
SCLK, CS)
Transmission Point-to-point
Point-to-point Master-slave
Mode or multipoint
Low to
High (tens of Moderate to
Speed moderate (up to
Mbps) high
90 a few Mbps)
Aspect UART SPI HDLC
No built-in error Cyclic
Error Parity bit, frame
detection Redundancy
Detection error detection
(software-based) Check (CRC)
Frames with No predefined Frames with flags,
Data Format start and stop format (depends address, control,
bits (e.g., 8N1) on application) and CRC
Limited to one Scalable with Scalable with
Scalability device per pair multiple CS lines multipoint
of lines or daisy-chaining capability
Complexity Simple Moderate More complex
Minimal for
Wiring Increases with point-to-point,
Minimal
Requirements multiple slaves more for
multipoint
Power
91
Low Moderate to high Moderate
 Protocol Typical Devices Applications
Microcontrollers, Debugging,
UART GPS modules, low-speed
Bluetooth modules communication
EEPROMs, flash High-speed data
SPI memory, sensors, acquisition, real-time
displays systems
Routers, industrial WAN
HDLC controllers, SCADA communication,
systems industrial automation
92