Scribd
Upload
16 views

Timing Issues

The document discusses timing issues in sequential circuits, focusing on synchronous and asynchronous design approaches. It explains concepts such as clock skew, clock jitter, and their impacts on circuit performance, along with sources of these timing variations. Additionally, it outlines design techniques to mitigate skew and jitter for improved circuit reliability.

Uploaded by

yuvaraj6cuber
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
16 views

Timing Issues

The document discusses timing issues in sequential circuits, focusing on synchronous and asynchronous design approaches. It explains concepts such as clock skew, clock jitter, and their impacts on circuit performance, along with sources of these timing variations. Additionally, it outlines design techniques to mitigate skew and jitter for improved circuit reliability.

Uploaded by

yuvaraj6cuber
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 19

Timing Issues

E.Margaret Belsia
Timing Issues
• All sequential circuits have a well-defined switching events.
• The systemic switching ensure the circuit to be functional
correctly.
Synchronous approach
• All the circuit elements will be simultaneously updated with
the global clock.
• Functionality ensure by the constraints of clock generation
and proper distribution.

Asynchronous approach
• No global distributed clock is required.
• However these protocol results in increased complexity
Synchronous Design

• A synchronous signal is one that has the exact same


frequency as local clock, and maintains a fixed phase offset
with respect to the local clock
• In such a timing methodology, the signal is “synchronized”.
• With the clock, data can be sampled directly without any
uncertainty.
• Most straight forward type of interconnect
Propagation delay and contamination Delay
Synchronous Design
Clock Skew
• The spatial variation in arrival time of a clock transition on an integrated circuit is
commonly referred to as clock skew
Positive skew occurs when the transmitting register receives the clock tick earlier than
the receiving register.
Negative skew is the opposite: the receiving register gets the clock tick earlier than the
sending register.
Zero clock skew refers to the arrival of the clock tick simultaneously at transmitting
and receiving register.
Clock Skew
• Clock skew between two points i and j on a IC is given by δ (i,j) = ti - tj , where, ti
and tj are the position of the rising edge of the clock with respect to a reference
• Clock skew is caused by static path-length mismatches in the clock load and by
definition skew is constant from cycle to cycle

Positive clock skew


The rising clock edge is delayed by a positive δ at the second register.
Positive clock skew
• If the clock skew is positive, the time
available for signal to propagate from R1
to R2 is increased by the skew δ.
• The constraint on the minimum clock period
can then be derived as:

• if the minimum delay of the


combinational logic block is small, the
inputs to R2 may change before the clock
edge 2, resulting in incorrect evaluation.
• The constraint of the minimum propagation
delay through the register and logic would
be
Negative Clock Skew
• The rising edge of CLK2 happens
before the rising edge of CLK1.
• Here δ is negative,
• The constraint on the minimum
clock period becomes more
stringent
Clock jitter
• defined as “deviation of a clock edge from its ideal location.”

• Clock jitter refers to the temporal variation of the clock period at a given
point and clock period can reduce or expand on a cycle-by-cycle basis.

Tjitter,i(n) = Ti , n+1 - Ti,n - TCLK


• where Ti,n is the clock period for period n,
• T i,n+1 is clock period for period n+1,
• TCLK is the nominal clock period
Circuit performance under Clock jitter
• Clock jitter impacts the performance of a sequential system.
• Ideally the clock period starts at edge 2and ends at edge 5 with clock
period of TCLK.

• The total time available to complete the operation is reduced by 2 tjiiter in


the worst case.
Impact of Clock Skew and Clock Jitter
• ideal clocks are distributed to both registers (the clock period is identical
every cycle and the skew is 0).
Impact of Clock Skew and Clock Jitter
A static skew δ is present in two clock signals (CLK1 and CLK2).
(δ >0).
• CLK1 has jitter of tjitter1.
• CLK2 has jitter of tjitter2.
• The constraint on the minimum clock period -
Source of Skew and Jitter
• A ideal clock signal can not be achieved because of the variety of the process and
environmental variations.
• Off chip or on-chip generated clock signal is distributed through multiple “matched”
path.
• Errors can be classified in to two categories :
1) Systematic Error
• Predictable.
• Identical in chip to chip
• Modeled and corrected at design time.
2) Random Error
• Manufacturing variations
• Difficult to model and eliminate
• e.g., dopant fluctuations
Source of Skew and Jitter
1. Clock generation
• Source of clock generator itself causes jitter.
• Core of a PLL is a Voltage Control Oscillator- which is very sensitive to
the device noise and supply variation.
• Analog circuits are affected by noisy digital circuits.
• Cycle-to-cycle clock variation due to substrate noise.
2. Manufacturing Device Variations
• Mismatch among the clock buffer circuits in the distributed network.
• Because of the process variations, device parameters in buffer circuits
vary –results static skew error.
• Variation in oxide layer, dopant profile, dimension ratio affect the over
all performance
Source of Skew and Jitter
3. Mismatch in Interconnects
• The dimension variations in routing causes interconnect capacitance
and resistances to vary – statics skew between different paths.
• Inter-level-thickness variations.
• Variation in polish rate in planarization process.
• Deviation in the width of the wires and line spacing.
4. Environmental variations
• Most significant sources to contribute jitter and skew.
• Temperature gradient because of variation in power dissipation.
• Activity region is chip varying depending on design.
• Variation in temperature is time varying
Source of Skew and Jitter
5. Power supply variations
• Major source of clock jitter in circuit.
• Delay through buffers is a very strong function of power supply.
• The buffer delay along one path is very different than the buffer delay
along another path.
• Instantaneous IR drops along the power grid due to fluctuations in
switching activity.
• Clock signal is modulated on a cycle-by-cycle basis, resulting in jitter.

6. Capacitive coupling
• The variation in capacitive load also contributes to timing uncertainty.
• Coupling between the clock lines and adjacent signal wires.
• Variation in gate capacitance.
• The adjacent signal can transition in arbitrary directions and at arbitrary
times, This results in clock jitter
Design Techniques to Reduce of Skew
and Jitter
• A balanced clock paths from a central distribution sources - using H-
tree structures or routed tree structures.
• The use of local clock grids can reduce skew.
• If data flows in one direction, route data and clock in opposite
directions.
• Avoid data dependent noise by shielding clock wires from adjacent
signal wires.
• Dummy fills are very common and reduce skew by increasing uniformity.
• High frequency power supply variation can be reduced by addition of
on-chip decoupling capacitors
Clock Distribution

You might also like