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The Synopsys UCIe PHY IP supports data rates up to 40Gb/s with a bandwidth density of 12.9Tbps/mm, designed for high-performance applications in data centers, AI, and networking. It features integrated signal integrity monitors, comprehensive test and repair capabilities, and compatibility with various packaging technologies. This PHY IP provides a complete solution for die-to-die connectivity, ensuring low power, low latency, and high energy efficiency.

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42 views2 pages

dwc_ucie_phy

The Synopsys UCIe PHY IP supports data rates up to 40Gb/s with a bandwidth density of 12.9Tbps/mm, designed for high-performance applications in data centers, AI, and networking. It features integrated signal integrity monitors, comprehensive test and repair capabilities, and compatibility with various packaging technologies. This PHY IP provides a complete solution for die-to-die connectivity, ensuring low power, low latency, and high energy efficiency.

Uploaded by

withinfinitecourage
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SYNOPSYS IP DATASHEET

Universal Chiplet Interconnect Express


(UCIe) PHY

Highlights Overview
• Supports data rates up to 40Gb/s and Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency
bandwidth density of 12.9Tbps/mm die-to-die connectivity in a multi-die package for hyperscale data center, AI,
• Compliant with the latest UCIe and networking applications. The PHY’s flexible architecture supports standard
specification and advanced package technologies and allows up to 12.9Tbps/mm of data to
travel at data rates up to 40Gbps. It supports widely used AMBA protocols such
• Integrated signal integrity monitors and
as AXI and CHI C2C in streaming mode and standards-based protocols such
comprehensive test and repair features
as PCI Express and CXL. The IP offers maximum performance with low BER,
• Supports high-density advanced minimum latency, and implementation flexibility. Synopsys UCIe PHY IP delivers
packaging technologies such as silicon high energy efficiency with an optimized architecture using a single reference
interposer, silicon bridge, and RDL fanout clock feature, low-voltage signaling, and hardware-based initialization. The
• Supports standard packaging mission mode integrated signal integrity monitors and comprehensive test
technologies such as organic substrate and repair capabilities ensure die, die-to-die, and multi-die package health from
and laminate in-design to in-field. Robust die-to-die link operation is ensured with embedded
• Hardware-based initialization & sideband training and calibration algorithms. The PHY is compliant with the latest
vendor message support release of the UCIe specification, ensuring successful interoperability between
heterogeneous dies.
• 100 MHz single reference clock
architecture Synopsys UCIe PHY IP along with Synopsys Controller IP and Verification IP
• Supports on-chip interconnect fabrics deliver a complete solution for die-to-die connectivity in multi-die packages.
including AXI, CHI C2C, CXS, PCIe, CXL,
and streaming

Mainband
Target Applications 40Gbps

• High-performance computing and servers Die1 Die2

• Artificial intelligence / machine learning 64(16) Data


2 Clock
• Networking and infrastructure
1 Valid
• Consumer and mobile 1 Track
R T T R
X X X X
Technology 64(16) Data
2 Clock
• Advanced FinFET technologies across Module Module
1 Valid
multiple foundries 1 Track

SB Data

R T SB Clock T R
X X SB Data X X

SB Clock

800MHz
Sideband

Figure 1: Synopsys UCIe PHY IP architecture (one module)


synopsys.com/ip
Key Features
• Data rates up to 40Gbps per pin while also compliant with the latest UCIe specification
• Self-contained hard macro
• Self-calibrating and training with low BER
• Side band channel for initialization and parameter exchange
• Built-in self-test (BIST), internal loopback, and external PHY-to-PHY link test
• Integrated signal integrity monitors for in-field monitoring
• Flexible module configuration for standard package and advanced package technologies
• Support for various advanced packaging technologies: Silicon and RDL Interposers, Silicon Bridge, RDL Fanout
• Built-in test and repair functionality with redundant pins to maximize yield
• NS (north, south) orientation, EW (east, west) also available

Deliverables
• Verilog models and test bench
• Protocol-specific test bench
• Liberty™ timing views (.lib), LEF abstracts (.lef), CDL netlist (.cdl)
• GDSII
• IP-XACT XML files with register details
• ATPG models
• IBIS-AMI models
• Documentation

About Synopsys IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad Synopsys IP portfolio
includes logic libraries, embedded memories, PVT sensors, embedded test, analog IP, wired and wireless interface IP,
security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP
into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits, and IP subsystems.
Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology
enable designers to reduce integration risk and accelerate time-to-market.

For more information on Synopsys IP, visit synopsys.com/ip .

©2024 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is
available at synopsys.com/copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.
08/26/24.CS915445924-UCIe-PHY-IP-DS.

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