DESIGN AND IMPLEMENTATION OF DIGITAL PHASE LOCKED

LOOP WITH HIGH PERFORMANCE

1
JYOTI, 2V. MOYAL

M.E. Scholar SSGI, Associate professor (SSITM, SSTC), Bhilai (C.G.) India
[email protected]
[email protected]

Abstract— In this paper introduced the Design and implementation of Digital Phase Locked Loop (DPLL) with High
Performance. A DPLL is a close loop frequency system that lock the phase of an output signal to an input reference signal
.The term lock refers to a constant or zero phase difference between two signal. A DPLL is a feedback system that compares
the output frequency / phase with the input frequency/ phase. The PLL is noise sensitive electronic device, and due to noise,
performance of the PLL is poor. To overcome this we used PFD (Phase Frequency Detector) is have 4states. The PLL is
work in different mode, the Lock mode is zero phase difference mode. It also have better phase characteristics. This design
and implementation work is done in Zeni Electronic Design Automation (EDA) environment tool with high oscillation
frequency and low power consumption. Phase locked loop’s were used in most of the application for clock generation and
recovery as well. The DPLL circuit design are include the Phase Frequency Detector (PFD), the Charge Pump (CP) , the
Loop Filter(LF) ,the Voltage Controlled Oscillator(VCO) and divide by counter.

Keywords: Phase Locked Loop, Phase Frequency Detector, Voltage Control Oscillator, Charge Pump.

I. INTRODUCTION A challenging work in the CMOS technology

is to design a low phase noise ring oscillator for a
Over the last decades, the path of CMOS technology charge pump Phase Locked Loop using CMOS
scaling has been accompanied by the trend of technology. A design is to improve the overall
digitization in the hardware realization of circuits and characteristics of DPLL.
system to exploit the finest process node available for A charge pump circuit is used to convert the
the cost reduction [1]. A Digital phase-locked loop digital signal from the phase frequency detector to
(DPLL) is an electronic feedback system that analog signal .The output of which is used to control
generates a signal, the phase of which is locked to the the frequency of the voltage control oscillator.
phase of an input reference signal. A DPLL is a The Loop filter (LF) that smoothes the PD
closed-loop feedback system that sets fixed phase output signal and applies it to the VCO input.
relationship between its output clock phase and the Voltage-controlled oscillator (VCO).The output
phase of a reference clock. [5] frequency of this devices is a monotonic increasing
A DPLL is can be utilized for frequency function of its input voltage .Frequency divider (FD).
synthesis, frequency multiplication, carrier recovery, The output of the frequency divider is a
frequency division and frequency demodulation. As signal with a frequency equal to the VCO output
the name implies, the purpose of a PLL is to generate frequency divided by a division factor N. The first
a signal in which the phase is the same as the phase of component of PLL is the PFD(Phase Frequency
a reference signal. This is done after Detector), which has been designed to improve of the
many iterations of comparing the reference and PLL because it has been minimizing the dead zone.
feedback signals in phase, this is the lock mode.
After this, the PLL continues to compare the two II. PLL ARCHITECTURE
signals but since they are in lock mode, the PLL
output is constant [16]. A PLL is essentially a feedback loop that
A basic form of a DPLL consists of five locks the on-chip clock phase to that of an input clock
main blocks Phase Frequency Detector (PFD), or signal.[14] Phase locked loop is closed loop
Charge Pump (CP), Loop Filter (LF), Voltage control system that compares the output phase with
Controlled Oscillator (VCO), Frequency divider[7]. the input phase. A PLL is a closed-loop feedback
system that sets fixed phase relationship between its
output clock phase and the phase of a reference clock.
A PLL tracks the phase changes that are
within the bandwidth of the PLL. A PLL is a negative
feedback control system circuit.[14].
A basic form of a PLL consists of five main
blocks:
 Phase Frequency Detector(PFD)
 Charge Pump(CP)
Figure1. Basic block diagram of PLL
 Loop Filter(LF)

Proceedings of National Conf. on Recent Innovations in Science Engineering & Technology, 16th Aug 2015, Pune, India, ISBN: 978-93-85465-81-9
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 Design And Implementation Of Digital Phase Locked Loop With High Performance

 Voltage Controlled Oscillator(VCO) This is the arrangement of two upper most PMOS n
 Frequency Divider(FD) two lower most NMOS. It have two input UP and
DN. When PFD goes “UP” signal high, the PMOS
As the name implies, the purpose of a PLL is will turn on. This will connect the current the current
to generate a signal in which the phase is the same as source to the loop filter. It is in similar way when the
the phase of a reference signal. This is done after PFD “DN” signal goes high.
many iterations of comparing the reference and
feedback signals. The overall goal of the PLL is to V. LOOP FILTER
match the reference and feedback signals in phase,
this is the lock mode. After this, the PLL continues to The function of the loop filter is to covert the output
compare the two signals but since they are in lock signal of PFD to control voltage and also to filter out
mode, the PLL. any high frequency noise introduce by the PFD.

III. PHASE FREQUENCY DETECTOR

The phase frequency detector (comparator) produces

an error output signal based on the phase difference
between the phase of the feedback clock and the
phase of the reference clock.

Figure 4. Schematic circuit of loop filter

VI. VOLTAGE CONTROLLED OSCILLATOR

The operation of Voltage Controlled Oscillator is

similar to the ring oscillator. It is the heart of Phase
Locked Loop.
If the error signal from the PFD is an up signal,
then the charge pump pumps charge onto the LF
capacitor which increases the voltage V control. On
Figure 2. Schematic circuit of phase frequency detector the contrary, if the error signal from the PFD is a
down signal, the charge pump removes charge from
Over time, small frequency differences the LF capacitor, which decreases V control[14]. V
accumulate as an increasing phase error. If there is a control is the input to the VCO. Thus, the LF is
phase difference between the two signals, it generates necessary to only allow DC signals into the VCO
up or down synchronized signals to the charge pump/
loop filter.

IV. CHARGE PUMP

A charge Pump circuit is used to convert

the digital signal from the phase frequency detector to
analog signal. The output of which is used to control
the frequency of the voltage.

Figure 5. Schematic circuit of Voltage Controlled Oscillator

necessary to store the charge from the CP. The

purpose of the VCO is to either speed up or slow
Figure 3. Schematic circuit of Charge Pump
down the feedback signal according to the error

Proceedings of National Conf. on Recent Innovations in Science Engineering & Technology, 16th Aug 2015, Pune, India, ISBN: 978-93-85465-81-9
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 Design And Implementation Of Digital Phase Locked Loop With High Performance

generated by the PFD. If the PFD generates an up ―up signal, the VCO speeds up. On the contrary, if a
signal, the VCO speeds up. On the contrary, if a ―down signal is generated, the VCO slows down.
down signal is generated, the VCO slows down.
VIII. EXPECTED OUTPUT
VII. FREQUENCY DIVIDER
In the designing and Implementation of High
The frequency of oscillation is divided down performance PLL all the schematic is designed in
to the feedback clock by a frequency divider. The Zeni EDA tool and successfully run in 180 nm
phase is locked when the feedback clock has a technology. For achieving low power and high speed
constant phase error and the same frequency as the operation is the skill of high performance phase
reference clock. Because the feedback clock is a locked loop. High speed phase frequency detector is
divided version of the oscillator‘s clock frequency, proposed for PLL design. The proposed phase
the frequency of oscillation is N times the reference frequency detector is simple in its structure and has
clock.[7] no glitch output as well as better phase
characteristics.

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Proceedings of National Conf. on Recent Innovations in Science Engineering & Technology, 16th Aug 2015, Pune, India, ISBN: 978-93-85465-81-9
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Proceedings of National Conf. on Recent Innovations in Science Engineering & Technology, 16th Aug 2015, Pune, India, ISBN: 978-93-85465-81-9
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