VISVESVARAYA TECHNOLOGICAL UNIVERSITY

JNANASANGAMA,BELGAVI-590045

PROJECT REPORT (BEC602)

On
“VLSI Implementation of a Vending Machine Using Xilinx”
Submitted in partial fulfilment for the award of degree of
Bachelor of Engineering
In
ELECTRONICS AND COMMUNICATION ENGINEERING
For the Academic Year 2024-2025
Submitted by
SANIYA KOUSAR T - 1HK22EC145
VI SEMESTER
Submitted to
Prof.THIRUPPATHIRAJA M
Assistant Professor
Dept of ECE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

HKBK COLLEGE OF ENGINEERING
No.22/1,Opposite Manayata Tech Park , Bengaluru,Karnataka 560045
 ABSTRACT

This project presents the design and implementation of a digital vending machine
using Xilinx FPGA tools. The system is modeled using finite state machine (FSM)
principles and implemented in Verilog Hardware Description Language (HDL).
The vending machine is designed to accept inputs such as product selection and
coin detection, process transactions based on defined logic, and dispense products
or return change accordingly. The design is synthesized and simulated using Xilinx
ISE/Vivado, allowing real-time testing and verification of system behavior. The
primary objective is to demonstrate a practical application of VLSI design
techniques by integrating combinational and sequential logic to control a vending
machine.

The system architecture supports multiple product options and coin denominations,
with logic implemented to handle valid and invalid input conditions. The FSM is
structured to ensure efficient state transitions and reliable output generation,
maintaining system robustness and ease of scalability. Simulation waveforms
validate the design functionality and timing accuracy. This project reflects the
practical relevance of digital logic design in embedded systems and consumer
electronics, illustrating how FPGA-based solutions offer enhanced performance,
flexibility, and reduced time-to-market for complex control-oriented applications
such as automated vending machines.
 TABLE OF CONTENTS

INTRODUCTION ................................................................................ 1
DESIGN OVERVIEW… ..................................................................... 2
VERILOG CODE................................................................................ 3-6
SIMULATION AND TESTING… ..................................................... 7-9
EXPECTED RESULTS AND CHALLENGES… ............................. 10
APPLICATIONS ................................................................................... 11
CONCLUSION ...................................................................................... 12
 INTRODUCTION

The advancement of Field Programmable Gate Arrays (FPGAs) has significantly

transformed the way digital systems are designed, tested, and implemented.
FPGAs offer a flexible, high-performance platform for developing complex
digital circuits, making them an ideal choice for various embedded systems,
including automation systems. One such system is the digital vending machine,
which serves as an excellent example of integrating Finite State Machine (FSM)
concepts with VLSI design techniques.
This project focuses on the design and implementation of a digital vending
machine using Xilinx FPGA tools. The vending machine system simulates real-
world interactions where a user inserts coins, selects products, and receives either
a product or change depending on the input conditions. The design is based on
FSM architecture, where states represent different stages of the transaction
process, such as accepting coins, checking for sufficient balance, dispensing
products, and returning change.
The system is implemented using Verilog HDL (Hardware Description
Language), which is synthesized and simulated through Xilinx ISE/Vivado.
This allows the project to be tested for functional correctness, speed, and timing
accuracy, providing valuable insights into the efficiency of FPGA-based designs
in handling real-time control systems.
The primary aim of this project is to demonstrate the application of digital logic
design in solving real-world problems through FPGA-based solutions.
Additionally, it explores how VLSI principles can be used to optimize the design
of digital systems with high performance, scalability, and low power
consumption, making it suitable for practical applications in consumer
electronics and automation systems.

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System Design Overview
The digital vending machine system is designed using an Xilinx FPGA and is
based on a finite state machine (FSM). The main components of the system are:
1. Coin Detection: The system accepts a variety of coins, with each coin
corresponding to a specific value. A mechanism detects the coin inserted
into the machine and updates the total amount.
2. Product Selection: The user selects a product by pressing a button
corresponding to a product. If sufficient funds are available, the product is
dispensed.
3. Change Dispensing: If the total inserted coins exceed the price of the
selected product, the system calculates the difference and returns the
appropriate amount of change.
4. FSM Logic: The system is governed by an FSM that dictates the transitions
based on inputs like coin values and product selection. The states of the
FSM ensure correct operation in dispensing products and handling change.

Finite State Machine (FSM) Design

The finite state machine (FSM) controls the flow of the vending machine. The
key states of the FSM include:
1. Idle State: The system waits for coin insertion. When a coin is detected,
the FSM transitions to the coin insertion state.
2. Coin Insertion State: The system accepts coins and adds their value to the
total balance. It then transitions to the product selection state.
3. Product Selection State: The user selects a product. If the balance is
sufficient, the FSM transitions to the dispense product state; otherwise, it
returns to the coin insertion state.
4. Dispense Product State: The machine dispenses the selected product and
returns to the idle state.
5. Change Dispensing State: If the inserted coins exceed the product price,
the FSM transitions to this state to calculate and return change

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Hardware Description Language (Verilog) Implementation
Verilog Implementation
The FSM for the vending machine is implemented in Verilog HDL. Below is a
basic outline of the Verilog modules:
Module: FSM (Finite State Machine)
module VendingMachineFSM(
input clk,
input reset,
input [3:0] coin, // 4-bit input for coin value
input [3:0] product, // 4-bit input for product selection
output reg dispense, // Output to control product dispensing
output reg change // Output to control change dispensing
);
// Define the states
reg [2:0] state;
reg [2:0] next_state;

// State encoding
localparam IDLE = 3'b000, COIN_INSERT = 3'b001, PRODUCT_SELECT =
3'b010, DISPENSE_PRODUCT = 3'b011, DISPENSE_CHANGE = 3'b100;

// State transitions
always @(posedge clk or posedge reset) begin
if (reset)
state <= IDLE;
else
state <= next_state;

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end

// Next state logic

always @(*) begin
case(state)
IDLE: begin
if (coin != 4'b0000) next_state = COIN_INSERT;
else next_state = IDLE;
end
COIN_INSERT: begin
if (product != 4'b0000) next_state = PRODUCT_SELECT;
else next_state = COIN_INSERT;
end
PRODUCT_SELECT: begin
if (coin >= 4'b0100) next_state = DISPENSE_PRODUCT;
else next_state = COIN_INSERT;
end
DISPENSE_PRODUCT: begin
next_state = DISPENSE_CHANGE;
end
DISPENSE_CHANGE: begin
next_state = IDLE;
end
default: next_state = IDLE;
endcase
end

4
// Output logic
always @(state) begin
case(state)
IDLE: begin
dispense = 0;
change = 0;
end
COIN_INSERT: begin
dispense = 0;
change = 0;
end
PRODUCT_SELECT: begin
dispense = 0;
change = 0;
end
DISPENSE_PRODUCT: begin
dispense = 1;
change = 0;
end
DISPENSE_CHANGE: begin
dispense = 0;
change = 1;
end
default: begin
dispense = 0;

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 change = 0;
end
endcase
end

endmodule
This Verilog code describes the FSM, where the system transitions between
various states based on inputs like coin value and product selection
Module Declaration:
• The VendingMachineFSM module accepts inputs like clock (clk), reset,
coin (inserted coin value), and product (selected product).
• It outputs dispense (to trigger product dispensing) and change (to trigger
change dispensing).
State Encoding:
• The system has 5 states:
o IDLE: Waits for coin insertion.
o COIN_INSERT: Accepts coins and updates the balance.
o PRODUCT_SELECT: User selects a product.
o DISPENSE_PRODUCT: Dispenses the product.
o DISPENSE_CHANGE: Returns any excess change.
State Transition Logic:
• The FSM moves between states based on inputs (coin value, product
selection). For example:
o From IDLE to COIN_INSERT when a coin is inserted.
o From COIN_INSERT to PRODUCT_SELECT when a product is
selected.

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 o If enough money is inserted, the FSM moves from
PRODUCT_SELECT to DISPENSE_PRODUCT and then to
DISPENSE_CHANGE.
State Update:
• The FSM updates its current state based on clock cycles, with reset setting
it back to IDLE.
Output Logic:
• Depending on the state, the outputs are set:
o dispense is set to 1 in the DISPENSE_PRODUCT state to dispense
the product.
o change is set to 1 in the DISPENSE_CHANGE state to return
change.

Simulation and Testing

Simulation Setup

The simulation was performed using Xilinx ISE/Vivado. A testbench was

created to simulate inputs like coin insertion, product selection, and reset
conditions

TestBench Code:

module Testbench();

reg clk;

reg reset;

reg [3:0] coin;

reg [3:0] product;

wire dispense;

wire change;

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// Instantiate the VendingMachineFSM module

VendingMachineFSM uut (

.clk(clk),

.reset(reset),

.coin(coin),

.product(product),

.dispense(dispense),

.change(change)

);

// Clock generation

always begin

#5 clk = ~clk; // 100 MHz clock

end

// Initial block to apply inputs

initial begin

// Initial conditions

clk = 0;

reset = 1;

coin = 4'b0000;

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 product = 4'b0000;

#10 reset = 0; // Release reset

// Test case: Coin insertion and product selection

coin = 4'b0100; // Insert 4 unit coins

product = 4'b0001; // Select product 1

#50 coin = 4'b0000; // Stop inserting coins

product = 4'b0000; // De-select product

#100 $finish; // End simulation

end

endmodule

Simulation results (waveforms) indicate that the FSM transitions correctly

through all states. When a valid coin is inserted, the system transitions from the
coin insertion state to the product selection state, dispenses the product when
sufficient coins are available, and correctly calculates and dispenses any change.

How the Testbench Works:

• The testbench generates the clock signal (clk), applies the reset, and
supplies various input values (coin and product) to the
VendingMachineFSM module.
• It simulates a scenario where coins are inserted and a product is selected,
and after a certain amount of time, it stops the coin insertion and de-selects
the product.

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 • The outputs of the FSM (dispense, change) are observed to verify if the
system behaves as expected.
• The simulation runs for a specified amount of time and is then stopped
using $finish.

Expected Behavior in Simulation:

1. Initially, the FSM is in the IDLE state, waiting for coins to be inserted.
2. Upon coin insertion (coin = 4'b0100), the FSM moves to COIN_INSERT
and updates the total balance.
3. After the product is selected (product = 4'b0001), the FSM checks if the
balance is sufficient to dispense the product.
4. If the balance is enough, it transitions to the DISPENSE_PRODUCT
state, and then moves to the DISPENSE_CHANGE state to return any
excess money.
5. The simulation ends after the specified time.

Analysis of Results

• Verify Correctness: Ensure that the FSM behaves as expected—correctly

dispensing the product and returning change when applicable.
• State Transitions: Check that the FSM transitions through the correct
states based on the inputs, following the expected sequence (e.g., from
IDLE to COIN_INSERT, then to PRODUCT_SELECT, and so on).
• Output Analysis: Validate the dispense and change signals to confirm they
are triggered at the right moments in the FSM sequence.

Challenges and Issues Encountered

• Simulation Errors: If there are any discrepancies in the FSM’s behavior,

discuss the issues encountered, such as incorrect state transitions, improper
output values, or synthesis problems.
• Debugging: Describe the steps taken to debug the design, such as checking
the logic for state transitions, verifying the coin value logic, or adjusting
delays in the testbench.

10
Applications of Vending Machine Design Using FSM in Xilinx

1. Embedded Systems and Digital Circuit Design

The Vending Machine FSM is primarily used for controlling systems that
require step-by-step operations, such as coin insertion, product selection, and
change dispensing. This FSM design can be implemented on Xilinx FPGAs to
control digital systems in real-time. Tools like Vivado and ISE allow designers
to simulate, synthesize, and implement the FSM logic on FPGA boards such as
Spartan-6 or Artix-7.

2. Smart Vending Machines and IoT Integration

In the context of IoT, FSM-based designs in smart vending machines can

manage payment systems, inventory tracking, and remote updates. Xilinx’s
Zynq-7000 or ZCU102 SoCs, which combine processing systems and
programmable logic, are ideal for such applications, where embedded software
on the ARM core integrates with the FPGA fabric for controlling machine
operations.

3. Digital Payment Systems

FSM designs are used in coin-operated machines like toll booths or ticket
dispensers. These systems require payment verification before providing
services or products. Xilinx FPGAs are suitable for processing coin values
quickly and efficiently, ensuring that the system verifies payments in real time.

How Xilinx is Used

Xilinx FPGAs provide the flexibility to implement FSMs for various applications,
from simple vending machine designs to more complex IoT or payment systems.
Xilinx's Vivado or ISE design tools are used for simulation, synthesis, and
hardware implementation, making FPGA-based solutions ideal for controlling
embedded systems and real-time applications.

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 CONCLUSION
The development of a vending machine using a Finite State Machine (FSM) and
its implementation on Xilinx FPGA platforms demonstrates the practical
application of digital system design principles. FSMs provide a systematic way
to manage sequential operations such as coin insertion, product selection,
validation, and dispensing, making them ideal for automation tasks. By
leveraging Xilinx tools like Vivado or ISE, the Verilog-based design can be
simulated, synthesized, and deployed efficiently onto FPGA hardware for real-
time operation.

This project not only strengthens understanding of FSM-based design but also
showcases the versatility and power of FPGAs in handling complex logic with
high speed and reliability. The vending machine model serves as a scalable
solution that can be extended to support multiple products, digital payments, and
smart features for IoT integration. Overall, this implementation highlights the
relevance of HDL and FPGA-based prototyping in modern embedded systems
and real-world automation.

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