SE computer ( 2019) Microprocessor

Notes unit 1
History of Intel processors

• Intel, (Intel Corporation ), is a manufacturer of semiconductor computer circuits.

• Its headquarter is in Santa Clara, California. The company‘s name comes from
―integrated electronics.‖
• Intel was founded in 1968 by American engineers :Gordon Moore &Robert Noyce

Summary ( you can remember easily by this table , draw it in exam also )

year processor cores Size Speed / clock No. of transistors Technology Instructions per
bits ( micron) second
1971 4004 1 4 740KHz 2300 10 µ 600
1972 4040 1 4
1972 8008 1 8 800KHz 3500 10 µ 5lakh
1974 8080 1 8 2MHz 4500 6µ
1976 8085 1 8 3MHz 6500 7.7 lakh
1978 8086 1 16 5M , 10M 29000 3µ 2.5 million
1982 80186 1 16 6-25M 55000 2µ
1982 80286 1 16 6M 134000 1.5 µ
1985 80386 1 32 16M 275000 1.5 µ
1989 80486 1 32 25M 1.2 million 1µ
1993 Pentium 1 32 66M 3.1milion 0.8 µ
2001 Xeon 1 32 1.7GHz 42 million 0.18 µ
2008 Core2duo 1,2,4 64 2.4G 291million 45nm
2008 Core i7 4 to10 64 2.66 – 3.2G 731M 45nm
2009 Core i5 2,4 64 2.66G 774M 45nm
2010 Core i3 2-4 64 2.93-3.07G 382 M 32nm
2017 Core i9 10-18 64 2.6-4G undisclosed 14-10nm

Intel has three brands

1) Intel® processor : is an economical product line created for price-conscious consumers.
2) Intel® Core™ processors have faster performance and additional features not available in
Intel® Processor models.
3) Intel® Xeon® processors offer a higher level of performance for servers and workstations.

Intel® Core™brand has 4 brand modifiers ( i.e. processors )

i3
i5
i7
i9

Each of the above core processors ( brand modifiers ) have various generations (1 to 13)
The main difference between different generations is the architecture. They also got better RAM
support, cache support, and overclocking capabilities

More details : https://techgamesnews.com/cpus/intel-processor-generations-timeline-and-evolution/

generations year Name technology
1 2008 Nehalem 45nm
2 2011 Sandy 32
3 2012 Ivy 22
4 2013 Haswell 22
5 2014 Broadwell 14
6 2015 Skylake 14
7 2016 Kaby lake 14
8 2017 Kaby lake R 14
9 2017 Coffee lake 14
10 2019 Ice lake 14
11 2021 Tiger lake 14
12 2021 Alder lake 14
13 2022 Raptor lake 14

Feature of 80386 DX
 Flexible 32-Bit Microprocessor
— allows 8, 16, 32-Bit Data Type
 Very Large Address Space
— 4 Gigabyte Physical
— 64 Terabyte Virtual
— 4 Gigabyte Maximum Segment Size
 Integrated ( on chip)Memory Management Unit
— Virtual Memory Support
— Optional On-Chip Paging ( can be enabled or disabled)
— 4 Levels of Protection

 Object Code Compatible with All 8086 Family Microprocessors

 Virtual 8086 Mode Allows Running of 8086 Software in a Protected and Paged System
 Hardware Debugging Support
 Self test facility
 Optimized for System Performance
— Pipelined Instruction Execution
— On-Chip Address Translation Caches
— 20, 25 and 33 MHz Clock

 Intel387 DX Math Coprocessor can be connected for complex numerical operations

 Complete System Development Support
— Software: C, PL/M, Assembler System Generation Tools
— Debuggers: PSCOPE, ICETM-386
 High Speed CHMOS IV Technology
 Available in
132 Pin Grid Array Package
132 Pin Plastic Quad Flat Package

designed for single-user applications and operating systems such as MS-DOS and Windows.
Functional block diagram /architecture of 80386

OR
80386 contains following units
1. Bus unit
2. Central processing unit ( consists of Instruction unit& execution unit)
3. Memory management unit (Consists of asegmentation unit and a paging unit )
1.Bus unit
provides the interface between the 80386 and system around it.
It gets requests for code fetches (from the Code Prefetch Unit) and data transfers (from the Execution
Unit), accordingly it generates signals to read/write data & read instructions(code)
2. Central processing unit
consists of the i) execution unit and ii) instruction unit.
i)The execution unit contains the eight 32-bit general purpose registers which are used for both address
calculation, data operations. A 64-bit barrel shifter used for fast shift, rotate, multiply, and divide
operations. The multiply and divide logic makes multiply & divide in less than one microsecond.
Execution Unit executes the instructions from the Instruction Queue.
It has three subunits :
I. The Control Unit contains microcode for each instruction and effective address calculation.
II. The Data Unit contains the ALU, a file of eight 32-bit general-purpose registers, and a 64-bit
barrel shifter (which performs multiple bit shifts in one clock). The Data Unit performs data
operations requested by the Control Unit.
III. The Protection Test Unit checks for segmentation violations under the control of the
microcode.
ii) The instruction unit :
It has two parts i) Code Pre-fetch Unit& ii) pre-decode unit
i) Code Pre-fetch Unit: When the Bus Unit is not accessing bus, the Code Pre-fetch Unit uses
the Bus Unit to fetch next instructions,
ii) pre-decode unit; decodes up to 3 the instruction opcodes and stores them in a queue called pre-
decoded instruction queue , which can be directly executed by the execution unit.
These two units makes processing faster.
3.The memory management unit (MMU)
Consists of i) a segmentation unit and ii) a paging unit.
i) Segmentation Unit
The Segmentation Unit translates logical addresses into linear addresses
The translated linear address is forwarded to the Paging Unit( if it is enabled) ,else directly
sent to bus unit.
The segmentation unit provides four-levels of protection for isolating and protecting
applications and the operating system from each other.
ii) Paging Unit
When the 80386 paging mechanism is enabled, then Each segment is divided into one or
more 4Kbyte pages. The Paging Unit translates linear addresses generated by the
Segmentation Unit or the Code Prefetch Unit into physical addresses. (If paging is not
enabled, the physical address is the same as the linear address, and no translation is
necessary.) The Page Descriptor Cache stores recently used Page Directory and Page Table
entries in its Translation Lookaside Buffer (TLB) to speed this translation.
The Paging Unit forwards physical addresses to the Bus Interface Unit to perform memory
and I/O accesses
Operatingmodes of80386

80386 can operate in one of the following modes , one at a time

Real mode
Protected mode
Virtual8086 mode
1.real mode
It is mode in which 386 works after reset.
purpose of Real Mode is to set up theprocessor for Protected Mode Operation.
works as 8088 / 8086
access to all registers except TR & LDTR.
Instructions of protected mode can‘t be used i.e. VERR, VERW, LAR, LSL LTR, STR, LLDT, SLDT
,ARPL
Memory handling 1 MB
No logical / virtual memory
Segment size is always 64 KB
This mode handles only one task at a time.
No paging of memory
No protection mechanism
only The privilege level = 0 (most privileged)is used
.2.protectedmode
386 is switched from real mode to protected mode when PE bit in CR0 is set to 1, when in real mode
purpose = to provide Full features of protection & paging
Can access to all registers
All Instructions of protected mode can be used
Memory handling 4GB
logical / virtual memory = 64TB
Segment size can vary from 1 byte up to 4GB
Can do multi tasking
paging of memory available
protection mechanism available
All privilege levels ( 0 to 3) are used .

3.Virtual 8086 mode

i. Virtual8086Modeallowstheexecutionof8086programs,whilestillallowingthesystemdesignerto take
full advantage of the Intel386DX protection mechanism.
ii. allows the simultaneous execution of 8086 operating systems and 8086 applications, and also
an80386 operating system and 80386 applications. Thus, in a multi-user 80386 computer, one person
could be running an MS-DOS spreadsheet, another person using MS-DOS, and a third person could be
running multiple Unix utilities and applications. Each person believes that he had the computer only
for himself
It is mode which can be activated when 386 is already in protected mode , by setting VM bit in flags
register
Purpose = to run multiple 8086 programs but with protection along with other 386 programs
works as 8088 / 8086 but with some features of 386
Registers that can‘t be used : TR & LDTR, GDTR, control registers, debug registers
Instructions of protected mode can‘t be used i.e. VERR, VERW, LAR, LSL LTR, STR, LLDT, SLDT
,ARPL
Physical Memory size = 1 MB for 8086 programs & 4GB for 386 programs
No logical / virtual memory for 8086 programs &but 64TB for 386 programs
Segment size = 64 KB for 8086 programs & 4GB for 386 programs
Can do multi tasking
paging of memory
 protection mechanism
All Virtual 8086 Mode programs execute at privilege
level 3, (the level of least privilege.)

compare all three modes of 80386

Real mode Protected mode Virtual 8086 mode

386 is switched from real mode It is mode which can be
It is mode in which 386 works to protected mode when PE bit activated when 386 is already in
after reset. in CR0 is set to 1, when in real protected mode , by setting VM
mode bit in flags register
purpose = is to set up Purpose = to run multiple 8086
purpose = to provide Full
theprocessor for Protected Mode programs but with protection
features of protection & paging
Operation. along with other 386 programs
works as 8086 but with some
works as 8086 Works with full features
features of 386
access to registers except TR &
access to all registers except TR
access to all registers LDTR, GDTR, control registers,
& LDTR.
debug registers
Instructions of protected mode Instructions of protected mode
can‘t be used i.e. VERR, All Instructions of protected can‘t be used i.e. VERR,
VERW, LAR, LSL LTR, STR, mode can be used VERW, LAR, LSL LTR, STR,
LLDT, SLDT ,ARPL LLDT, SLDT ,ARPL
Memory handling 1 MB for
Memory handling 1 MB Memory handling 4Gb 8086 programs & 4GB for 386
programs
No logical / virtual memory for
No logical / virtual memory logical / virtual memory = 64TB 8086 programs & 64TB for 386
programs
Segment size = 64 KB for 8086
Segment size can vary from 1
Segment size is always 64 KB programs & 4GB for 386
byte up to 4GB
programs
This mode handles only one
Can do multi tasking Can do multi tasking
task at a time.
No paging of memory paging of memory paging of memory
No protection mechanism protection mechanism protection mechanism
All Virtual 8086 Mode
only The privilege level = 0 All privilege levels ( 0 to 3) are programs execute at privilege
(most privileged)is used used . level 3, (the level of least
privilege.)

programmer‘ smodel of 80386

• It is the view of CPU from Programmer‘s point of view.
• It describes what parts programmer can access& what operations ( instructions)Programmer can
dousing CPU,
• It does not describe how CPU works .i.e. electronic aspect of CPU.
• programmer‘s model include Registers, addressing modes, data types & instruction set.
• The Intel 386DX has32 register resources in the following categories:
• General Purpose Registers ( EAX, EBX, ECX, EDX): are used for Holding data before & after an
instruction execution.
Index registers ESI & EDI are used for string ( array) operations. Pointer registers ESP& EBP are used
in stack segment during function call

• Segment registers : memory is divided in segments which are used to store different parts of
program i.e. code (CS), stack (SS)&data( DS, ES, FS,GS)

• Instruction pointer used to hold the address of next instruction.

• Flags register: control certain operations and indicate some special status of the result after
some arithmetic or logical operations

• Control Registers
The Intel386 DX has three control registers of 32 bits, CR0, CR2 and CR3, These registers, hold
machine status that for all tasks in the system.
• System Address Registers used to access the tables or segments when 80386 is operating in
protection model.

• Debug Registers:
The six debug registers provide on-chip support for debugging.

• Test Registers: used to control the testing of the Translation Lookaside Buffer

• Instruction format consists of opcode ( operation to be performed by processor),

Source operand &destination operand

AddressingModes
It is the way the operands are specified in an instruction
Control unit decides from where to take operand and where to store the result operand based on
addressing mode used in instruction.
TheIntel386DXprovidesatotalof 11addressing modes for instructions to specify operands
1.Register Operand Mode:
• The operand is located in one of the8-, 16-or 32-bitgeneral registers.
• Eg ADD EAX,ECX
• Contents of CX are added to AX ( and result is stored in AX)

2. Immediate Operand Mode

In which the operand value is present in the instruction
So when instruction is fetched ,it is fetched along with the operand .No separate memory access
required to fetch data.
Eg ADD EAX, 500E
The value 500E is added to register AX & result is stored in AX

3. Direct Mode:
The operand‘s offset is contained as part of the instruction as an 8,16 or 32 bit displacement.
EXAMPLE: ADD EAX,[500E]
Offset=500E

4. Register Indirect Mode:

• ABASE register contains the address of the operand.
• EXAMPLE:MOVEAX,[EDX]& Suppose EDX contains 2CA7
So offset=2CA7

5. Based Mode:
A BASE register‘s contents is added with a DISPLACEMENT to form the operands offset.

EXAMPLE:MOVECX,[EAX+24]
Suppose EAX contains 1000Sooffset =1024

6. Index Mode:
• An INDEX register‘s contents is added with a DISPLACEMENT to form the operands offset.
• EXAMPLE:ADD EAX,[ESI+FD]
• Suppose ESI contains 2000
• So offset=20FD
7. Scaled Index Mode:
An INDEX register‘s contents is multiplied by a scaling factor( which can either 1,2,4or8) which is
added to a DISPLACEMENT to form the operands offset.
EXAMPLE :IMULEBX,[EDI*2]+7
Suppose EDI contains 2000; So offset =4007

8. Based Index Mode:

The contents of a BASE register is added to the contents of an INDEX register to form the effective
address of an operand.
EXAMPLE:MOVEAX, [ECX][EBX]
Suppose ECX =2000&EBX=3000; So offset=5000

9. Based Scaled Index Mode:

The contents of an INDEX register is multiplied by a SCALING factor and the result is added to the
contents of a BASE register to obtain the operands offset.
EXAMPLE: MOV ECX, [EDX*2] [EBP]
Suppose EDX=1000EBP=2000Sooffset=4000
10. Based Index Mode with Displacement:
The contents of an INDEX Register and a BASE register‘s contents and a DISPLACEMENT are all
summed together to form the operand offset.
EXAMPLE: ADD EDX, [ESI] [EBP+00FFFFF0H]
Offset=ESI+EBP+00FFFFF0
11. Based Scaled Index Mode with Displacement:
The contents of an INDEX register are multiplied by a SCALING factor, the result is added to the
contents of a BASE register and a DISPLACEMENT to form the operand‘s offset.
EXAMPLE: MOVEAX, [EDI*4][EBP+80]
So offset=(EDI*4) + EBP+80

So Possible combinations are :

Data types supported by80386
The80386 supports all of the data types commonly used in high level languages:
1. Bit: A single bit quantity.
2. BitField: A group of up to32 contiguous bits, i.e. maximum of four bytes.
3. BitString: A group of up to4gigabits contiguous bits .
4. Signed Byte ( 8 bit ):range of values that can be stored= 0 to 255
5. Unsigned Byte( 8 bit ): range = -128 to +127
6. Signed Word ( 16 bit ) (Integer) range = 0 to + 65535
7. Unsigned Word ( 16 bit ) ( Integer) range = -32768 to +32767
8. Signed Double Word ( 32 bit) ( Long Integer ) range = 0 to + 4.294* 10 9
9. Unsigned Double Word ( 32 bit) ( Long Integer ) range = - 2,147 * 10 9 to +2,147 * 10 9
10. Signed Quad Word (64 bit )
11. Unsigned Quad Word (64 bit )
12. Unpacked BCD: A byte storing single decimal digit ( 0–9.)
Eg 19 is stored as 0000 0001 & 0000 0101
13. Packed BCD: A byte storing two decimal digits ( 00–99.)storing one digit in each nibble.
Eg 19 is stored as 0001 0101
14. Offset: A 32-bit offset, quantity which indirectly references another memory location in the
same segment

15. Pointer: consists of a16-bit segment selector and either a 16-or32-bit offset which
references another memory location in the different segment

16. Char: A byte representation of an ASCII Alphanumeric or control character.

Eg character ‗0‘ is represented as 31H in ASCII,
There is difference between number 0 (=00000000) & its ASCII code ( =31H)
17. String: A contiguous sequence of bytes, words or dwords. A string size can be between 1 byte
to 4 Gbytes.
String is Sequences of separate but related data items stored in consecutive addresses ( i.e. array).
The 80386supports bytestrings, wordstrings, and dword strings.
Instructions
The instruction set is divided into nine categories of operations:
1. Data Transfer ( general purpose ,conversion, input/output , address object , flag manipulation)
2. Arithmetic ( + - * / )
3. logical ( AND OR NOT XOR , Shift & rotate)
4. String Manipulation
5. Bit Manipulation
6. Control Transfer ( unconditional , conditional , iteration , interrupts)
7. High Level Language Support
8. Operating System Support ( protection mode )
9. Processor Control

Data Movement ( transfer)Instructions

These instructions are used for moving bytes, words, or double words of data between memory and the
registers of the basic architecture( real mode).
Eg MOV EAX,EBX
The contents of register EBX are copied into EAX.
Flag control instructions
Contents of some bits of flag register can be changed ( set or reset)
Eg STC
This instruction sets carry flag to 1
Eg CLC
This instruction clears carry flag to 0

Arithmetic instructions

Eg ADD EAX, EBX

The contents of EBX are added to EAX and the result is stored in EAX . Flags affected: Sign , zero,
carry ,overflow flags

Logical Instructions

Following Logical operations are possible AND, OR, NOT, XOR, rotate, shift , test
Eg
AND EAX, EBX
Each bit of EBX is ANDed with corresponding bit of EAX and the result of ANDing is stored in EAX.

Control transfer

Processor executes instructions in sequence, but control transfer instructions executes instruction
which is not the next in the sequence based on some decision
Eg JMP2100
1000 Instruction n
1001 Instructionn+1
1002 Instructionn+2
1003 JMP 1000
1004
1005
….

2003 Instruction z
 2004 Instructionz+1

When IP(instruction pointer)is1003, theJMP1000instruction will be executed. The offset 1000 in the
instruction is added in current IP to find the address of instruction which will be executed next . The
next instruction that will executed is from address 2003

On similar lines you can write for other types of instructions namely

3. logical ( AND OR NOT XOR , Shift & rotate)

4. String Manipulation
5. Bit Manipulation
6. Control Transfer ( unconditional , conditional , iteration , interrupts)
7. High Level Language Support
8. Operating System Support ( protection mode )
9. Processor Control