Coa assignment Btech 4th sem
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suprgamer1112Coa assignment Btech 4th sem
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suprgamer1112ASSIGNMENT 01
Ques1: Mark each inclividlal path in the flowchart ofFig. IG-2 by a number and then
indicate the overall path that the algorithm takes when the following signed·
magnitude numbers are computed. In each case give the value of AVF. The
leftmost bit in the followi!lg numbers presents the sign bit.
a. 0 101101 + 0 011111
b. 1 011111 + 1 101101
c. 0 101101 - 0 011111
d. 0 101101 - 0 101101
e. 1 011111 - 0 101101
Ques2: Perform the arithmetic operations below with binary numbers and with
negative number$ In slgned-2"s complement "'Preset�!Jotion. Use seven bits
to accommodate each number together with its sign. In each cue, determine
if there is an overflow by checking the carries Into and out ol the sign bit
position.
a. (+35) + (+40)
b. (-35) + (-40)
c. (-35) - (+40)
Ques3: Consider the binary numbers when they are in signed-2’s complement
representation. Each number has n bits: one for the sign and lc = " - 1 lor
the magnitude. A negative number -X is represented as 2' + (2' - X).
where the first 2' designates the sign bit and (2' - X) is the 2's complement
of X. A positive number is represented as O + X, where the O design at the
sign bit, and X, the k bit magnitude. Using these generalized symbols, prove
that the sum ( ± X) + ( ± Y) can be formed by adding the numbers including
their sign bits and discarding the carry-out of the sign-bit position. In other
words, prove the algorithm for adding two binary numbers in signed-2's
complement representation.
Ques4: Formulate a hardware procedure for detecting an overflow by comparing the
sign of the sum with the signs of the augend and addend. The numbers are
in signed-2' s complement representation.
Ques5: a. Perform the operation ( -9) + ( - 6) = - 15 with binary numbers in
signed-1' s complement representation using only five bits to represent
each number (including the sign). Show that the overflow detection
procedure of checking the inequality of the last two carries fails in this
case.
b. Suggest a modified procedure for detecting an overflow when signed-l's
complement numbers are used.
Ques6: Derive an algorithm in flowchart form for adding and subtracting two fixedpoint
binary numbers when negative numbers are in signed-l's complement
representation.
Ques7: Prove that the multiplication of two n-digit numbers in base r gives a product
no more than 2n digits in length. Show that this statement implies that no
overflow can occur in the multiplication operation.
Ques8: Show the contents of registers E, A, Q, and SC (as in Table 10-2) during the
process of multiplication of two binary numbers, 11111 (multiplicand) and
10101 (multiplier). The signs are not included.
Ques9: Show the contents of registers E, A, Q, and SC (as in Fig. 10-12) during the
process of division of (a) 10100011 by 1011; (b) 00001111 by 0011 . (Use a
dividend of eight bits.)
Ques10: Show that adding B after the operation A + B + 1 restores the original value of A. What
should be done with the end carry?
Ques11: Why should the sign of the remainder after a division be the same as the sign
of the dividend?
Ques12: Design an array multiplier that multiplies two 4-bit numbers. Use AND gates
and binary adders.
Ques13: Show the step-by-step multiplication process using Booth algorithm (as in
Table 10-3) when the following binary numbers are multiplied. Assume 5-bit
registers that hold signed numbers. The multiplicand in both cases is + 15.
a. ( + 15) x ( + 13)
b. ( + 15) X ( - 13)
Ques14: Derive an algorithm in flowchart form for the nonrestoring method of fixedpoint
binary division
Ques15: Derive an algorithm for evaluating the square root of a binary fixed-point
number.
