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Design and Implementation of RISC-V ISA (RV32IM) on FPGA

Article in International Journal of VLSI & Signal Processing · June 2023

DOI: 10.14445/23942584/IJVSP-V10I2P103

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SSRG International Journal of VLSI and Signal Processing Volume 10 Issue 2, 17-21, May-Aug 2023
ISSN: 2394–2584 / https://doi.org/10.14445/23942584/IJVSP-V10I2P103 © 2023 Seventh Sense Research Group®

Original Article

Design and Implementation of RISC-V ISA (RV32IM)

on FPGA
Anmol Singh1, Arpit Kumar2, Abhishek Singh3, R. Anirudh Reddy4, K. N. Pushpalatha5
1,2,3,4,5
Department of Electronics & Communication Engineering, Dayananda Sagar College of Engineering, Karnataka, India.

Received: 29 April 2023 Revised: 05 June 2023 Accepted: 20 June 2023 Published: 06 July 2023

Abstract - RISC-V, an open-source Instruction Set Architecture, originated from the collaborative efforts of researchers at the
University of California, Berkeley, in 2010. It is a basic Load and Store type architecture based on traditional principles of
RISC whilst providing flexibility in terms of extensions to the base Integer Set such as multiply, floating point and atomic
instructions. This paper details the Design and Implementation of 5 stages pipelined RV32IM (base integer set with multiply
extension). The design also incorporates a 2-bit branch predictor for increased throughput. Analysis and Verification have
been performed for proper decoding, pipelined operation, branch prediction, stalling, memory access, and overall
functionality. Verilog HDL on Intel QuestaSim has been used to design the core and simulation. DE 10 Lite board with Max
10 family of FPGA has been used for hardware synthesis and analysis of the design.

Keywords - RISC-V, Instruction Set Architecture, RV32IM, 5-stage pipeline, DE10 Lite FPGA.

1. Introduction instructions. The purpose of branch prediction is to anticipate

A processor forms one of the major and important parts the outcome of a branch instruction before it is resolved and
of any modern computer system. An Instruction Set to speculatively fetch and execute the predicted instructions.
Architecture (ISA) distinguishes one type of architecture By doing so, the processor can avoid pipeline stalls and
from another. RISC V offers a viable alternative to maintain a high instruction throughput.
proprietary ISAs such as ARM and x86. One of the key
features of RISC-V is its modularity, which allows users to The DE10 Lite board with Max 10 FPGA combines the
customize the ISA to fit their specific needs [1]. This DE10 Lite hardware platform with the Intel Max 10 FPGA
flexibility is achieved using a small base ISA, which family. The Max 10 FPGA devices are low-power, non-
provides minimal instructions, and a series of standard volatile programmable logic devices that offer a range of
extension modules that can be added to the base ISA as resources and capabilities suitable for various applications.
needed. Another advantage of RISC-V is its open-source
nature, which allows for collaborative development and The further sections detail the implementation process,
reduces the dependence on a single vendor or manufacturer. results and review carried out.
This has led to a growing ecosystem of RISC-V tools and
platforms, including development boards, compilers, and 2. Reference Study
operating systems. A. Singh et al. [3] introduce a hardware design framework
aimed at implementing the RV32I base integer instruction set
A five-stage pipeline is a fundamental concept in in RISC-V for 32-bit address space. The implemented
processor design, which aims to improve the efficiency and architecture discussed in this paper is a single-core, in-order,
performance of instruction execution. It involves breaking non-bus-based, single-cycle design that fully supports the
down the instruction execution process into five distinct RV32I base integer instruction set. This architecture finds
stages, each handling a specific operation. The five stages application in various domains, including acoustic signal
typically include instruction fetch, instruction decode, processing, real-time embedded systems, sensor technology
execution, memory access, and writeback [2]. and myriad other domains. A suite of tools and test
frameworks around RISC-V was created targeted at 32-bit
Branch prediction is a crucial technique employed in architectures. RV32I was specifically designed to serve as a
modern processors to mitigate the performance impact of comprehensive compiler target and provide support for
conditional branch instructions. Branches occur when the modern operating systems. Additionally, its design aims to
processor encounters instructions like conditional branches, minimize the hardware resources needed for a basic
loops, or function calls that can alter the sequential flow of implementation.

This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

 Anmol Singh et al./ IJVSP, 10(2), 17-21, 2023

The fetch, decode and control logic block is responsible is then processed and broken down into its constituent parts
for fetching the instruction from the instruction memory, to determine the operation to be performed, the operands
decoding the instruction, and generating the control signals. involved, and any additional information needed for
It is also responsible for resolving jump and branch target execution.
addresses. The RV32I architecture includes various
components such as the program counter, target address 3.3. Execute Stage
selection logic, instruction memory controller, instruction The Execute stage is responsible for carrying out the
decoder, and a control unit. Furthermore, it incorporates a actual computations in a processor. Usually, this stage
dedicated adder responsible for incrementing the program incorporates an Arithmetic Logic Unit (ALU). In addition to
counter in each cycle. The control unit is purely the ALU, it may also include a multiple-cycle multiplier and
combinatorial, with all the control signals generated in the divider for more complex mathematical operations. The ALU
same cycle. is responsible for performing Boolean operations (and, or,
not, nand, nor, xor, xnor) and also for performing integer
A comparison of synthesis and implementation has been addition and subtraction. The bit shifter is responsible for
conducted on two Virtex family boards, considering shifts and rotations.
utilization reports and power reports as the evaluation criteria
[3]. 3.4. Memory Stage
If data memory needs to be accessed, it is done in this
3. Materials and Methods stage. It is responsible for performing memory-related
Once we have designed and optimized each sub- operations, such as loading data from memory or storing data
component, we must integrate them in a way that enables in memory.
them to collaborate effectively and deliver the expected
output for each instruction. Achieving this often requires 3.5. Writeback
making specific modifications to the design of each sub- During this stage, both single-cycle and two-cycle
component to ensure smooth integration with the others. instructions store their results in the register file. It is
Pipeline stages are made by adding registers to store the important to note that two different stages access the register
result from each stage so that another instruction can be file simultaneously. The decode stage reads two source
processed after the first instruction. SDC file is added to registers, while the writeback stage writes the destination
provide constraints for the design so that we can find the register of a previous instruction. This situation can lead to a
maximum operating frequency. hazard on actual silicon (more on hazards below). A hazard
arises when there is a conflict between the source registers
Before uploading the design to the FPGA, we convert being read in the decode stage and the destination register
the desired C code that we want to execute on the RISC-V being written in the writeback stage. In such cases, the same
core we covert into a hex file. This is because our digital memory cells in the register file are read and written
design cannot understand high-level code. Therefore, we simultaneously. The block diagram of the design is shown
need to convert these instructions to hex values that can be below.
read by our design. The path of this hex file is then provided
to the design via Platform Designer (formerly known as 3.6. Block Diagram
Qsys). The design is then compiled and uploaded to the
ALU Register
FPGA. While it's possible to use our own design for the File
PC Decoder Ext.
register file during simulations, when implementing it on the Memory
FPGA, we'll need to rely on the internal memory blocks of Register
the FPGA instead. File
Multiplier
The different functions of the pipeline stages are Instr. RS1
Memory Staller Register
mentioned below [11]:
Divider
Ext.
3.1. Instruction Fetch RS2 Memory
The instructions reside in memory that takes one cycle to Register
read. This memory can be dedicated to SRAM or an
Decoder
Instruction Cache. During the Instruction Fetch stage, a 32- Fig. 1 Block Diagram
bit instruction is fetched from the instruction memory.
4. Results
3.2. Instruction Decode The following results are from the simulation of the
During the instruction decodes stage, the core receives RV32IM core on Intel QuestaSim. The results shown are for
the instruction from the previous fetch stage. The instruction basic operations taking place within the core

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 Anmol Singh et al./ IJVSP, 10(2), 17-21, 2023

4.1. Add Instruction

Fig. 2 Add instruction

4.2. Multiplication Instruction

Fig. 3 Multiplication instruction

4.3. Subtraction Instruction

Fig. 4 Subtraction instruction

4.4. XOR Instruction

Fig. 5 XOR instruction

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 Anmol Singh et al./ IJVSP, 10(2), 17-21, 2023

4.5. Quartus Synthesis Summary

Fig. 6 Hardware utilization

4.6. Synthesized RTL

Fig. 7 Synthesized RTL

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 Anmol Singh et al./ IJVSP, 10(2), 17-21, 2023

5. Conclusion In conclusion, the objective of this paper is to provide

In this paper, we have presented our work, Design and hardware designers and developers with an overview of the
Implementation of RISC V ISA on FPGA and have RISC-V architecture, enabling them to gain a deeper
illustrated and experienced the findings and the specific understanding of its prominent implementations and
features of our design. versions.

The paper also demonstrates the design's 5-stage Additionally, the paper aims to explore advanced
pipeline and branch prediction capabilities whilst illustrating features and their integration within the RISC-V framework,
its functionality through simulation and hardware results. like the 5-stage pipeline and branch prediction, all combined,
Further, the paper also aims to showcase the development of forming a large hardware and software ecosystem.
the architecture core on the DE10 Lite board.

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