Q. 1. Solve (11001)2 — (10101)2.

4. Change the sign and take the I’s complement of the result to get the final
answer.

Question:

1001 — 1101
 Result from Step 1: 0010

Result from Step 2: 1011

Result from Step 3: -.0100

To verify, note that 9 — 13 = — 4

Q. 3. State De-Morgan’s theorem.

Ans. De-Morgan’s theorems are extremely useful in simplifying expressions in

which a product or sum of variables is inverted. The two theorems are

Theorem (1) says that when the OR sum of two variables is inverted, this is the
same as inverting each variable individually and then ANDing these inverted
variables.

Theorem (2) says that when the AND product of two variables is inverted, this is
the same as Inverting each variable individually and then ORing them

For Question
 Q. 5. What is a BCD code? What are its advantages and disadvantages?

Ans. Binary-coded decimal (BCD) information is stored in either packed or

unpacked forms. Packed BCD data are stored as two digits per byte and unpacked
BCD data are stored as one digit per byte. The range of a BCD digit extends from
(0000)2 to (1001)2, 0-9 decimal. Table 2.3 shows some decimal numbers
converted to both packed and unpacked BCD forms.

Advantages and disadvantages of BCD

Redundant codes. Since the maximum decimal digit is 9, the maximum code
that can be represented using each of the 4 bits is 1001. This means that 1010,
1011, 1100, 1101, 1110 and 1111 are effectively redundant (although in some
systems, redundant codes can be used for representing positive and negative
numbers).

Complicated arithmetic operations. The BCD arithmetic operations usually take

longer than ordinary binary arithmetic. Also, it is more complicated. For question, a
“fiddle factor” of 6 is added when performing addition.

Fast conversion between BCD and decimal. The major advantage of BCD is the
ease and the speed with which decimal numbers can be converted into BCD
representation (Think how you convert a large decimal number to its ordinary
binary representation). If very little arithmetic is being done, then slower
performance is a less serious drawback.

Q. 6. Design a circuit that will generate an odd parity bit for 3-bit input and
implement it using exclusive gates.

Ans. As we have studied earlier, a parity bit is an extra bit to be included with
a binary message to make the number of l’s either odd (i.e. odd parity) or even
(i.e. even parity). The message, including the parity bit, is transmitted and then
checked at the receiving end for errors. An error is detected if the checked parity
does not correspond to the one transmitted.

Parity generator: the logic circuit that generates the parity bit in the
transmitter.

Parity checker: the logic circuit that checks the parity in the receiver.

The truth table below is for an odd parity generator for the Transmitting Unit.

Note that the truth table displays property = 2 from the previous page. The
minterms all have an even number of l’s (i.e. 000,011,101,110). Thus the odd
parity generator can be implemented as shown below:
 The truth table below is for an odd parity checker for the Receiving Unit. Note
that the output C of the parity checker is a I when an odd parity error occurs.

Since the function for C consists of the eight minterms with numerical values
having an even number of 0’s, the function can be expressed with XNOR
(equivalence) operators as follows

C = x xnor y xnor z xnor P

The circuit is diagrammed below:

Q. 7. The decimal equivalent of Binary number 11010 is:

(A) 26 (B) 36

(C) 16 (D) 23.

 Ans. (A) 26

Q. 8. 1’s complement representation of decimal number of —17 by

using 5 bit representation is

(A) 11101110 (B) 11011101

(C) 11001100 (D) 00010001.

Ans. (A) 11101110

Q. 9. The excess 3 code of decimal number 26 is:

(A) 01001001 (B) 01011001

(C) 10001001 (D) 01001101.

Ans. (B) 01011001

Q. 10.How may And gates are required to realize Y = CD + EF + G?

(A)4 (B)5

(C)3 (D)2.

Ans. (D) 2.

Q. 11. (a) Convert decimal 177.25 to octal number.

Ans. 177.25

Converting each number in three bit binary

001—111—111.010—101

001111111.010101 in octal number

(b) Perform following subtraction

(i) 11001 — 10110 using l’s complement

(ii) 11011—11001 using 2’s complement.

Ans.
 (1) 11001 — 10110 using l’s complement

Subtract 1010100 - 1000011 using l’s complement:

(c) 11011, — 11001 using 2’s complement

Ans.

Subtract 1010100 - 1000011 using 2’s complement:

Q. 12 (a) Reduce the following equation using k-map

(b) Write the expression for Boolean function

F(A, B, C) = Sm(1, 4, 5, 6, 7) in standard POS form.

Ans. (A+B’C)

Q. 13. (a) Choose the correct or best alternative in the following:

(i) 8 is equal to signed binary number

(A) 10001000 (B) 00001000

(C) 10000000 (D) 11000000.

Ans. (B) 00001000

 (ii) De Morgan’s first theorem shows the equivalence of

(A) OR gate and Exclusive OR gate

(B) NOR gate and Bubbled AND gate

(C) NOR gate and NAND gate

(D) NAND gate and NOT gate

Ans. (B) NOR gate and Bubbled AND gate.

(b) (i) Convert 2222 in Hexadecimal number.

Ans. 2222

Converting each number in three bit binary

0010—0010—0010-0010

001 0001 000100010

(ii) Subtract—27 from 68 using 2’s complements.

Example. Perform the following 2’s complement arithmetic. Also show each
problem in base 10.
Answer: 111100001 ÷ 1101 = 100101

Q. 14. State and prove De-Morgan’s theorems.

 Ans. De-Morgan’s theorems are extremely useful in simplifying expressions in
which

a product or sum of variables is inverted. The two theorems are:

Theorem (1) says that when the OR sum of two variables is inverted, this is the
same as inverting each variable individually and then ANDing these inverted
variables.

Theorem (2) says that when the AND product of two variables is inverted, this
is the same as inverting each variable individually and then ORing them.

For Question

Implications of De-Morgan’s Theorem

For: (x+y)’ x’ * y’

Proof of De Morgan theorem’s in the form of a truth table:

 Q. 16. Minimize the logic function

F (A, B, C, D) = PM (1, 2, 3, 8, 9, 10, 11, 14). d (7, 15)

Use Karnaugh map. Draw the logic circuit for the simplified function
using NOR gates only.

Ans. (AB’+ACD’+A’B’D+CD’)

Q. 17. Find the value of x in the following.

Q. 18. Realize AND gate using NOR gates only.

Ans. Realization of AND gates using NAND and NOR gates

Q.19. Define l’s and 2’s complements.

Ans. Complements are used in digital computers for simplifying the subtraction
operation and logical manipulations. Since A B = A + (-B) and complement systems
provide a convenient way of representing negative numbers, we can convert a
subtraction to an addition. When implemented with digital hardware, it is more
efficient to use complements than to use direct subtraction. Since multiplication and
division correspond to repeated addition and subtraction, respectively, it is possible
to perform the four basic arithmetic operations using only the hardware for addition
when negative numbers are represented in complement form.

One’s complement

A system known as ones’ complement can be used to represent negative

numbers.

The ones’ complement form of a negative binary number is the bitwise NOT applied
to

it the complement of its positive counterpart. Like sign-and-magnitude

representation, one’s complement has two representations of 0: 00000000 (+0)
and 11111111 (“0).

Two’s complement

The problems of multiple representations of 0 and the need for the end-around
carry are circumvented by a system called two’s complement. In two’s complement,
negative numbers are represented by the bit pattern which is one greater (m an
unsigned sense) than the ones’ complement of the positive value.

In two s-complement, there is only one zero (00000000). Negating a number

(whether negative or positive) is done by inverting all the bits and then adding 1 to
that result. Addition of a pair of two’s-complement integers is the same as addition
of a pair of unsigned numbers (except for detection of overflow, if that is done). For
instance, a two’s-complement addition of 127 and -128 gives the same binary bit
pattern as an unsigned addition of 127 and 128,
Q. 22. Simplify the following Boolean functions using K-maps.

(a) F (A, B, C) = S (0, 2, 3, 4, 6)

 (b)F(A,B,C,D)=S(1,3,5, 7,9,15),d(A,B,C,D)=S(4,6,12,13)

Ans. The Karnaugh map, known as a Veitch diagram (KV-map or K-map for
short), is a method to simplify Boolean algebra expressions. The Karnaugh map
reduces the need for extensive calculations by taking advantage of humans’
pattern-recognition capability, permitting the rapid identification and elimination of
potential race hazards.

In a Karnaugh map the Boolean variables are transferred (generally from a truth
table) and ordered according to the principles of Gray code in which only one
variable changes in between squares. Once the table is generated and the output
possibilities are transcribed, the data is arranged into the largest possible groups
containing 2ri cells (n = 0,1,2,3...) and the minterm is generated through the
axiom laws of Boolean algebra.

Q. 25. Simplify the Boolean Functions:

F (w, x, y, z) = S (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)

Ans. Same as Question No. 22.

Q. 26. Draw the gate implementation of the simple Boolean Function

 F (A, B, C) = A’C + A’B + AB’C + BC using and OR gates.

Ans.
Q. 27. What is electronics?

Ans. What is electronics?

The branch of engineering which deals with the flow of electrons through vacuum,
gas or semiconductor is called Electronics.

To understand electronics you have to take two viewpoints to your design:

1. The bottom-up (physical)

2. The top-down (behavioral)

Q. 28. Differentiate between digital and analog electronics.

Ans. Digital electronics is the branch of electronics dealing with discrete levels
of voltage in circuitry. Most digital electronics is based on signals that are coded to
operate at just 2 levels. The idea that just 2 levels are needed to convey
information is not new. Over 200 years ago, the Admiralty telegraph was invented
to convey messages comparatively rapidly over long distances.

George Boole published his famous work. An Investigation of the Laws of Thought
in 1854. In it, he set up the foundations of “Boolean algebra”. Electronic logic really
began to develop from the 1890s when automatic telephone exchanges were
introduced,, to control the routing of telephone circuits.

Digital electronics is a particular behavior where two voltage values or ranges are
used as a basis for communication between electronic components, devices and
systems.

Analog voltages are the real world continuous voltages,

 Analog data implies continuity, continuously varying level information signals,
as contrasted to digital data that is concerned with discrete states, is and Os. The
information content of an analog signal is conveyed by continuously varying some
characteristic such as amplitude, frequency or phase of a voltage or other
characteristic of the signal. Computers, motors, lights and other electrical devices
generate electrical noise (unwanted electrical signals), which produce undesirable
variations on the information content of an analog signal, thus making it error
prone.

Q. 29. Explain the major applications of electronics.

Ans. Applications of Electronic Systems

A major application of electronic systems is in the processing and

transmission of information by electronic signals. The amount of information to be
transmitted at any one time determines the frequency range or bandwidth of the
electronic signal.

The human ear can detect sounds in the range of 20 Hz to 20 kHz. This is
considered to be the range of frequencies that need to be transmitted for a hi-fi
music system. If it is not intended to transmit music but only speech, then the
bandwidth required can be reduced to extend from 300 Hz to 4 kHz. This reduced
bandwidth is the range that normal telephone lines use.

A fax machine is able to send pictures along a telephone line. However, as soon
as a moving picture is required to be transmitted then the bandwidth of the signal
has to increase considerably to accommodate all of the additional information. A
typical colour television picture signal occupies a bandwidth from 50Hz to
approximately 6MHz, or 300 times the bandwidth of a hi-fi music signal. To
transmit information requires either the various signals to be passed along cables
(metal or optical fiber) or to be modulated onto a radio frequency carrier signal.
Most commercial radio stations have a carrier frequency that is greater than 150
kHz and can extend well into the GHz region of the radio spectrum. A television
signal transmitted at a frequency of 487.25MHz will occupy a bandwidth that
extends to 493.25MHz. Some basic applications of electronics systems are
discussed as follows

Audio systems

Each sub-system of the hi-fi system has a specific function which is

detailed below. The tuner receives the radio signals from the aerial and translates
them into audio electrical signals. A strong radio station will produce an output from
the aerial of approximately 5OmV across the tuner input impedance of 75W and
this will result in an audio signal of approximately 300mV.
 The CD player reads the digital information stored on a compact
disc and translates it into an audio electrical signal of approximately 300 mV. At the
moment most CD players are read only. It is expected, though, that within a short
time there will be recordable CD equipment will be commonly available.

The cassette deck records and plays cassette tapes. It produces an

audio electrical signal of approximately 300mV from the varying magnetic fields
stored on the cassette tape.

The microphone changes sounds into electrical signals which can be

recorded onto cassette tape by the cassette deck. There are several different types
of microphone available but a dynamic microphone will have an output of
approximately l0mV.

The pre-amplifier has two main functions. It contains the signal source selector so
that the tuner, CD player etc. can be selected. It also provides extra amplification
of the signals and boosts them to the level required by the amplifier (approximately
2 V). The pre-amplifier will also contain the other controls, e.g., volume, treble,
bass, balance etc.

The amplifier boosts the level of the signal from the pre-amplifier to the
level required by the loudspeakers without distorting the signal. A typical hi-fl
amplifier is capable of delivering 100 watts of electrical power to each loudspeaker.

The loudspeakers change the electrical audio signals into sound. Most hi-
fi speakers nominally have an impedance of 8W, while car speakers have an
impedance of 4W. Most loudspeakers are very inefficient and often more than 95%
of the power delivered to the speaker by the amplifier just heats up the
loudspeaker without being converted into sound.

Radio

The given below Figure shows the basic block diagram of a simple radio
receiver.
 The aerial receives radio waves from transmitting stations, and other sources of
radio waves, which induce alternating currents and voltages in the aerial. These
mall voltages and currents then pass to the radio frequency (RF) tuned circuit which
filter out the required radio station.

The demodulator removes the radio frequency carrier

component and restores the original audio signal. The audio signal is then amplified
to power a loudspeaker or earphones.

Question 3. Convert the decimal number 443.62510 to binary.

For now we will work very mechanically and slowly - we will work much more
quickly later.

1. Break the decimal number into its integer and fractional parts;

— The integer part of 443.62510 is 44310

— The fractional part of 443.62510 is 0.62510 (or .62510 - this form will suit us
better!)

2. Divide the integer part of the number repetitively by 2 until a Zero value results,
recording the remainders from each division, then assemble the remainders, most
recent leftmost, to form the integer part of the result;
 Divide the integer part of the number respective by 2 until
a Zero value results, recording the remainders from each division, then assemble
the remainders, most recent left most, to form the integer part of the result.

3. Multiply the fractional part of the number repetitively by 2 (recording any integer
overflows) until either a Zero value results or we find sufficient digits of accuracy,
then assemble the overflows, most recent rightmost, to form the result’s fractional
part;
The fractional part of the result is 1012 (i.e. 0.1012)

4. Place a radix point between the integer and fractional parts of the result and
write in a subscript to indicate the base.

This is confirmed by question 1 above which converted 110111011.1012 to decimal

yielding the result 443.62510.

Question. Convert 12483.04687510 to octal.

 Question

Use binary arithmetic; find the answers of the followings:

(i) 11101010 + 00110111

 Q. 30. Why NAND and NOR gates are called UNIVERSAL GATES?

Ans. NAND and NOR as UNIVERSAL GATES

Somewhat earlier in this chapter, we mentioned that the basic Boolean gates
were AND, OR, and NOT; and indicated that the NAND and NOR gates could be
considered as “derived”. From the viewpoint of Boolean algebra, this is true. From
the viewpoint of electrical engineering, this is false as the two “derived” gates are
often used to construct the gates for the functions that appear to be logically
simpler.

As an exercise in logic, we show that the NAND (Not AND) gate is a

universal gate in that it can be used to synthesize the AND, OR, and NOT gates. We
begin with the basic NAND.

The basic truth table for the NAND is given by

 Q. 1. List two applications of De-Multiplexer.

Ans. 1. The opposite of the multiplexer circuit, logically enough, is the

demultiplexer. This circuit takes a single data input and one or more address
inputs, and selects which of multiple outputs will receive the input signal.

2. The same circuit can also be used as a decoder, by using the address inputs
as a binary number and producing an output signal on the single output that
matches the binary address input. In this application, the data input line functions
as a circuit enabler — if the circuit is disabled, no output will show activity
regardless of the binary input number.

Q. 4. What do you mean by self starting type counter?

Ans. A self-starting counter is one in which every possible state, even those
not in the desired count sequence, has a sequence of transitions that eventually
leads to a valid counter state. This guarantees that no matter how the counter
starts up, it will eventually enter the proper counter sequence.

In general, it is desirable to enter the counter sequence in as few transitions as

possible, so we would prefer the correct state diagram. However, there may be an
advantage in departing from this rule if a particular sequence of noncounter states
can lead to reduced hardware.
 Q. 5. What is the basic difference between a counter and a shift
register?

Ans. The term register can be used in a variety of specific applications, but in
all cases it refers to a group of flip-flops operating as a coherent unit to hold data.
This is different from a counter, which is a group of flip-flops operating to generate
new data by tabulating it.

In this context, a counter can be viewed as a specialized kind of

register, which counts events and thereby generates data, rather than just holding
the data or changing the way it is handled. More commonly, however, counters are
treated separately from registers. The two are then handled as separate concepts
which work together in many applications, and which have some features in
common. Two of the most common types of shift register counters are the Ring
counter and the Johnson counter. They are basically shift registers with the serial
outputs connected back to the serial inputs in order to produce particular
sequences. These registers are classified as counters because they exhibit a
specified sequence of states.

Q. 7. How many select lines will a 16 to 1 multiplexer will have:

(A) 4 (B)3

(C) 5 (D) 1.

Ans. (A) 4

The block diagram of a 16 to 1 multiplexer is as follows

 Q. 8. How many flip flops are required to construct a decade counter:

(A) 10 (B) 3

(C)4 (D)2.

Ans. (C) 4

A decade counter is one that counts in decimal digits, rather than binary. A
decimal counter may have each digit binary encoded (that is, it may count in
binary-coded decimal, as the 7490 integrated circuit did) or other binary encodings
(such as the bi quinary encoding of the 7490 integrated circuit). Alternatively, it
may have a “fully decoded” or one-hot output code in which each output goes high
in turn; the 4017 was such a circuit. The latter type of circuit finds applications in
multiplexers and demultiplexers, or wherever a scanning type of behavior is useful.
Similar counters with different numbers of outputs are also common. The decade
counter is also known as a mod-l0 counter.
OCTAL TO BINARY ENCODER -

Octal-to-Binary take 8 inputs and provides 3 outputs, thus do the opposite of what
the 3-to-8 decoder does. At any one time, only one input line has a value of 1. The
figure below shows the truth table of an Octal-to-binary encoder.

For an 8-to-3 binary encoder with inputs 10-17 the logic expressions of the
outputs Y0-Y7 are:

Based on the above equations, we can draw the circuit as shown below:
 Q. 11. Explain the working of master slave JK flip-flop.

Ans. The memory elements in a sequential circuit are called flip-flops. A flip-
flop circuit has two outputs, one for the normal value and one for the complement
value of the stored bit. Binary information can enter a flip-flop in a variety of ways
and gives rise to different types of flip-flops.

Master-slave flip-flop is constructed from two separate flip-flops. One circuit

serves as a master and the other as a slave. The logic diagram of an SR flip-flop is
shown in Figure. The master flip-flop is enabled on the positive edge of the clock
pulse CP and the slave flip-flop is disabled by the inverter. The information at the
external R and S inputs is transmitted to the master flip-flop. When the pulse
returns to 0, the master flip-flop is disabled and the slave flip-flop is enabled. The
slave flip-flop then goes to the same state as the master flip-flop.
 The timing relationship is shown in Figure below and is assumed that the flip-
flop is in the clear state prior to the occurrence of the clock pulse. The output state
of the master-slave flip-flop occurs on the negative transition of the clock pulse.
Some master- slave flip-flops change output state on the positive transition of the
clock pulse by having an additional inverter between the CP terminal and the input
of the master.

Q. 12. Explain how Parallel In Serial Out (PISO) shift register works.

Ans. Shift Registers consists of a number of single bit “D-Type Data Latches”
connected together in a chain arrangement so that the output from one data latch
becomes the input of the next latch and so on, thereby moving the stored data
serially from either the left or the right direction. The number of individual Data
Latches used to make up Shift Registers are determined by the number of bits to be
stored with the most common being 8-bits wide. Shift Registers are mainly used to
store data and to convert data from either a serial to parallel or parallel to serial
format with all the latches being driven by a common clock (Clk) signal making
them Synchronous devices.

They are generally provided with a Clear or Reset connection so that they can
be “SET” or “RESET” as required.

Generally, Shift Registers operate in one of four different modes:

• Serial-in to Parallel-out (SIPO)

• Serial-in to Serial-out (SISO)

• Parallel-in to Parallel-out (PIPO)

• Parallel-in to Serial-out (PISO)

 Parallel-in to Serial-out

Parallel-in to Serial-out Shift Registers act in the opposite way to the Serial-in
to Parallel-out one above. The DATA is applied in parallel form to the parallel input
pins PA to PD of the register and is then read out sequentially from the register
one bit at a time from PA to PD on each clock cycle in a serial format.

As this type of Shift Register converts parallel data, such as an 8-bit data word
into serial data it can be used to multiplex many different input lines into a single
serial DATA stream which can be sent directly to a computer or transmitted over a
communications line. Commonly available IC’s include the 74HC165 8-bit Parallel-
in/ Serial-out Shift Registers.

Q. 12. Design a mod-6 up counter using D-type and flip-flops.

Ans.

A mod-6 counter will require three flip-flops. There required relationship

between the present and next states plus the required inputs to the JK flip-flops’ is
shown in

Table: Note that two states are unused.

 D-type implementation

The Karnaugh maps for the next state variables are shown in Table these, and
from minimizing taking advantage of the ‘don’t care’ conditions:

Table: Karnaugh maps for the next state variables for a mod-6 binary up-
counter
 Using the above equations to determine the next state values for the unused
states of 6 (i.e. Q2 QI Q0 110) and 7, we find that they lead to states 7 and 4,
respectively. (The states can also be found by considering the Boolean values used
in the ‘don’t care’ conditions in the Karnaugh maps during minimisation). These are
shown, together with the state diagram in Fig. Which illustrates the sequence of
states the circuit moves through as it is clocked.

Fig. State diagram for the mod-6 binary up-counter implemented using D-type
flip-flops

Note that rather than using the ‘don’t care’ states to aid minimization they
could have been used to ensure the unused count states led to specific states. A
common choice is for them to lead to state 0 so that if either state was entered due
to a circuit error then at the next clock cycle the counter would ‘reset’. (To achieve
this 0’s are simply entered in place of the x’s before the Karnaugh maps are used
for minimization.)

Q. 15. The device which changes from serial data to parallel data is:

(A)Counter (B) Multiplexer

(C)Demultiplexer (D) Flip—Flop.

Ans. (C) Demultiplexer

Q. 16. A device which converts BCD to Seven Segment is called:

(A)Encoder (B) Decoder

(C)Multiplexer (D) Demultiplexer.

 Ans. (A) Encoder

Q. 17. A combinational circuit has 3 inputs A, B, C and output F. F is

true for following input combinations.

A is False, B is True

A is False, C is True

A, B, C are False

A, B, C are True

(a) Write the Truth table for F. Use the convention True = 1 and False = 0.

(b) Write the simplified expression for F in SOP form.

(c) Write the simplified expression for F in POS form.

(d) Draw logic circuit using minimum number of 2-input NAND gates.

Ans. Refer to Question No. 12.

Q. 18. Differentiate between synchronous and asynchronous counters.

Ans. In an asynchronous counter, an external event is used to directly SET or

CLEAR a flip-flop when it occurs. In a synchronous counter however, the external
event is used to produce a pulse that is synchronized with the internal clock. An
example of an asynchronous counter is a ripple counter. Each flip-flop in the ripple
counter is clocked by the output from the previous flip-flop. Only the first flip-flop is
clocked by an external clock. Ahead is an example of a 4-bit ripple counter
 Q. 23. What is Full Adder?

Ans. The full-adder circuit adds three one-bit binary numbers (C A B) and
outputs two one-bit binary numbers, a sum (S) and a carry (Cl). The full-adder is
usually a component in a cascade of adders, which add 8, 16, 32, etc. binary
numbers. The carry input for the full-adder circuit is from the carry output from the
circuit “above” itself in the cascade. The carry output from the full adder is fed to
another full adder “below” itself in the cascade. Basically a full adder is a logic
element which operates on two binary digits and a carry digit from a preceding
stage, producing as output a sum digit and a new carry digit. It is also known as
three-input adder.

Q. 24. What is flag?

Ans. A one-bit register or a flip-flop which indicates overflow, carry, or sign bit
from past or current operations. 8085 microprocessor has a set 5 flip-flops which
serves as the status flags & they are: Sign Flag, Carry Flag, Auxiliary Carry Flag,
and Parity Flag & Zero Flag.

1. Zero flag: if result is 0 than it is set condition i.e.1 otherwise it is reset i.e. is 0.

2. Carry flag: if an extra bit arises than it is set condition i.e.1 otherwise it is
reset i.e. is 0.

3. Sign flag: in it only D7 is considered if D7 is 1 than it is set condition i.e.1 but

if D7 is 0 than it is reset i.e. is 0.

4. Parity flag: if number of l’s in the answer is even than it is set condition i.e.1
otherwise it is reset i.e. is 0.

5. Auxiliary carry flag: if a carry is generated in D3 & passed to D4 than ac flag is

set condition i.e. 1 otherwise it is reset i.e. is 0.

Q. 25. What are decoders?

 Ans. A decoder is a device which does the reverse of an encoder, undoing the
encoding so that the original information can be retrieved. The same method used
to encode is usually just reversed in order to decode. In digital electronics, a
decoder can take the form of a multiple-input, multiple-output logic circuit that
converts coded inputs into coded outputs, where the input and output codes are
different e.g. n-to-2n, binary-coded decimal decoders. Enable inputs must be on for
the decoder to function, otherwise its outputs assume a single “disabled” output
code word. Decoding is necessary in applications such as data multiplexing, 7
segment display and memory address decoding. The example decoder circuit would
be an AND gate because the output of an AND gate is “High” (1) only when all its
inputs are “High.” Such output is called as “active High output”. If instead of AND
gate, the NAND gate is connected the output will be “Low” (0) only when all its
inputs are “High”. Such output is called as “active low output”.

Q. 26. What is don’t care condition?

Ans. We know logic reduction problems where the input conditions were
completely specified. That is, a 3-variable truth table or Karnaugh map had 2’ = 2
or 8-entries, a full table or map. It is not always necessary to fill in the complete
truth table for some real-world problems. We may have a choice to not fill in the
complete table.

For example, when dealing with BCD (Binary Coded Decimal) numbers encoded
as four bits, we may not care about any codes above the BCID range of (0, 1, 2.
.9). The 4-bit binary codes for the hexadecimal numbers (Ah, Bh, Ch, Eh, Fh) are
not valid BCD codes. Thus, we do not have to fill in those codes at the end of a
truth table, or K-map, if we do not care to. We would not normally care to fill in
those codes because those codes (1010, 1011, 1100, 1101, 1110, 1111) will never
exist as long as we are dealing only with BCD encoded numbers. These six invalid
codes are don’t cares as far as we are concerned. That is, we do not care what
output our logic circuit produces for these don’t cares.

Don’t care in a Karnaugh map, or truth table, may be either is or Os, as

long as we don’t care what the output is for an input condition we never expect to
see. We plot these cells with an asterisk, ‘, among the normal is and Os. When
forming groups of cells, treat the don’t care cell as either a 1 or a 0, or ignore the
don’t cares. This is helpful if it allows us to form a larger group than would
otherwise be possible without the don’t cares. There is no requirement to group all
or any of the don’t cares. Only use them in a group if it simplifies the logic.

Q. 27. (a) What is shift register?

Ans. In digital circuits, a shift register is a cascade ol flip flops, sharing the
same clock, which has the output of any one but the last flip-flop connected to the
“data” input of the next one in the chain, resulting in a circuit that shifts by one
position the one-dimensional “bit array” stored in it, shifting in the data present at
its input and shifting out the last bit in the array, when enabled to do so by a
transition of the clock input. More generally, a shift register may be
multidimensional, such that its “data in” input and stage outputs are themselves bit
arrays: this is implemented simply by running several shift registers of the same
bit-length in parallel.

Shift registers can have both parallel and serial inputs and outputs.
These are often configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-
out (PISO). There are also types that have both serial and parallel input and types
with serial and parallel output. There are also bi-directional shift registers which
allow shifting in both directions: L-R or R-L

Q. 28. Explain Edge Triggered Flip-Flop.

Ans. In digital circuits, a flip-flop is a term referring to an electronic circuit (a

bistable multivibrator) that has two stable states and thereby is capable of serving
as one bit of memory. Today, the term flip-flop has come to mostly denote non—
transparent (clocked or edge-triggered) devices, while the simpler transparent ones
are often referred to as latches; however, as this distinction is quite new, the two
words are sometimes used interchangeably (see history).

A flip-flop is usually controlled by one or two control signals and/or a gate or

clock signal. The output often includes the complement as well as the normal
output. As flip-flops are implemented electronically, they require power and ground
connections

An edge-triggered flip-flop changes states either at the positive edge (rising edge)
or at the negative edge (falling edge) of the clock pulse on the control input. The
three basic types are introduced here: S-R, J-K and D.
 Notice the small triangle, called the dynamic input indicator, is used to
identify an edge-triggered flip-flop.

Positive edge-triggered (without bubble at Clock input): S-R, J-K and D.

Negative edge-triggered (with bubble at Clock input):S-R, J-K and D.

The S-R, J-K and D inputs are called synchronous inputs because data on
these inputs are transferred to the flip-flop’s output only on the triggering edge of
the clock pulse. On the other hand, the direct set (SET and clear (CLR) inputs are
called asynchronous inputs, as they are inputs that affect the state of the flip-flop
independent of the clock. For the synchronous operations to work properly, these
asynchronous inputs must both be kept LOW.

Edge-triggered S-R flip-flop

The basic operation is illustrated below, along with the truth table for this type
of flip-flop. The operation and truth table for a negative edge-triggered flip-flop are
the same as those for a positive except that the falling edge of the clock pulse is
the triggering edge.

As S=1, R = 0. Flip-flop SETS on the rising.

Note that the S and R inputs can be changed at any time when the clock input is
LOW or HIGH (except for a very short interval around the triggering transition of
the clock) without affecting the output. This is illustrated in the timing diagram
below:
Edge-triggered J-K flip-flop

The J-K flip-flop works very similar to S-R flip-flop. The only difference is
that this flip-flop has NO invalid state. The outputs toggle (change to the opposite
state) when both J and K inputs are HIGH. The truth table is shown below.

Edge-triggered D flip-flop

The operation of a D flip-flop is much simpler. It has only one input

addition to the clock. It is very useful when a single data bit (0 or 1) is to be stored.
If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs
and stores a 1. If there is a LOW on the D input when a clock pulse is applied, the
flip-flop RESETs and stores a 0. The truth table below summarizes the operations of
the positive edge-triggered D flip-flop. As before, the negative edge-triggered flip-
flop works the same except that the falling edge of the clock pulse is the triggering
edge.

While the master-slave U flip flop is also triggered on the edge of a clock, its
components are each triggered by clock levels. The “edge-triggered D flip-flop”
does not have the master-slave properties.
Uses

• A single flip-flop can be used to store one bit, or binary digit, of data. See preset.

• Any one of the flip-flop types can be used to build any of the others.

• Many logic synthesis tools will not use any other type than D flip-flop and D latch.

• Level sensitive latches cause problems with Static Timing Analysis (STA) tools and
Design For Test (DFT). Therefore, their usage is often discouraged.

• One use is to build finite state machines from electronic logic. The flip-flops
remember the machine’s previous state, and digital logic uses that state to
calculate the next state.

Q.29. Explain the working of half adder and full adder? How can we
construct full adder using half adders?
 Ans. Half Adder and Full Adder.

A single bit binary adder circuit basically adds two bits and a carry bit,
generated by the addition of the least significant bits. The output of the single bit
adder circuit generates a sum bit and a carry bit. A single digit binary adder circuit
therefore has three inputs, one representing single bit number A, the other
representing the single bit number B and the third bit represents the single bit
carry. The single bit binary adder has two bit output. One bit represents the Sum
between numbers A and B. The other bit represents the carry bit generated due to
addition.

1. Half-Adder

A Half-Adder can be fully described in terms of its Truth table, its

Sum and Carry Out Boolean Expressions and the circuit Implementation.

Half-Adder Truth Table -

The Half-Adder has a 2-bit input and a 2-bit output. The truth table of the Half
Adder has two input columns representing the two single bit numbers A and B. The
truth table also has two output columns representing the Sum bit and Carry Out bit.
Half –Adder Sum & Carry Out Boolean Expressions

The Sum and Carry Out expressions of the Half-Adder can be determined from
the truth table. The Half-Adder Sum and Carry Out outputs are defined by the
expressions

Half-Adder Logic Circuit

The Half-Adder Logic Circuit can be directly implemented from the Sum and
Carry Out Boolean expressions. Figure 14.6

1. Full-Adder

A Full-Adder can be fully described in terms of its Truth table, its Sum
and Carry Out Boolean Expressions and the circuit Implementation.

Full-Adder Truth table

The Full-Adder has a 3-bit input and a 2-bit output. The truth table of
the Full- Adder has three input columns representing the two single bit numbers A,
B and the Carry In bit. The truth table also has two output columns representing
the Sum bit and Carry Out bit. Table 14.4
Full-Adder Sum & Carry Out Boolean Expressions

The Sum and Carry Out expressions of the Full-Adder can be determined from
the truth table. The Full-Adder Sum and Carry Out outputs are defined by the
expressions.

Full-Adder Logic Circuit

The Full-Adder Logic Circuit can be directly implemented from the Sum and
Carry out Boolean expressions.
Forming a Full-Adder using Half-Adders

A 1-bit Full-Adder can be implemented by combining together two Half-

Adders.

Q. 30. What are the applications of demux?

Ans. Applications of Demultiplexer

Demultiplexer is used to connect a single source to multiple destinations. One use

of the Demultiplexer is at the output of the ALU circuit. The output of the ALU has
to be stored in one of the multiple registers or storage units. The Data input of the
Demultiplexer is connected to the output of the ALU. Each output of the
Demultiplexer is connected to each of the multiple registers. By selecting the
appropriate output data from the ALU is routed to the appropriate register for
storage.

The second use of the Demultiplexer is the reconstruction of Parallel Data from the
incoming serial data stream. Serial data arrives at the Data input of the
Demultiplexer at fixed time intervals. A counter attached to the Select inputs of the
Demultiplexer routes the incoming serial bits to successive outputs where each bit
is stored. When all the bits have been stored, data can be read out in parallel.

Q. 31. Explain the use of parity bit in details.

Ans. Example: Parity may also be calculated in software using a shift register
to count the number of ‘1’ bits in each byte. When the calculated parity from the
received character does not match the value of the received parity bit, then a parity
error is said to have occurred, and the character is normally discarded. This parity
check detects any number of odd errors but passes any number of even errors
without detecting an error.

Q. 32. What are Race conditions?

Race Conditions

Race condition - Two or more variables are required to change at the same time.

Critical race - Depending on the outcome of the race the circuit may end up in one
of two or more possible states. The SR latch above demonstrates a critical race
condition.

The two possible final states are Q=1, Q’=O and Q0, Q’l.

Non critical race - regardless of the outcome of the race the circuit ends up in the
same state. For example:

Q. 33. Explain the working of seven segment display.

Ans. 7-Segment Display

In the appendix you will find the specifications for the MC14495 BCD to Seven
Segment Decoder/Driver. This device has seven outputs and four inputs. The
outputs are normally in the “0” state but rise to the “1” state for the proper
segments of a seven-segment display corresponding to the binary coded decimal
input:

There are a variety of devices available for seven segment display, utilizing gas
discharge, light emitting diode arrays and various other gadgets. For display in the
lab sessions, we will use a seven segment display using LEDs.

Any source of current for LEDs must have current limiting resistors. With many
seven segment display drivers these resistors are connected between the driver
and the LEDs. The MC14495 is unusual in that it has the current limiting resistors
included in the driver chip.
Q. 1. List two applications of De-Multiplexer.

Ans. 1. The opposite of the multiplexer circuit, logically enough, is the

demultiplexer. This circuit takes a single data input and one or more address
inputs, and selects which of multiple outputs will receive the input signal.

2. The same circuit can also be used as a decoder, by using the address inputs as a
binary number and producing an output signal on the single output that matches
the binary address input. In this application, the data input line functions as a
circuit enabler — if the circuit is disabled, no output will show activity regardless of
the binary input number.

Q.5. What is the basic difference between a counter and a shift register?

Ans. The term register can be used in a variety of specific applications, but in all
cases it refers to a group of flip-flops operating as a coherent unit to hold data. This
is different from a counter, which is a group of flip-flops operating to generate new
data by tabulating it.

In this context, a counter can be viewed as a specialized kind of

register, which counts events and thereby generates data, rather than just holding
the data or changing the way it is handled. More commonly, however, counters are
treated separately from registers. The two are then handled as separate concepts
which work together in many applications, and which have some features in
common. Two of the most common types of shift register counters are the Ring
counter and the Johnson counter. They are basically shift registers with the serial
outputs connected back to the serial inputs in order to produce particular
sequences. These registers are classified as counters because they exhibit a
specified sequence of states.

Q. 7. How many select lines will a 16 to 1 multiplexer will have:

(A) 4 (B)3

(C) 5 (D) 1.

Ans. (A) 4

The block diagram of a 16 to 1 multiplexer is as follows

Q. 8. How many flip flops are required to construct a decade counter:

(A) 10 (B) 3

(C)4 (D)2.

Ans. (C) 4

A decade counter is one that counts in decimal digits, rather than binary. A decimal
counter may have each digit binary encoded (that is, it may count in binary-
coded decimal, as the 7490 integrated circuit did) or other binary encodings (such
as the bi quinary encoding of the 7490 integrated circuit). Alternatively, it may
have a “fully decoded” or one-hot output code in which each output goes high in
turn; the 4017 was such a circuit. The latter type of circuit finds applications in
multiplexers and demultiplexers, or wherever a scanning type of behavior is useful.
Similar counters with different numbers of outputs are also common. The decade
counter is also known as a mod-l0 counter.
Q. 9. Implement the following function using a 3 line to 5 line decoder

S(A, B, C) = Sm(1, 2, 4 7)

C(A, B, C) = Sm (3, 5, 6, 7)

Ans. You have 5 input lines and you need output lines. Now let lines are

d0 lsb

d1

d2

d3

d4 msb

connect d3 and d4 to 2-to-4 line decoder

connect do, dl, and d2 to all 3-to-8 line decoders.

Now connect output of 2-to-4 line decoder to enable pins of 3-to-8 line decoders
such that the first output makes first 3-to-8 line decoders enable. That’s it 32
output of 3-to-8 line decoders are your required output.
OCTAL TO BINARY ENCODER -

Octal-to-Binary take 8 inputs and provides 3 outputs, thus do the opposite of what
the 3-to-8 decoder does. At any one time, only one input line has a value of 1. The
figure below shows the truth table of an Octal-to-binary encoder.
For an 8-to-3 binary encoder with inputs 10-17 the logic expressions of the
outputs Y0-Y7 are:

Based on the above equations, we can draw the circuit as shown below:

Q. 11. Explain the working of master slave JK flip-flop.

Ans. The memory elements in a sequential circuit are called flip-flops. A flip-flop
circuit has two outputs, one for the normal value and one for the complement value
of the stored bit. Binary information can enter a flip-flop in a variety of ways and
gives rise to different types of flip-flops.
 Master-slave flip-flop is constructed from two separate flip-flops. One circuit
serves as a master and the other as a slave. The logic diagram of an SR flip-flop is
shown in Figure. The master flip-flop is enabled on the positive edge of the clock
pulse CP and the slave flip-flop is disabled by the inverter. The information at the
external R and S inputs is transmitted to the master flip-flop. When the pulse
returns to 0, the master flip-flop is disabled and the slave flip-flop is enabled. The
slave flip-flop then goes to the same state as the master flip-flop.

The timing relationship is shown in Figure below and is assumed that the flip-flop is
in the clear state prior to the occurrence of the clock pulse. The output state of the
master-slave flip-flop occurs on the negative transition of the clock pulse. Some
master- slave flip-flops change output state on the positive transition of the clock
pulse by having an additional inverter between the CP terminal and the input of the
master.

Q. 21. Draw the circuit diagram of a mod-5 counter and convert it into
decade counter.
Ans. Decade counters and the general Modulo-n counter

The decade counter resets to zero by every 10th pulse. The output
known as binary coded decimal (BCD) is the same as a 4-bit binary scale up to
decimal number 9. Beyond 9, the counter repeats, starting again from 0. The reset
at 10 is so fast that you do not see it with a LED. The more general case is a
Module-n counter, which resets to zero for every n-th pulse. A decade counter is
the same as a Module-l0 counter.

We will illustrate how the conversion is done for a 3-bit Modulo-5

counter. You will work out the details for a 4-bit Decade counter.