Cortex m3 Registers:

The Cortex-M3 processor has registers R0 through R15 ,R13 (the stack pointer) is banked, with
only one copy of the R13 visible at a time
R0–R12: General-Purpose Registers R0–R12 are 32-bit general-purpose registers for data
operations. Some 16-bit Thumb® instructions can only access a subset of these registers (low
registers, R0–R7)
R13: Stack Pointers The Cortex-M3 contains two stack pointers (R13). They are banked so that
only one is visible at a time. The two stack pointers are as follows:
Main Stack Pointer (MSP): The default stack pointer, used by the operating system (OS) kernel
and exception handlers
Process Stack Pointer (PSP): Used by user application code The lowest 2 bits of the stack
pointers are always 0, which means they are always word aligned
R14: The Link Register When a subroutine is called, the return address is stored in the link
register.
R15: The Program Counter The program counter is the current program address. This register
can be written to control the program flow.
Special Registers The Cortex-M3 processor also has a number of special registers (see Figure
2.3). They are as follows:
• Program Status registers (PSRs)
• Interrupt Mask registers (PRIMASK, FAULTMASK, and BASEPRI)
•Control register (CONTROL) These registers have special functions and can be accessed only
by special instructions. They cannot be used for normal data processing.
Cortex m3 Operation Modes:
The Cortex-M3 processor has two modes and two privilege levels. The operation modes (thread
mode and handler mode) determine whether the processor is running a normal program or
running an exception handler like an interrupt handler or system exception handler .
The privilege levels (privileged level and user level) provide a mechanism for safeguarding
memory accesses to critical regions as well as providing a basic security model. When the
processor is running a main program (thread mode), it can be either in a privileged state or a user
state, but exception handlers can only be in a privileged state.
When the processor exits reset, it is in thread mode, with privileged access rights. In the
privileged state, a program has access to all memory ranges (except when prohibited by MPU
settings) and can use all supported instructions. Software in the privileged access level can
switch the program into the user access level using the control register. When an exception takes
place, the processor will always switch back to the privileged state and return to the previous
state when exiting the exception handler. A user program cannot change back to the privileged
state by writing to the control register.
It has to go through an exception handler that programs the control register to switch the
processor back into the privileged access level when returning to thread mode. The separation of
privilege and user levels improves system reliability by preventing system configuration registers
from being accessed or changed by some untrusted programs. If an MPU is available, it can be
used in conjunction with privilege levels to protect critical memory locations, such as programs
and data for OSs.

Cortex m3 address map:

The Cortex-M3 has a predefined memory map. This allows the built-in peripherals, such as the
interrupt controller and the debug components, to be accessed by simple memory access
instructions. Thus, most system features are accessible in C program code. The predefined
memory map also allows the Cortex-M3 processor to be highly optimized for speed and ease of
integration in system-on-a-chip (SoC) designs. Overall, the 4 GB memory space can be divided
into ranges as shown in Figure 2.6. The Cortex-M3 design has an internal bus infrastructure
optimized for this memory usage. In addition, the design allows these regions to be used
differently. For example, data memory can still be put into the CODE region, and program code
can be executed from an external Random Access Memory (RAM) region.

Cortex m3 The Instruction Set:

The Cortex-M3 supports the Thumb-2 instruction set. This is one of the most important features
of the Cortex-M3 processor because it allows 32-bit instructions and 16-bit instructions to be
used together for high code density and high efficiency. It is flexible and powerful yet easy to
use.
In previous ARM processors, the central processing unit (CPU) had two operation states: a 32-bit
ARM state and a 16-bit Thumb state. In the ARM state, the instructions are 32 bits and can
execute all supported instructions with very high performance. In the Thumb state, the
instructions are 16 bits, so there is a much higher instruction code density, but the Thumb state
does not have all the functionality of ARM instructions and may require more instructions to
complete certain types of operations. To get the best of both worlds, many applications have
mixed ARM and Thumb codes. However, the mixed-code arrangement does not always work
best.
There is overhead (in terms of both execution time and instruction space, see Figure 2.7) to
switch between the states, and ARM and Thumb codes might need to be compiled separately in
different files. This increases the complexity of software development and reduces maximum
efficiency of the CPU core. With the introduction of the Thumb-2 instruction set, it is now
possible to handle all processing requirements in one operation state.
There is no need to switch between the two. In fact, the Cortex-M3 does not support the ARM
code. Even interrupts are now handled with the Thumb state. (Previously, the ARM core entered
interrupt handlers in the ARM state.) Since there is no need to switch between states, the Cortex-
M3 processor has a number of advantages over traditional ARM processors, such as:
• No state switching overhead, saving both execution time and instruction space
• No need to separate ARM code and Thumb code source files, making software development
and maintenance easier
• It’s easier to get the best efficiency and performance, in turn making it easier to write software,
because there is no need to worry about switching code between ARM and Thumb to try to get
the best density/performance
The Cortex-M3 processor has a number of interesting and powerful instructions. Here are a few
examples:
• UFBX, BFI, and BFC: Bit field extract, insert, and clear instructions
• UDIV and SDIV: Unsigned and signed divide instructions
• WFE, WFI, and SEV: Wait-For-Event, Wait-For-Interrupts, and Send-Event; these allow the
processor to enter sleep mode and to handle task synchronization on multiprocessor systems
• MSR and MRS: Move to special register from general-purpose register and move special
register to general-purpose register; for access to the special registers
Cortex m3 exceptions:
The Cortex-M3 processor implements a new exception model, introduced in the ARMv7-M
architecture. This exception model differs from the traditional ARM exception model, enabling
very efficient exception handling. It has a number of system exceptions plus a number of
external Interrupt Request (IRQs) (external interrupt inputs). There is no fast interrupt (FIQ) (fast
interrupt in ARM7/ARM9/ ARM10/ARM11) in the Cortex-M3; however, interrupt priority
handling and nested interrupt support are now included in the interrupt architecture. Therefore, it
is easy to set up a system that supports nested interrupts (a higher-priority interrupt can override
or preempt a lower-priority interrupt handler) and that behaves just like the FIQ in traditional
ARM processors.
Write buffer:
To prevent bus wait cycles from stalling the processor during data stores, buffered stores to the
DCode and System buses go through a one-entry write buffer. If the write buffer is full,
subsequent accesses to the bus stall until the write buffer has drained. The write buffer is only
used if the bus waits the data phase of the buffered store, otherwise the transaction completes on
the bus.DMB and DSB instructions wait for the write buffer to drain before completing. If an
interrupt comes in while DMB or DSB is waiting for the write buffer to drain, the processor
returns to the instruction following the DMB or DSB after the interrupt completes. This is
because interrupt processing acts as a memory barrier operation.
Bit-banding:
Bit-banding maps a complete word of memory onto a single bit in the bit-band region. For
example, writing to one of the alias words sets or clears the corresponding bit in the bit-band
region. This enables every individual bit in the bit-banding region to be directly accessible from
a word-aligned address using a single LDR instruction. It also enables individual bits to be
toggled without performing a read-modify-write sequence of instructions.
The processor memory map includes two bit-band regions. These occupy the lowest 1MB of the
SRAM and Peripheral memory regions respectively. These bit-band regions map each word in an
alias region of memory to a bit in a bit-band region of memory.
The System bus interface contains logic that controls bit-band accesses as follows:
 It remaps bit-band alias addresses to the bit-band region.
 For reads, it extracts the requested bit from the read byte, and returns this in the Least
Significant Bit (LSB) of the read data returned to the core.
 For writes, it converts the write to an atomic read-modify-write operation.
 The processor does not stall during bit-band operations unless it attempts to access the
System bus while the bit-band operation is being carried out.
The memory map has two 32-MB alias regions that map to two 1-MB bit-band regions:
 Accesses to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region.
 Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band
region.
A mapping formula shows how to reference each word in the alias region to a corresponding bit,
or target bit, in the bit-band region. The mapping formula is:
bit_word_offset = (byte_offset x 32) + (bit_number × 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
 bit_word_offset is the position of the target bit in the bit-band memory region.
 bit_word_addr is the address of the word in the alias memory region that maps to the
targeted bit.
 bit_band_base is the starting address of the alias region.
 byte_offset is the number of the byte in the bit-band region that contains the targeted bit.
 bit_number is the bit position, 0 to 7, of the targeted bit.

NVIC functional description:

The NVIC supports up to 240 interrupts each with up to 256 levels of priority. You can change
the priority of an interrupt dynamically. The NVIC and the processor core interface are closely
coupled, to enable low latency interrupt processing and efficient processing of late arriving
interrupts. The NVIC maintains knowledge of the stacked, or nested, interrupts to enable tail-
chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can cause interrupts to enter
a pending state in user mode if you enable this capability using the Configuration Control
Register. Any other user mode access causes a bus fault.
You can access all NVIC registers using byte, halfword, and word accesses unless otherwise
stated. NVIC registers are located within the SCS.
All NVIC registers and system debug registers are little-endian regardless of the endianness state
of the processor.
Processor exception handling is described in Exceptions.

NVIC programmers model

Interrupt Controller Type Register, ICTR
The ICTR characteristics are:
Purpose
Shows the number of interrupt lines that the NVIC supports.
Usage Constraints
There are no usage constraints.
Configurations
This register is available in all processor configurations.
Attributes
 Functions of arm cortex m3

The ARM Cortex-M3 processor provides various functions that enable developers to write
software for microcontrollers based on this core. These functions contribute to efficient
program execution, memory management, interrupt handling, and system control. Here are
some key functions of the ARM Cortex-M3:

1. Core Functions:
 Arithmetic and Logic Unit (ALU): The Cortex-M3 processor includes an ALU that
performs arithmetic operations (addition, subtraction, multiplication, and division)
and logical operations (AND, OR, XOR, etc.) on data.
 Barrel Shifter: The processor's barrel shifter allows efficient shifting and rotation
operations on data, facilitating bit manipulation and data handling.
 Pipeline Architecture: The Cortex-M3 utilizes a three-stage pipeline architecture that
improves instruction throughput and efficiency by overlapping instruction fetch,
decode, and execution stages.
 Thumb-2 Instruction Set: The Cortex-M3 uses the Thumb-2 instruction set
architecture, which combines 16-bit Thumb instructions for code density and 32-bit
ARM instructions for performance.
2. Memory Management:
 Memory Protection Unit (MPU): The Cortex-M3 supports an optional MPU that
enables memory protection and access control by defining regions with different
attributes (read, write, execute permissions).
 Stack Management: The processor provides stack operations and stack pointer
management for handling function calls, interrupts, and exception handling.
3. Interrupt Handling:
 Nested Vectored Interrupt Controller (NVIC): The Cortex-M3 includes an NVIC that
manages interrupts and exceptions. It supports configurable interrupt priorities and
allows nested interrupts.
 Interrupt Vector Table (IVT): The processor has an IVT that stores the addresses of
interrupt service routines (ISRs) and exception handlers.
4. System Control:
 Power Management: The Cortex-M3 provides power management features, such as
clock gating and sleep modes, to optimize power consumption.
 System Timer: The processor may include a system timer that generates periodic
interrupts, enabling precise timing and timekeeping functionality.
5. Debug and Trace:
 Debug and Trace Unit (DWT): The Cortex-M3 processor incorporates a DWT that
provides advanced debugging and profiling capabilities, such as instruction and data
tracing, cycle counting, and event monitoring.
6. Floating-Point Unit (FPU) (optional):
 Some Cortex-M3 implementations include an optional FPU for executing floating-
point operations in hardware, enhancing numerical computation performance.
 Interfaces of arm cortex m3:

The ARM Cortex-M3 processor provides various interfaces to connect and communicate
with external devices and peripherals. These interfaces enable data transfer, control signals,
and communication protocols. Here are some of the commonly used interfaces supported by
the ARM Cortex-M3:

1. GPIO (General-Purpose Input/Output):

 The Cortex-M3 provides GPIO pins that can be configured as inputs or outputs to
interface with external devices, such as sensors, buttons, LEDs, and other digital
peripherals.
2. UART (Universal Asynchronous Receiver/Transmitter):
 UART is a serial communication interface that allows for asynchronous data
transmission between the microcontroller and other devices. The Cortex-M3 typically
supports one or more UART interfaces for serial communication.
3. SPI (Serial Peripheral Interface):
 SPI is a synchronous serial communication interface that allows for full-duplex data
transfer between the Cortex-M3 and peripheral devices, such as sensors, display
modules, and memory chips.
4. I2C (Inter-Integrated Circuit):
 I2C is a multi-master, multi-slave serial communication interface used for low-speed
communication between integrated circuits. The Cortex-M3 often includes one or
more I2C interfaces for connecting to devices like sensors, EEPROMs, and real-time
clocks.
5. CAN (Controller Area Network):
 CAN is a widely used serial communication protocol for real-time, high-reliability
communication in automotive and industrial applications. Some Cortex-M3
microcontrollers offer built-in CAN controllers for interfacing with CAN networks.
6. USB (Universal Serial Bus):
 USB is a popular interface used for connecting various peripherals to a host device.
Some Cortex-M3 microcontrollers feature USB interfaces for connecting to USB
devices, such as mice, keyboards, storage devices, and communication modules.
7. Ethernet:
 Ethernet interfaces are available on some advanced Cortex-M3-based
microcontrollers, enabling networking capabilities for applications requiring internet
connectivity or communication with other devices over Ethernet.
8. Timers and PWM (Pulse Width Modulation):
 The Cortex-M3 incorporates timers and PWM channels that generate precise timing
signals or analog-like output signals. These are often used for tasks such as timing
measurement, generating audio signals, controlling motors, and dimming LEDs.
9. ADC (Analog-to-Digital Converter):
 The Cortex-M3 may include one or more ADC channels for converting analog
signals, such as voltage or current, into digital values that can be processed by the
microcontroller.
Delay program:

Programmers models:

the programmer's model in the ARM Cortex-M3 processor architecture defines the set of
registers and memory-mapped control registers that are used to program and control the
behavior of the processor.

Parallel input output in arm cortex m3 processors

The ARM Cortex-M3 processor supports parallel input/output (PIO) operations through its
General Purpose Input/Output (GPIO) pins. The GPIO pins can be configured as either input
or output and can be used to communicate with external devices or to interface with on-board
peripherals.

To use the PIO functionality in the Cortex-M3 processor, you need to configure the GPIO
pins using the appropriate registers. The configuration process involves setting the pin
direction (input or output), the pin mode (push-pull or open-drain), and the pin speed (low,
medium, or high). Once configured, the PIO pins can be accessed and manipulated using the
GPIO register set.

In addition to PIO, the Cortex-M3 processor also supports other input/output operations, such
as serial communication (USART, SPI, I2C), analog-to-digital conversion (ADC), and
digital-to-analog conversion (DAC). These operations can be used to communicate with
external devices, read sensors, and generate analog signals.

Overall, the Cortex-M3 processor provides a flexible and powerful platform for developing
embedded systems with a wide range of input/output capabilities.
 Arm cortex m3 processor programmers models
The ARM Cortex-M3 processor is a 32-bit microcontroller core designed for low-power and
high-performance applications. It is widely used in embedded systems, especially in
microcontrollers and other similar devices. There are various models of ARM Cortex-M3
processors available in the market, with different features and specifications. Some popular
models include:

1. STM32F103C8T6: This is a popular model of the ARM Cortex-M3 processor from

STMicroelectronics. It has 64 KB of Flash memory, 20 KB of SRAM, and runs at a
maximum clock speed of 72 MHz.
2. LPC1768: This is another popular model of the ARM Cortex-M3 processor from NXP
Semiconductors. It has 512 KB of Flash memory, 64 KB of SRAM, and runs at a maximum
clock speed of 100 MHz.
3. AT91SAM3X8E: This is a model of the ARM Cortex-M3 processor from Atmel
Corporation. It has 512 KB of Flash memory, 96 KB of SRAM, and runs at a maximum clock
speed of 84 MHz.
4. EFM32GG990F1024: This is a model of the ARM Cortex-M3 processor from Silicon Labs.
It has 1 MB of Flash memory, 128 KB of SRAM, and runs at a maximum clock speed of 48
MHz.

Programmers working with ARM Cortex-M3 processors can use various software tools to
develop and debug their code. Some popular software tools include:

1. Keil µVision IDE: This is a popular Integrated Development Environment (IDE) for ARM
Cortex-M processors. It includes a code editor, compiler, linker, debugger, and other useful
tools.
2. GNU Toolchain for ARM: This is a collection of open-source software tools for developing
and debugging software for ARM processors. It includes a C/C++ compiler, assembler,
linker, debugger, and other utilities.
3. IAR Embedded Workbench: This is a commercial IDE for ARM Cortex-M processors. It
includes a code editor, compiler, linker, debugger, and other tools for developing and
debugging embedded software.
4. Atmel Studio: This is an IDE for developing software for Atmel microcontrollers, including
those based on ARM Cortex-M processors. It includes a code editor, compiler, linker,
debugger, and other useful tools.

Programming techniques of arm cortex m3

The ARM Cortex-M3 is a 32-bit microcontroller architecture used in embedded systems.
Some of the programming techniques used in ARM Cortex-M3 include:

1. Assembly language programming: Assembly language is a low-level language that is used to

write programs for microcontrollers. ARM Cortex-M3 supports assembly language
programming, which can be used to write optimized and efficient code for the
microcontroller.
2. C language programming: C is a high-level programming language that is widely used for
embedded systems programming. ARM Cortex-M3 supports C language programming,
which makes it easy to write complex programs for the microcontroller.
3. Interrupt programming: Interrupts are used to handle external events and generate responses
in real-time. ARM Cortex-M3 supports interrupt programming, which can be used to
implement real-time control and communication systems.
4. Direct Memory Access (DMA): DMA is a technique used to transfer data between memory
and peripherals without involving the CPU. ARM Cortex-M3 supports DMA, which can be
used to improve the performance and efficiency of data transfer operations.
5. Power management: ARM Cortex-M3 includes various power management features, such as
sleep modes and

Stack and stack pointer in arm cortex m3

In ARM Cortex-M3 architecture, the stack is a region of memory used to store temporary
data and function call information. The stack pointer is a register that holds the address of the
current top of the stack. When a function is called, the processor automatically stores some
registers and function parameters onto the stack, and when the function returns, the processor
pops these values off the stack and restores the saved registers.

The stack pointer is typically initialized at system startup to point to the top of the available
memory region reserved for the stack. As data is pushed onto the stack, the stack pointer is
decremented, and as data is popped off the stack, the stack pointer is incremented.

Here's an example of how to use the stack and stack pointer in ARM Cortex-M3 assembly
language programming:
 a value onto
the stack PUSH {r0} ; Push multiple values onto the stack PUSH {r1-r3} ; Pop a value off
the stack POP {r0} ; Pop multiple values off the stack POP {r1-r3}

In this example, the MOV instruction initializes the stack pointer to the address 0x20001000.
The PUSH instruction pushes a value or multiple values onto the stack, and the POP
instruction pops a value or multiple values off the stack. The {} notation is used to specify the
registers to push or pop. When pushing or popping multiple registers, the registers are listed
in order of decreasing register number.

It's important to note that the stack grows downward in memory, so as data is pushed onto the
stack, the stack pointer is decremented. It's also important to ensure that there is enough
memory allocated for the stack to avoid stack overflow issues.

Subroutines in arm cortex m3

Subroutines are a fundamental programming concept in ARM Cortex-M3 architecture that
allow a section of code to be called from multiple locations in a program. In assembly
language programming, subroutines are typically implemented using a branch-and-link
instruction, which stores the return address on the stack and branches to the subroutine
address.
Here's an example of how to implement a subroutine in ARM Cortex-M3 assembly language
programming:

program

In this example, the my_subroutine subroutine is defined using a label. The subroutine code
is executed when it's called using the BL (branch-and-link) instruction. The BL instruction
saves the return address on the stack and branches to the address of the subroutine. The BX
instruction is used to return to the calling function. The lr (link register) is a register that
holds the return address when a subroutine is called.

The main function calls the my_subroutine subroutine using the BL instruction. After the
subroutine returns, the program continues to execute the code after the BL instruction.

It's important to note that subroutines should always save the registers they modify on the
stack and restore them before returning to the calling function. This ensures that the calling
function's state is preserved and avoids unexpected behavior.

parameter passing in arm cortex m3

Parameter passing is a common programming concept in ARM Cortex-M3 architecture that
allows values to be passed to a subroutine or function for processing. There are several ways
to pass parameters in ARM Cortex-M3 assembly language programming, including passing
values in registers or on the stack.
Here's an example of how to pass parameters in ARM Cortex-M3 assembly language
programming using registers:

In this example, the my_subroutine subroutine takes two parameters, which are passed in
registers r0 and r1. The ADD instruction adds the two parameters and stores the result in
register r2. The BX instruction is used to return to the calling function.

The main function sets the values of the two parameters using the MOV instruction, and then
calls the my_subroutine subroutine using the BL instruction. After the subroutine returns,
the program continues to execute the code after the BL instruction.

It's important to note that the registers used for parameter passing should be saved by the
subroutine if they are modified, to ensure that the calling function's state is preserved and to
avoid unexpected behavior. Additionally, if the number of parameters passed in registers
exceeds the number of available registers, parameters can also be passed on the stack.