Briefly Note Microprocessor 8086

Contents
Contents...........................................................................................................................1
7.1 Memory locations:..............................................................................................2
7.1 I/O Ports:............................................................................................................3
2. Architecture Type......................................................................................................3
3. Architecture and Features of 8086............................................................................3
7.1 Features 8086....................................................................................................3
4. General-Purpose Registers & Special-Purpose Registers........................................4
7.1 General-Purpose (Multipurpose) Registers:......................................................4
7.1 Special-Purpose Registers:...............................................................................4
5. Functional Units of 8086...........................................................................................4
7.1 Execution Unit (EU)........................................................................................... 4
7.1 Bus Interface Unit (BIU).....................................................................................5
6. Memory Addressing..................................................................................................6
7. Instructions Set......................................................................................................... 7
7.1 Data Transfer Instructions: (MOV, PUSH, PUSHF, POP, POPF)......................7
8. Generating a Memory Address.................................................................................9
7.1 Memory and I/O Ports Locations:....................................................................10
7.1 Memory Types and Simple Interfacing............................................................10
9. 8086........................................................................................................................ 11

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 Briefly Note Microprocessor 8086
1. General Diagram of Microcomputer and CPU
Block diagram of any computer system:

Block diagram of any processor:

1.1 Memory locations:

Memory locations are actually 8-bits in width. So whenever 16-bit data is accessed two
consecutive 8-bit memory location. Using concept of Little- Endian format.

 Little-Endian format: The least significant byte is always stored in the lowest-
numbered memory location, and the most significant byte is stored in the highest.

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 Briefly Note Microprocessor 8086
1.2 I/O Ports:
Like Memory, I/O ports are actually 8-bits in width. So whenever 16-bit port is accessed
two consecutive 8-bit ports are actually addressed.

2. Architecture Type
 In Von Neumann architecture, programs and data are stored in the same memory
and managed by the same information-handling subsystem.
 In Harvard architecture, programs and data are stored and handled by different
subsystems.

3. Architecture and Features of 8086

3.1 Features 8086

 Data Bus (Size): (16-bit Internal/External) Microprocessor.
 Address Bus: 20-bit.
 Memory: access to 1 MByte of memory.

General laws:
Memory Space (Size) = (2^Address Bus) [unit of memory location width
(capacity)] Memory Capacity = Memory Space * Memory Location Capacity
[bit]
= (2^Address Bus) * Memory Location Capacity [bit]
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 Briefly Note Microprocessor 8086
 I/O: can access (2^16 = 64K) I/O’s.
 Pipelining: supports pipelined architecture, it uses 2 stages of pipelining Fetch
Stage and Execute Stage
 Pipelining means fetching the next instruction while the current is executed
 Fetch Stage can prefetch up to 6 bytes of instructions and store them in the
queue (cache)

4. General-Purpose Registers & Special-Purpose Registers

4.1 General-Purpose (Multipurpose) Registers:
Include AX, BX, CX, DX, BP, DI, and SI. These registers hold various data sizes (bytes
or words) and are used for almost any purpose, as dictated by a program. For some
instructions maybe, a multipurpose register has a special purpose but is generally
considered to be a multipurpose register.
4.2 Special-Purpose Registers:
Include IP, SP, and FLAGS, and the segment registers include CS, DS, SS, and ES.
These registers are used for a certain purpose only.

5. Functional Units of 8086

8086 Microprocessor is divided into 2 functional units
 Execution Unit (EU)
 Bus Interface Unit (BIU)
5.1 Execution Unit (EU)
function and control operations on data using the instruction decoder and ALU. It gives
instructions to BIU stating from where to fetch the data and then decode and execute
those instructions.

 ALU: handles all arithmetic and logic operations.

 General purpose registers (Ax, Bx, Cx, Dx): Each register is 16-bit and consists
of 2 8-bit register like (AH, Al).
 AX (Accumulator register): used with I/O and arithmetic operations.
 BX (Base Index register): sometimes holds the offset address of a location in the
memory.
 CX (Counter register): holds the count for various instructions.
 DX (Data register): holds a part of data used in I/O and some arithmetic (DIV &
MUl) operations.
 SP (Stack Pointer register): point to the top of the stack.
 BP (Base Pointer register): point to somewhere in the stack.
 SI (Source Index register): used in addressing.
 DI (Destination Index register): used in addressing.
 Flag Register (9 Flags): indicate the condition control operation.
 Conditional Flags: changes status according to the result of the last
arithmetic or logical instruction executed.
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 Briefly Note Microprocessor 8086
o CF (Carry flag)
o AF (Auxiliary flag): (half-carry) carry given by D3 to D4 is AF flag.
o ZF (Zero flag)
o SF (Sign flag)
o PF (Parity flag): when the lowest 8-bit contains even number of 1’s the flag
is set. else the flag is reset.
o OF (Overflow flag): system capacity is exceeded.
 Control Flags:
o IF (Interrupt flag): interrupt enable/disable flag.
o TF (Trap flag): used for single step control allows to execute one instruction
at time for debugging.
o DF (Direction Flag): used in string operation. When it is set the string bytes
are accessed from the higher memory address to the lower and vice-a-versa.
(selects either the increment or decrement mode for the DI and/or SI
registers during string instructions)
5.2 Bus Interface Unit (BIU)

It takes care of all data and address transfers on buses for EU like
writing/reading data, fetching instructions and sending address.
 Instructions Queue (Cache): store up to 6 bytes of prefetched next instructions.
 IP (Instruction Pointer register): point to the next instruction in a section of
memory defined as a code segment. That will be fetched to be executed by the
EU.
 Segment registers (CS, DS, SS, ES): used by the microprocessor to access
memory locations. [Note: our registers are 16-bit, but the address bus is 20- bit,
so we have used segmentations]
o CS (Code Segment): for memory locations where the executable program is
stored. Works with [IP].
o DS (Data Segment): for memory locations that deal with data. Works with
[BX, SI, DI].
o SS (Stack Segment): for memory locations that related to the stack. Works
with [SP, BP].
o ES (Extra Segment): for memory locations that deals with extra destination
data (Arrays, Strings). Works with [SI, DI].
Calculating the absolute (actual) address:
Physical address = [Segment address] x 10h + Offset address
0110 1000 1000 0111 0000 Segment, 16 bits, shifted 4 bits left, (or multiplied by10H)
+ 1011 0100 1010 1001 Offset, 16 bits

0111 0011 1101 0001 1001 Address, 20 bits

6. Memory Addressing
 To access the content of a memory location having its address we write the
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 Briefly Note Microprocessor 8086
instruction operand like that: [address]
 The address can only consist of any combination from (BX, BP, SI, DI, or a direct
displacement 8-bit/16-bit)
Note:
o we can’t use (BX) and (BP) together.
o we can’t use (SI) and (DI) together.
o memory location is 8-bit so when we store or read a 16-bit data it uses two
sequential locations the first for the lowest 8-bit and the second for the highest 8-
bit.

o Direct Addressing Mode

[displacement] like [1111H]
o Register Indirect Addressing Mode
[BX] or [BP] or [SI] or [DI]
o Based Addressing Mode
[BX | BP + displacement 8-bit |16-bit] like [BX + 082H]
o Indexed Addressing Mode
[SI | DI + displacement 8-bit | 16-bit] like [BX + 0082H]
o Base-Indexed Addressing Mode
[BX | BP + SI | DI]
o Base-Indexed with Displacement Addressing Mode
[BX | BP + SI | DI + displacement 8-bit | 16-bit] like [BX + SI + 04H]
 Notes:
 “Memory” word refers to: [address]
 “REG” word refers to: (AX, AL, AH), (BX, BL, BH), (CX, CL, CH), (DX, DL, DH),
SI, DI, SP, BP
 “SREG” word refer to: CS (read only), DS, SS, ES
 “immediate” word refers to an immediate data: 1111H

7. Instructions Set
The 8086 microprocessor supports 8 types of instructions −

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 Briefly Note Microprocessor 8086
 Data Transfer Instructions
 Arithmetic Instructions
 Bit Manipulation Instructions
 String Instructions
 Program Execution Transfer Instructions (Branch & Loop Instructions)
 Processor Control Instructions
 Iteration Control Instructions
 Interrupt Instructions

7.1 Data Transfer Instructions: (MOV, PUSH, PUSHF, POP, POPF)

o MOV operand1, operand2

operand1 = operand2
Flags unchanged (C, Z, S, O, P, A)

Operand1, Operand2
REG, memory
SREG, memory
memory, REG
memory, SREG
REG, REG
REG, SREG
SREG, REG
memory, immediate
REG, immediate
o PUSH operand1
SP = SP – 2, SS:[SP] = operand (Push 16-bit into stack)

o POP operand1
operand = SS:[SP], SP = SP + 2 (Pop 16-bit from stack)

Operand1:
REG
SREG
Memory

o PUSHF NO Operand
Push the flag register to stack

o POPF NO operand
Pop the flag register from stack
7.2 Arithmetic Instructions: (ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV)

o ADD operand1, operand2

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 Briefly Note Microprocessor 8086
operand1 = operand1 + operand2

o ADC operand1, operand2

operand1 = operand1 + operand2 + CF

o SUB operand1, operand2

operand1 = operand1 - operand2

o SBB operand1, operand2

operand1 = operand1 - operand2 - CF

o INC operand1
operand1 = operand1 + 1

o DEC operand1
operand1 = operand1 – 1

Conditional Flags changed (Z, S, O, P, A), and Flag (C) unchanged,

Operand1:
REG
memory

o MUL operand1 (Unsigned Multiply)

If operand1 refers to 8-bit ~ AX = AL * operand1
If operand1 refers to 16-bit ~ (DXAX) = AX * operand1

Conditional Flags changed (C, O) CF=OF=0 if the high section of result is zero. and the
Flags (Z, S, P, A) unchanged.

Operand1:
REG
memory

o DIV operand1 (Unsigned Divide)

If operand1 refers to 8-bit ~ AL = AX / operand1, and AH = reminder
If operand1 refers to 16-bit ~ AX = (DXAX) / operand1, and DX = reminder

Conditional Flags unchanged (C, Z, S, O, P, A)

Operand:
REG
memory
7.3 Execution Transfer Instructions: (CMP, JMP, LOOP, CALL, RET)
CMP operand1, operand2
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 Briefly Note Microprocessor 8086
operand1 - operand2 (update flags only) Conditional Flags changed (C, Z, S, O, P, A)

Operand1, Operand2:
REG, memory
memory, REG
REG, REG
REG, immediate
memory, immediate

JMP operand1
jump to label/address(operand1) (Unconditional Jump)

Flags unchanged (C, Z, S, O, P, A)

Operand1 is:
Label, immediate 4-byte address segment:offset

JFlag/JCondition operand1

Flags unchanged (C, Z, S, O, P, A)

Operand1 is:
Label, immediate 4-byte address segment:offset (conditional Jump)

like: (JZ (jump if ZF=1), JNZ (jump if ZF=0))

CALL operand1 ~ Push IP into stack then transfer to the called address If it's a far call,
then code segment is pushed to stack as well. Operand1 may be:
label
immediate 4-byte address segment:offset
procedure name

RET No operand ~ Pop IP from stack and use to return for caller

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 Briefly Note Microprocessor 8086
The essential difference between these two architectures:
Von-Neumann Architecture Harvard Architecture
This model not a modern one This model used with modern computer

Same memory addresses are used for Separate memory addresses are used for
both data and instructions data and instructions.
When execute one instruction, required One clock cycle is enough for executing
at least two clock cycles one instruction
Cost is less to create this model Costly than Von Neumann model
CPU cannot access instructions and CPU can access instructions and
read/write data at same time read/write data at same time
This model mostly uses in signal
This model most suitable for small
processing and microcontrollers;
computers and personal computers
however, used with specific applications.

(DF, IF and TF) into (bit9-bit11) provide an control signal. Flag register exposed in figure
below:

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 Briefly Note Microprocessor 8086

8. Generating a Memory Address

In Intel literature concerning of 8086, there are three types of addresses mentioned
frequently: the physical address (actual address), offset address, and logical
address.

 The physical address is a 20-Bit address that is actually put on (address pins) of
microprocessor.
 The offset address is a location within a 64K Byte segment range.
 The logical address consists of a segment value and an offset address i.e., CS:IP.

The physical address used to access memory a 20 Bits length. To generator a

physical address involves a 16-Bit offset address and combining with 16-Bit of segment
register of (DS, ES, CS and SS, that can be calculated using the follow equation:

The value of segment register is shifted left by four-bit positions, with its LSBs filled with
zeros. This gives a segment address. Then added a 0000 into LSBs to shift value. The
outcome of this addition is 20-Bit, as demonstrated in figure below:

The address can be only consisting of any combination from (BX, BP, SI, DI).
Therefore, 8086 has a segment register and offset register combination as illustrations
in table below:
Segment Reg. Offset Reg.
CS IP
SS SB, BP

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 Briefly Note Microprocessor 8086
DS SI, DI, BX
ES DI, SI, BX

8.1 Memory and I/O Ports Locations:

Memory locations: are actually 8-Bits in width (memory cell). So, whenever 16-Bit data
is accessed two consecutives of 8-Bit memory location. 8086 used a concept of Little-
Endian format.

I/O Ports: Like Memory access, the I/O ports are actually 8-Bits in width. So, whenever
16-Bit port is accessed two consecutives of 8-Bit ports are actually addressed to certain
port.

Little-Endian format: The least significant byte is always stored in the lowest-
numbered memory location, and the most significant byte is stored in the highest.

Big-endian format: keeps the most significant byte of a word at the smallest memory
location and the least significant byte at the largest.
8.2 Memory Types and Simple Interfacing
There are two basic operations inside memory unit which are READ (R) or WRITE (W).
During READ operation, the data is retrieved from memory. While, in WRITE operation
a new data is saved into memory, there are two types of memory:

RAM ROM
Random Access Memory Random Only Memory
Volatile Non-Volatile

SRAM DRAM ROM PROM EPROM EEPROM UVEPROM

Programable Erasable Electrical Ultra-Violet
Static RAM Dynamic RAM
ROM PROM EPROM EPROM
fabricated fabricated
using using
Latches Capacitors
Don’t need Need
Refreshment Refreshment
Circuit Circuit

The address space is physically connected to a 16-Bit data bus by dividing the address
space into two 8-Bit banks 512K Byte of each, to configure a 1M Byte.
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 Briefly Note Microprocessor 8086
Even Bank: is connected to the lower half of the 16-Bit data bus (D0 – D7) and contains
even address bytes. when A0 bit is low, the bank is selected.

Odd Bank: is connected to the upper half of the 16-Bit data bus (D8 – D15) and
contains odd address bytes. when BHE (Byte High Enable) is low, the bank is selected.

The 8086 Data can be accessed from the memory in four different ways. They are:

 8-Bit data from Lower (Even) address Bank.

 8-Bit data from Higher (Odd) address Bank.
 16-Bit data starting from Even Address.
 16-Bit data starting from Odd Address.

9. 8086

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