Course Code: 20ITPC303

Course Name: Computer Organization and Architecture

Unit – I
 K–
S.No Questions Level
CO CAT

1. List the functional units present in a computer? K1 CO1 1

2. Define Computer architecture K1 CO1 1

3. Define Memory Unit. K1 CO1 1

4. State Response time and Throughput. K1 CO1 1

5. Define multiprocessing. K1 CO1 1

6. What is instruction register? K1 CO1 1

7. What is program counter? K1 CO1 1

8. What is processor time? K1 CO1 1

9. What are clock and clock cycles? K1 CO1 1

10. What are the addressing modes and its various types? K1 CO1 1

11. List out the methods used to improve system performance? K1 CO1 1

12. What are the instructions set available in MIPS architecture? K1 CO1 1

13. Define Little Endian arrangement. K1 CO1 1

14. How to represent instruction in a Computer System? K1 CO1 1

State the need for immediate addressing mode. Give an K1 1

15. example. CO1

16. Give the MIPS code for the statement f=(g+h)-(i+j). K1 CO1 1

Write the components of a computer system and list their K2 1

17. functions. CO1

Classify the instructions based on the operations they K2 1

perform and give one example
18. to each category. CO1

19. How CPU execution time for a program is calculated? K1 CO1 1

20. Define register mode and immediate addressing. K1 CO1 1

 Unit 1- / Part - B / 13 Marks
Marks K–
S.No Questions Splitup Level
CO CAT

Explain the important measure of the performance of a computer 7 K2 1

and derive the basic
performance equation. 6
Explain various instruction formats and illustrate the same with
an example.
1. CO1

Explain various instruction formats and illustrate the same with 7 K2 1

2. an example. 6 CO1

Explain the various addressing modes with suitable examples. 13 K2 1

3. CO1

Explain the components of a computer with the block diagram in K2 1

detail
(i) Explain in detail the various components of computer system 7
with neat diagram. 6
(ii) State the CPU performance equation and discuss the factors
that affect performance
4. CO1

What do you mean by addressing modes? Explain various K2 1

addressing modes in aMIPS with the
5 help of examples. CO1

13 K2 1
Explain Performance with an example
6. CO1

13 K1 1
Our favorite program runs in 10 seconds on computer A, which has a 2
GHz clock. We are trying to help a computer designer build a computer,
B, which will run this program in 6 seconds. The designer has
determined that a substantial increase in the clock rate is possible, but
this increase will affect the rest of the CPU design, causing computer B
to require 1.2 times as many clock cycles as computer A for this
program. What clock rate should we tell the designer to target?

7. CO1

Computer A runs a program in 12 seconds with a 3 GHz clock. 13 K2 1

We have to design a computer B such that it can run the same
program within 9 seconds. Determine the clock rate for computer
B. Assume that due to an increase in clock cycle rate , CPU
design of computer b is affected and it requires 1.2 times as many
clock cycles as computer A for execution of this program.
8. CO1
 Unit - I / Part - C / 15 Marks
Marks K–
S.No Questions Splitup Level
CO CAT

The table shows the two code sequences with a number of instructions 15 k2 1
of different instruction classes within each code sequence respectively.
The instruction are classified as A,B and C according to the CPI as
shown in table

Determine which code sequence executes the most instructions.

(ii) Determine which code sequence will execute quickly.
(iii) Determine the CPI for each code sequence

1. CO1

Explain how instruction that involve decision making are executed with 15 K2 1
2. an example? CO1

05 K2 1
a)i)Translate the following C code to MIPs assembly code. Use a
minimum number
of instructions. Assume that I and k correspond to registers $s3 and
$s5 and the
base of the array save is in $s6. What is the MIPS assembly code
corresponding
to this c Segment?
While(save[i] = = K)
i+ =1;
(April-2018)
ii)Assume that the variables f and g are assigned to the registers $s0
and $s1 respectively.Assume that the base address of the array A is in
register $s2.Assume fi zero initially
f=g-A[4];
A[5]=f+100;
Translate the above statements into MIPS code.How many MIPS 05
assembly instructions are needed to perform the C statements and how
many registers are needed to carry out the above C statements

b)Consider the following C code segment:

a=b+e; 05
c=b+f;
Translate the above statements into MIPS code.How many MIPS
assembly instructions are needed to perform the C statements
3. CO1
 Unit – II

S.No Questions K – Level CO CAT

Find the value of x-y where x=0000 1011 1110 1111 and y= 1111 0010 1001 K1 2
1. 1101 using 2’s complement method. 2

Find the value of (11010)2–(10000)2 using 1’s complement and 2’s K1 2 2

2. complement method.

3. List the Overflow condition for addition and subtraction. K1 2 2

K2 2 2
4. Outline the Logic diagram of the half adder .

5. Find the value of 100011 * 100010 . K1 2 2

6. Show how to Recode the multiplier 101100 for Booth’s multiplication . K1 2 2

7. Define modified Booth's algorithm. K1 2 2

8. Find the bit pair code for multiplier 11010 . K1 2 2

9. What is restoring division algorithm ? K1 2 3

K2 2 3
Infer the result of Adding the numbers (0.5)10 and (0.4375)10 using the
floating point addition.
10.

11. Summarize the steps in the non-restoring division algorithm. K2 2 3

12. Show the number (1259.125)10 in single precision format. K1 2 3

13. Infer the result of Dividing the numbers (1001010)2 by (1000)2 . K2 2 3

14. Outline the IEEE standard floating -point formats. K2 2 3

15. What is sub-word parallelism ? K1 2 3

Unit - II / Part - B / 13 Marks

Marks
K–
S.No Questions Splitu
Level
CO CAT
p

(i) Interpret the result of subtracting the numbers (28)10 –

(15)10 using 6 bit 1’s complement method. 7
(ii) Interpret the result of subtracting numbers (28)10 and 2 2 2
(15)10 using 6 bit 2’s complement representation. 6
1.
 (i) Interpret the result of multiplying the following pair of
signed 2’s complement numbers using Booth’s algorithm, 7
A=(-13)10=(110011)2 and B=(-20)10 = (101100)2 where A is
multiplicand and B is multiplier.
2 2 2
(ii) Interpret the result of multiplying the following 6
numbers using bit pair recoding
A=01111 multiplicand (15) and
2. B= 10110 multiplier (-10)

Explain in detail Carry-Look ahead Addition with a neat

13 2 2 2
3. diagram .

4. Describe in detail the Booth algorithm with an example . 13 2 2 2

Discuss in detail the sequential version of the multiplication

algorithm and hardware with a neat diagram. 13 2 2 2
5.

Discuss in detail the logic circuit which performs addition of

13 2 2 2
6. numbers with a neat diagram.

Interpret the result of addition and subtraction of single

precision floating point numbers A and B where 13 2 2 3
7. A=44900000H and B=42A00000H.

Describe in detail Arithmetic Operations on Floating-Point

13 2 2 3
8. Numbers Rules .

Describe in detail the restoring division algorithm with an

13 2 2 3
9. example .

Discuss in detail Floating-Point Representation with an

13 2 2 3
10. example.

(i) Show the number (309.1875)10 in single precision and

double precision format. 7
2 2 3
(ii) Show the numbers 32.75 and 18.125 in single precision
11. IEEE 754 format. 6

(i) Interpret the result of dividing the following unsigned

numbers using the restoring division method where 7
dividend = 1010 and Divisor= 00011 . 2 2 3
(ii) What is meant by subword parallelism?. Formulate an 6
12. example.
 Unit -II / Part - C / 15 Marks
Marks
K–
S.No Questions Split
Level
CO CAT
Up

(i) Interpret the result of subtracting the binary numbers 8

(11011)2 – (10011)2 using 2’s complement.
(ii) Interpret the result of subtracting numbers (15)10 and 7 2 2 2
(28)10 using 6 bit 2’s complement representation.
1.

(i) Interpret the result of multiplying the following signed 8

numbers using Booth’s algorithm, A=(-34)10=(1011110)2
and B=(22)10 = (0010110)2 where B is multiplicand and A is
multiplier.
2 2 2
(ii) Interpret the result of multiplying signed 2’s 7
complement numbers using bit pair recoding
A=110101 multiplicand (-11)
2. B= 011011 multiplier (+27)

(i) Show the IEEE 754 binary representation of the number 8

(-0.75)10 in single and double precision.
2 2 3
(ii) Show the number (-307.1875)10 in single precision and 7
3. in double precision formats.

(i) Interpret the result of dividing the following unsigned 8

numbers using the restoring division method where
2 2 3
dividend = 1000 and Divisor= 00011 .
4. (ii) Discuss about sub word parallelism. 7

Unit - III
 Unit - III/ Part - A / 2 Marks
Marks,
S.No Questions K - Level,CO

1. Define hazard. Give an example for data hazard K1, CO3

2. State the two steps that are common to implement any type of instruction. K1, CO3

3. Name the R-type instructions K1, CO3

Draw the diagram of portion of data path used for fetching instruction and
4. incrementing the PC K1, CO3

5. Classify the different types of hazards with examples. K1, CO3

6. Show the 5 stages pipelin K1, CO3

7. What is pipelining? K1, CO3

8. What is exception. Give one example for MIPS exception. K1, CO3

9. Point out the concept of exceptions and interrupts. K1, CO3

10. What are the control signals required to perform arithmetic operations? K1, CO3

11. Illustrate the various phases in executing an instruction K1, CO3

K1, CO3
12. Differentiate static and dynamic prediction.

13. What is the need of an instruction buffer in a pipelined CPU? K1, CO3

14. What is a datapath element? K1, CO3

15. Difference between when the control signal is asserted and deasserted K1, CO3

16. Draw the format for R-Type ,I type and J-Type Instruction. K1, CO3

17 Illustrate data forwarding method to avoid data hazards. K1, CO3

 Unit - III / Part - B / 13 Marks
Marks,
S.No Questions K - Level,CO

Discuss the basic concepts of pipelining? 13, K2,

1. CO3

13,K2,
2. Explain the concept of pipelined data path and control in detail. CO3

13, K2,
3. Explain data hazards and how to overcome it. CO3

10, K2,
4. Explain dynamic branch prediction? CO3

What are R-Type instructions? Draw and explain the functional block 13, K2,
5. diagram with control signals for basic implementation of MIPS subset. CO3

State and draw a simple MIPS datapath with control unit and explain the 13,K2,CO
6 execution of ALU instruction. 3

Design and develop an instruction pipeline working under various situations 13,K2,CO
7 of pipeline stall 3

Unit - III / Part - C / 15 Marks

Marks,
S.No Questions K - Level,CO

Draw and explain the functional block diagram with control signals for basic 15, K2,
1. implementation of MIPS subset. CO3

Explain the control implementation scheme. 15, K2,

2. CO3

Explain the operation of the data path for an R-type, Load Word, branch, 15, K2,
3. jump instructions in detail CO3

Plan the pipelining in MIPS architecture and generate the exceptions handled 15, K2,
4. in MIPS. CO3
 Unit - IV

Unit - IV/ Part - A / 2 Marks

Marks,
S.No Questions K - Level,CO

1. Define Parallelism and its types K1, CO4

2. Define Multiprocessor K1, CO5

3. Define a cluster and list its applications K1, CO5

4. Define Multicore Multiprocessors and shared memory multiprocessor K1, CO5

5. Differentiate strong scaling and weak scaling K1, CO4

6. Define multiple issue K1, CO4

7. Define the terms SISD, MIMD with examples K1, CO4

8. What is data level parallelism? K1, CO4

9. Why Graphics processing unit are needed? K1, CO5

10. Define multicore multiprocessors. K1, CO5

11. What do you mean by warehouse scale processors? K1, CO5

K1, CO4
12. Compare SMT and hardware multithreading.

13. Define fine grained multithreading. K1, CO4

14. What is the need for instruction level parallelism K1, CO4

15. List out the various multithreading options K1, CO4

What are the various approaches to hardware multithreading?

16. K1, CO4

17 Discriminate UMA and NUMA K1, CO4

18 What is message passing? K1, CO5

19 Name the interconnections used in multiprocessor system. K1, CO5

20 What is meant by hardware multithreading K1, CO4

21 List the benefits of clustering in computer architecture K1, CO5

 Unit - IV / Part - B / 13 Marks
Marks,
S.No Questions K - Level,CO

Describe the main characteristics and limitations of instruction level

1. parallelism 8, K2, CO4

2. Differentiate static and dynamic multiple issues 8, K2, CO4

3. Describe the properties of vector architectures over scalar architectures. 8, K2, CO4

10, K2,
4. Discuss the characteristics of SMT processors CO4

13, K2,
5. Explain in detail about hardware multithreading CO4

Explain how Graphics processing units help improve processor 13, K2,
6. performance CO5

13, K2,
7. Describe data level parallelism in SIMD and MISD CO4

Explain the classification of shared memory multiprocessor based on

8. memory access latency 8, K2, CO5

Compare and contrast fine grained and coarse grained multithreading

9. and simultaneous multithreading 8, K2, CO4

13, K2,
10. Describe the features of multicore processors CO5

13, K2,
11. Describe the types of multithreading and its advantages CO4

13, K2,
12. Describe in detail the following SISD and MIMD CO4

13, K2,
13 Explain simultaneous multithreading with example CO4

Describe the four principle approaches to multithreading with necessary 13, K2,
14 diagrams CO4

15 Explain clusters in detail 8, K2, CO5

16 Describe the working of warehouse scale computers in detail 8, K2, CO5

Summarize the challenges encountered in implementing parallel

17 processing 8, K2, CO4

18 State the advantages of multiprocessor systems 6,K1, CO5

 Unit - IV / Part - C / 15 Marks
Marks,
S.No Questions K - Level,CO

Summarize the merits and demerits of clusters and warehouse scale 15, K1,
1. computers CO5

Suppose you want to achieve a speed up of 90 times faster with 100

processors. What percentage of the original computation can be
2. sequential? 8, K2, CO4

Suppose you want to perform two sums: one is a sum of 10 scalar

variables and one is a matrix sum of a pair of two-dimensional arrays,
with dimensions 10 by 10. Assume only the matrix sum is parallelizable;
What speed up do you get with 10 versus 40 processors? Calculate the 15, K2,
3. speed up assuming the matrices grow to 20 by 20. CO4

Unit - V

Unit - V/ Part - A / 2 Marks

S.No Questions Marks,

K - Level,
CO

1. Define memory access time? K1, CO6

2. Define memory cycle time. K1, CO6

3. Define Static Memories. K1, CO6

4. Distinguish Between Static RAM and Dynamic RAM? K1, CO6

5. Distinguish between asynchronous DRAM and synchronous RAM. K1, CO6

6. What are the various units in the computer? K1, CO6

7. When is a memory unit called RAM? K1, CO6

8. What is MMU? K1, CO6

9. Define Memory Latency? K1, CO6

10. What are asynchronous DRAMs? K1, CO6

11. What are synchronous DRAMs? K1, CO6

12. What is a memory Controller? K1, CO6

13. Define memory cycle time. K1, CO6

14. Define L1 cache? K1, CO6

15. Define memory interleaving. K1, CO6

16. Define Hit and Miss? K1, CO6

17 What is cache memory? K1, CO6

18 What is message-passing? K1, CO6

19 What is a memory system? K1, CO6

20 Define memory access time. K1, CO6

21 Define memory cycle time. K1, CO6

22 What are the types of ROM? K1, CO6

23 What is interrupt? K1, CO6

24 What is program controlled I/O? K1, CO6

25 How do you construct a 8M x 32 memory using 512 k x 8 memory K1, CO6

chips?

26 What is virtual memory? K1, CO6

27 What is TLB (Translation Look – aside Buffer) K1, CO6

28 What is the function of a TLB (Translation Look – aside Buffer) K1, CO6

29 An address space is specified by 24-bits and the corresponding memory K1, CO6
space by 16-bits: How many word are there in the a) Virtual memory b)
Main memory

30 What is the necessity of an interface? Or what are the functions of a K1, CO6
typical I/O interface?

31 What are the components of an I/O interface? K1, CO6

32 How does the processor handle interrupt requests? K1, CO6

33 What is a non – mask able interrupt? What is the action performed on K1, CO6
receipt of a NMI?

34 How does the processor handle an interrupt request? K1, CO6

35 What is meant by bus arbitration? K1, CO6

36 What is DMA or what is DMA operation? State its advantages or Why do we K1, CO6
need DMA.
37 What are the three types of channels usually in large computers? K1, CO6

38 What are the necessary operations needed to start an I/O operation using K1, CO6
DMA?

39 What are tri – state gates? K1, CO6

40 State the advantages of virtual memory K1, CO6

Unit - V / Part - B / 13 Marks

Marks, K-
S.No Questions Level,CO

1. Explain in detail about memory Technologies 8, K2, CO6

2. Expain in detail about memory Hierarchy with neat diagram 8, K2, CO6

3. Discuss the various mapping schemes memory. 8, K2, CO6

4. Discuss the methods used to measure and improve the performance of the cache 10, K2, CO6

5. Explain cache memory in detail 13, K2, CO6

6. Explain about mapping fractions. 13, K2, CO6

7. Give one example for mapping technique. 13, K2, CO6

8. Discuss the various mapping schemes used in cache design 8, K2, CO6

9. Explain about interrupts 8, K2, CO6

10. Explain about virtual memory 13, K2, CO6

11. Explain DMA in detail with neat diagram 13, K2, CO6

12. Write short notes on Translation look-aside buffers (TLB). 13, K2, CO6

13 How do you access I/O devices? Explain with a diagram? 13, K2, CO6
 Unit - V / Part - C / 15 Marks

Marks,
S.No Questions K - Level,CO

Consider a cache with the following design parameters.Main memory address

length [word
addressed] = 21bits. Tag field length = 9 bits
Index field length = 8bits Total cache size = 32 k words
Main memory access time for one word = 70ns
a. What are N,K and L?
b. How many different lines in main memory can map to the K slots in set
# 1? 15, K1,
1. c. How many tag comparators are required for this cache? CO6

Consider a 64K direct mapped cache with a 16 byte block size. Show how a
2. 32 bit address is partitioned to access the cache 8, K2, CO6

A block set associative cache consists of a total of 64 blocks divided into

four block sets. The main memory contains 4096 blocks, each consisting
of 128 words.
a. A. How many bits are there in a main memory address?
b. B. How many bits are there in each of the TAG, SET and WORD fields?
c. C. What is the size of cache memory? 15, K2,
3. CO6

The application program in a computer system with cache uses 1400

instruction acquisition bus cycles from cache memory and 100 from main
memory. What is the hit rate? If the cache memory operates with zero
wait state and the main memory bus cycles use three wait states. What is
the average number of wait states experienced during the program 15, K2,
4. execution? CO6

Course Outcomes
CO1 Describe the physical, logical and functional aspects of Computer System- K2

CO2 Demonstrate the basic fixed point and floating point operations (addition, subtraction, K2
multiplication and Division) carried out by the processor.
CO3 Explain the significance and hazards associated with the pipelined data path and control K2
unit of computer system
CO4 Express the significance of the parallel processing architectures K2

CO5 Discuss the various multicore architectures and multiprocessor architectures K2

CO6 Elucidate the significance of Memory and I/O hierarchy. K2

 Distribution of COs (Percentage wise)

CO No. CO1 CO2 CO3 CO4 CO5 CO6

% 15 15 15 15 19 21

Course Moderator: Mrs.Shiny.A/SEC