Mansoura University

Faculty of engineering

Electrical Power and Machines Engineering

department

555 timer IC

3rd Electrical power and machines Engineering department

Prepared By : Ahmed Mohamed Eldasoki hassan

Section :: 2

Under supervision of / Dr / Ahmed Eid

Spring 2023
1. Introduction
The 555 timer IC is an integrated circuit
(chip) used in a variety of timer, delay, pulse
generation, and oscillator applications.
Derivatives provide two (556) or four (558)
timing circuits in one package.
The design was first marketed in 1972 by
Signetics and used bipolar junction transistors.
Since then, numerous companies have made the original timers and later
similar low-power CMOS timers. In 2017, it was said that over a billion 555
timers are produced annually by some estimates, and that the design was
"probably the most popular integrated circuit ever made".

2. History
The timer IC was designed in 1971 by Hans
Camenzind under contract to Signetics. In
1968, he was hired by Signetics to develop a
phase-locked loop (PLL) IC. He designed an
oscillator for PLLs such that the frequency did
not depend on the power supply voltage or temperature. Signetics
subsequently laid off half of its employees due to the 1970 recession, and
development on the PLL was thus frozen.
Camenzind proposed the development of a universal circuit based on the
oscillator for PLLs and asked that he develop it alone, borrowing equipment
from Signetics instead of having his pay cut in half.
Camenzind's idea was originally rejected, since other engineers argued the
product could be built from existing parts sold by the company; however, the
marketing manager approved the idea.

The first design for the 555 was reviewed in the summer of 1971. After this
design was tested and found to be without errors, Camenzind got the idea of
using a direct resistance instead of a constant current source, finding that it
worked satisfactorily.

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 The design change decreased the required 9 external pins
to 8, so the IC could be fit in an 8-pin package instead of
a 14-pin package.
This revised version passed a second design review,
and the prototypes were completed in October 1971 as
the NE555V (plastic DIP) and SE555T (metal TO-5).[9]
The 9-pin version had already been released by
another company founded by an engineer who had
attended the first review and had retired from Signetics; that
firm withdrew its version soon after the 555 was released. The 555 timer
was manufactured by 12 companies in 1972, and it became a best-selling
product.

The 555 found many applications beyond timers. Camenzind noted in 1997
that "nine out of 10 of its applications were in areas and ways I had never
contemplated. For months I was inundated by phone calls from engineers
who had new ideas for using the device.

3. Internal schematic

The internal block diagram and schematic of the 555 timer are highlighted with the
same color across all three drawings to clarify how the chip is implemented:

• Voltage divider: Between the positive supply voltage VCC and the ground GND is a voltage
divider consisting of three identical resistors (5 kΩ for bipolar timers, 100 kΩ or higher for
CMOS) to create reference voltages for the analog comparators. CONTROL is connected
between the upper two resistors, allowing an external voltage to control the reference
voltages:
o When CONTROL is not driven, this divider creates an upper reference voltage
of 2⁄3 VCC and a lower reference voltage of 1⁄3 VCC.
o When CONTROL is driven, the upper reference voltage will instead be
VCONTROL and the lower reference voltage will be 1⁄2 VCONTROL.
• Threshold comparator: The comparator's negative input is connected to voltage divider's
upper reference voltage, and the comparator's positive input is connected to THRESHOLD.
• Trigger comparator: The comparator's positive input is connected to voltage divider's lower
reference, and the comparator's negative input is connected to TRIGGER.
• Latch: A set-reset latch stores the state of the timer and is controlled by the two comparators.
RESET overrides the other two inputs, thus the latch (and therefore the entire timer) can be
reset at any time.

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• Output: The output of the latch is followed by an output stage with push–pull output drivers
that can supply up to 200 mA for bipolar timers, lower for CMOS timers.
• Discharge: Also, the output of the latch controls a transistor acting as an electronic
switch that connects DISCHARGE to ground (convenient for discharging a timing capacitor)
or leaves it disconnected.

555 internal block diagram

555 internal schematic of bipolar version 555 internal schematic of CMOS version

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 4. Modes
The 555 IC has the following operating modes:

1. Astable (free-running) mode – The 555 operates as an electronic oscillator. Applications

include:
o Light emitting diode and lamp flashers, pulse generation, pulse-width
modulation (PWM), logic clocks, tone generation, security alarms, pulse-
position modulation, etc.
o Analog-to-digital conversion (ADC) from an analog value represented by a
resistance or capacitance into a digital pulse length.
 e.g., selecting a thermistor as timing resistor allows the use of
the 555 in a temperature sensor with the period of the output
pulse determined by the temperature. A microprocessor can then
convert the pulse period to temperature, linearize it, and even
provide calibration.
2. Monostable (one-shot) mode – The 555 operates as a "one-shot" pulse generator.
Applications include:
o timers, missing pulse detection, bounce-free switches, touch switches,
frequency dividers, triggered measurement of resistance or capacitance,
PWM, etc.
3. Bistable (latch) mode – The 555 operates as a set-reset latch. Applications include:
o switch debouncing.
4. Schmitt trigger (inverter) mode – the 555 operates as a Schmitt trigger inverter gate.
Application:
o Converts a noisy input into a clean digital output.

Astable
In the astable configuration, the 555 timer puts out a continuous stream
of rectangular pulses having a specific period.
The astable configuration is implemented using two resistors, and one
capacitor .
The threshold and trigger pins are both connected to the capacitor; thus
they have the same voltage.
Its repeated operating cycle (starting with the capacitor uncharged) is:

1. Since the capacitor's voltage will be below 1⁄3 VCC,

the trigger pin causes the 555's internal latch to change state, causing OUT to go high
and the internal discharge transistor to cut-off.
2. Since the discharge pin is no longer short-circuited to ground, the capacitor starts
charging via current from Vcc through the resistors
3. Once the capacitor charge reaches 2⁄3 Vcc, the threshold pin causes the 555's internal
latch to change state, causing OUT to go low and the internal discharge transistor to go
into saturation (maximal-conductivity) mode.
4. This discharge transistor provides a discharge path, so the capacitor starts discharging
through.
5. Once the capacitor's voltage drops below 1⁄3 VCC, the cycle repeats from step 1.
During the first pulse, the capacitor charges from 0 V to 2⁄3 VCC, however, in later pulses, it only charges
from 1⁄3 VCC to 2⁄3 VCC. Consequently, the first pulse has a longer high time interval compared to later

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pulses. Moreover, the capacitor charges through both resistors but only discharges through , thus the
output high interval is longer than the low interval. This is shown in the following equations.

Monostable
Monostable mode produces an output pulse when the
trigger signals drops below 1⁄3 VCC. An RC circuit sets the
output pulse's duration as the time in seconds it takes to
charge C to 2⁄3 VCC:
where is the resistance in ohms, is the capacitance
in farads, is the natural log of 3 constant[b]. The output
pulse duration can be lengthened or shortened as desired
by adjusting the values of R and C. Subsequent
triggering before the end of this timing interval won't
affect the output pulse.
After the timing interval completes, the capacitor is almost instantly discharged through
the Discharge pin, to then allow for subsequent triggering.

Bistable SR latch
A 555 timer can act as an active-low SR latch (though
without an inverted Q output) by connecting a Reset input
signal to the RESET pin and connecting a Set input signal
to the TR pin. Thus, pulling Set momentarily low acts as a
"set" and transitions the output to the high state (VCC).
Conversely, pulling Reset momentarily low acts as a
"reset" and transitions the Out pin to the low state (GND).
No timing capacitors are required in a bistable
configuration. The threshold input is grounded because it is
unused. The discharge pin is left unconnected if unused, or may be used as an open-
collector output. The trigger and reset inputs may be held high via pull-up resistors if they
are normally Hi-Z and only enabled by connecting to ground.

Bistable Schmitt trigger

A 555 timer can be used to create a Schmitt trigger inverter gate,
which converts a noisy input into a clean digital output, by
connecting the input signal to both the trigger and threshold
pins. Thus, when the input exceeds
the 1⁄3 VCC and 2⁄3 VCC switching thresholds, the Schmitt
trigger's binary state will change. The reset, control, and
discharge pins are unused.
Optionally as done in the example schematic, the input may first
be connected through a series capacitor into a resistor
divider to center an AC input signal between VCC and GND.
Then thanks….