CS203: Digital Logic Design

Module 4: Sequential Circuits

Neeraj Goel
IIT Ropar
 Sequential circuits
• Output depends on – present inputs as well as
past inputs
Z = f(At, At-1, At-2...., Bt, Bt-1, Bt-2...., Ct, Ct-1, Ct-2...)

A
Two types:
B Z Finite memory system
Sequential circuit
Infinite memory system
C

Digital System Design 2

 Sequential circuits
• Questions
– Where to store past inputs
– How many inputs to be stored – which one
– How much memory required
• Solution:
– Identifying distinct states
– Their transition conditions
• Also knows as finite state machines

Digital System Design 3

 Synchronous Sequential system
• Synchronized by a clock signal
– Change in states happens synchronously
– Each storage element changes at same time

Digital System Design 4

 Example – sequential circuits
• Assume a serial port (like USB)
– Data as well as control will flow through same
serial link
– Matching patterns – sequence of bits will define if
it is a control word or data
– Sequential decoding

Digital System Design 5

 Building blocks
• Latches
• Flip-flop
– Edge triggered, different types: D, T, JK, RS
• Registers
– Array of memory cell, usually flip-flop
• Counters
• Memory

Digital System Design 6

 Design of basic storage element
• Digital circuit with feedback

T
∆t

X Y
01 10 01

Digital Logic Design:Sequential Circuits.

 Set Reset Latch
X
Y = X’
0
P Q

S
P
`
How to set a particular output?

` Q
01 R
P Q
S
R
10
10 10

Digital Logic Design:Sequential Circuits.

 Set-Reset Latch
R S

• What if R and S are both 1

SR Latch
– Both output would be 0
– Both R and S change to ‘0’ Q’ Q

simultaneously R
Q’
`
• Unstable output
• For valid inputs both the
outputs are complementary to ` Q
S
each

Digital Logic Design:Sequential Circuits.

 State-table SR Latch
R S Q Q+
0 0 Q Q
Next state equation:
0 1 X 1
Q+ = S + R’Q
1 0 X 0
1 1 X Invalid

SR Latch can be created using NAND gates as well

Applications:
-Storage
-Debouncing

Digital Logic Design:Sequential Circuits.

 Gated Latch
R
R S G Q Q+
Q’
`
X x 0 Q Q
0 0 1 Q Q G

0 1 1 X 1
1 0 1 X 0 ` Q
1 1 1 X Invalid S

Next state equation

Q+ = SG + Q(R’ + G’)

Digital Logic Design:Sequential Circuits.

 Gated D Latch

Next state equation `

Q’
Q+ = DG + QG’ G

` Q
D

D Q

D Latch
G Q’

Digital Logic Design:Sequential Circuits.

 D Latch Input example

Ideally there would be propagation delay!

Digital Logic Design:Sequential Circuits.

 Summary
• Latches

Digital Logic Design:Sequential Circuits.

 M4.02
Edge triggered D Flip-flop

Digital Logic Design:Sequential Circuits.

 Latches
• RS latch
– To store certain value reset/set value need to be
high
• D latch
– Store the input for controlled time
• If control input is ‘0’
– When control is ‘1’ they are transparent
• We require storage element that can store
value at precise time

Digital Logic Design:Sequential Circuits.

 Clock signal
• Synchronising signal
• Characteristics
– Time period (T)
– Duty cycle : (Tw/T) x 100
• Time of synchronisation
– Rising edge or falling edge

Tw

T Digital Logic Design:Sequential Circuits.

 Flip-flop
• A memory element that changes output only
during transition of clock signal
• Two possible transitions D Q

– Rising edge (positive edge)

Q’
CLK
– Falling edge (negative edge)
• Type of flip-flops
– D, JK, RS, T

Digital Logic Design:Sequential Circuits.

 D Flip-flop - features

D Q

Q’
CLK

Characteristic equation: Q+ = D

•D is sampled at positive edge of clock

•Value of D will be passed to Q
•Q will not change for one clock duration

Digital System Design 19

 Rising edge triggered D FF

D D Q D Q Q

D Latch D Latch
CLOCK Q’ Q’
G G

Digital Logic Design:Sequential Circuits.

 D-Flip flop - timing
Setup and hold time restrictions

Digital System Design 21

 Summary
• Flip-flop an important fundamental circuit for
synchronization

Digital Logic Design:Sequential Circuits.

M4.03 : Other Flip-flops

Digital Logic Design:Sequential Circuits.

M4.04 Counters

Digital Logic Design:Sequential Circuits.

 Flip-flops
• Type of flip-flop
– SR, D, JK, T FF
• Can we design one flip-flop from another?
• Counters
• Sequence generators

Digital Logic Design:Sequential Circuits.

 Design JK FF from D-FF
J K Q Q+
J
0 0 0 0
Q’
0 0 1 1 D Q
K’
0 1 0 0 Q
0 1 1 0 Q’
CLK
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Q+ = JQ’ + K’Q
Q+ = D (for DFF)
D = JQ’ + K’Q Digital Logic Design:Sequential Circuits.
 Clock divider using DFF
T Flip-flop with T always 1
D Q

Q’
CLK

CLK

Digital Logic Design:Sequential Circuits.

 More clock division

D CLK/8
D CLK/4
D CLK/2
Q’
Q’ CLK/4
Q’ CLK/2
CLK

All clock signals are not synchronized!

Digital Logic Design:Sequential Circuits.

 Counter
0000 1000
Frequency at every bit is half of other
0001 1001 Clock divider circuit can be used counter
0010 1010
0011 1011 Asynchronous counter
0100 1100
0101 1101
0110 1110
0111 1111
Digital Logic Design:Sequential Circuits.
 Synchronous counter
• Clock will not be modified
– One global clock to all FFs
• Next output depends on previous
output/input

Digital Logic Design:Sequential Circuits.

 3 bit synchronous counter
Q2 Q1 Q0 Q2+ Q1+ Q0+
0 0 0 0 0 1 Q0+ = Q0’
Q1+ = Q1’Q0 + Q1 Q0’
0 0 1 0 1 0 Q2+ = Q2’Q1Q0 + Q2 (Q1’ + Q0’)
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0

Digital Logic Design:Sequential Circuits.

 3 Bit counter

D2 Q2 D1 Q1 D0 Q0

Q2’ Q1’ Q0’

CLK CLK CLK

D0 = Q0’
D1 = Q1’Q0 + Q1 Q0’
D2 = Q2’Q1Q0 + Q2 (Q1’ + Q0’)
= Q2  Q1Q0
Digital Logic Design:Sequential Circuits.
 Modulo 6 bit counter
Q2 Q1 Q0 Q2+ Q1+ Q0+
0 0 0 0 0 1 Q0+ = Q0’
Q1+ = Q2Q1’Q0 + Q1 Q0’
0 0 1 0 1 0 Q2+ = Q1Q0 + Q2Q0’
0 1 0 0 1 1
0 1 1 1 0 0 Clock division by 6
1 0 0 1 0 1
1 0 1 0 0 0
1 1 0 x x X
1 1 1 x x X

Digital Logic Design:Sequential Circuits.

 Sequence generator
• Any sequence can be generated
• Steps
– Number of bits in sequence decide the number of
flip-flop
– Next state equations by writing the truth table
– Find Boolean expression for each next state bit
• Example Homework
– 0 -> 2 -> 1 -> 4 -> 6 -> 3 -> 0

Digital Logic Design:Sequential Circuits.

 Summary
• D Flip-flop based design
– Any other flip-flop
– Clock divider
– Counter
– Modulo counters
– Sequence generators

Digital Logic Design:Sequential Circuits.

 M4.05
Registers

Digital Logic Design:Sequential Circuits.

 Registers
• Array of flip-flops
– Used to store data (integers, floats, or bit array)
• Typical characteristics
– Output can change only at active edge of the
clock-cycle
– Common clock (synchronous)
– Value can be stored to register when “load =1”
• Load is also called CE (chip enable)
– Asynch. clear and preset may be there

Digital Logic Design:Sequential Circuits.

 Registers using DFF
Register
Data in

Load Data out

D Q
D FlipFlop
Clock
Q’
Clear CLK

Clear

Digital Logic Design:Sequential Circuits.

 Registers using DFF
Register
Data in

Load Data out

D Q
D FlipFlop
Clock
Q’
Clear CLK

Clear

Digital Logic Design:Sequential Circuits.

 N bit register
Q’N-1 QN-1 Q’1 Q1 Q’0 Q0

D FlipFlop D FlipFlop D FlipFlop

CE CE CE

D CLK D CLK D CLK

DataInN-1 DataIn1 DataIn0

Digital Logic Design:Sequential Circuits.

N-Bit register

4
Q

Clear 4 bit Register

CE D
Load CLK 4

Digital Logic Design:Sequential Circuits.

 Design an adder that adds 16 32-bit
numbers
32 32 32
Q B A

Clear 32 bit Register 32 Bit Adder Cin 0

CE D Sum

Load 32
CLK 32

Clear should be 1 in 0th cycle

Load should be 1 for 16 clock cycles
A module 16 counter can be used

Digital Logic Design:Sequential Circuits.

 Clock cycle considerations
Input Registers

Input

Combinational circuit
Clock

Output Registers
Data path +
Control path

Current state

Tclk >= Tcomb + Tsetup + Treg

 Tutorial question
• Design an adder that can implement
accumulator functionality (Sum = Sum + A) if
acc =1, else it add two numbers A and B and
stores in Sum.
• Assume Sum, A and B are all 32 bit registers.

Digital Logic Design:Sequential Circuits.

 Serial in data
• Serial ports, like USB
– Receive data one bit at a time
• Usually utilized in form of bytes and words
• Two possibilities:
– The least significant bit received first
– The most significant bit received first
• Registers can be used for receiving the data
efficiently
– Store the required number of bits
– Shift them efficiently

Digital Logic Design:Sequential Circuits.

 Serial-in registers
• 4 bit: the least significant bit received first

Din D3 Q3 D2 Q2 D1 Q1 D0 Q0
D D D D Out
FlipFlop FlipFlop FlipFlop FlipFlop
Q’
CLK CLK CLK CLK

CLK

DIN

Q3

Q2

Q1
Q0
 Shift operations: N bit number
• Shift right 01100 11100
0 0110 1
0 1110
– Divide by 2
00110
– Arithmetic shift right 01100
– Logical shift right 11000 Overflow!

• Shift left
– Multiply by 2
Implementation Shift registers

Digital Logic Design:Sequential Circuits.

 4 bit Right Shift register

0 D3 Q3 D2 Q2 D1 Q1 D0 Q0
D D D D
LSR FlipFlop FlipFlop FlipFlop FlipFlop
Q’
CLK CLK CLK CLK
CE CE CE CE
Shift

How about giving Input?

Digital Logic Design:Sequential Circuits.

 4 bit Right Shift register

0 D3 Q3 D2 Q2 D1 Q1 D0 Q0
D3 D D2 D D D0 D
D1
C1 FlipFlop C FlipFlop C FlipFlop C FlipFlop
Q’
CLK CLK CLK CLK
CE CE CE CE
C2

C1 (two bits): C10 = LSR; C11 = Load

C2 (one bit): C2 = Shift + Load
C (one bit): Load

Digital Logic Design:Sequential Circuits.

 Universal shift register
• Iterative circuit
• Each cell
– Can shift left
– Shift right
– Load data
– Retain data
• Boundary cell
– (N-1)th cell : Depends if shift right is ASR or LSR
– 0th cell : shift left value is ‘0’

Digital Logic Design:Sequential Circuits.

ith cell of universal shift register
Boundary cells
Qi+1 CellN-1
Qi-1
Qi Di Qi Qi+1 : 0 if LSR, Qi if ASR
Di D Cell0
C FlipFlop Qi-1 = 0

CLK

Operation C1 C0
Shift right 0 0
Shift left 0 1
Retain 1 0
Load data 1 1

Digital Logic Design:Sequential Circuits.

 Homework problems
• Design of circular shift register
• Design of parallel in – serial out register

Digital Logic Design:Sequential Circuits.

 Summary
• Registers and its application
• Shift registers and its role in communication
and arithmetic

Digital Logic Design:Sequential Circuits.

M4.06: Memories

Digital Logic Design:Sequential Circuits.

 Where to store large data?
• Flip-flops?
• Array of flip-flops?
• Data is the key – we need to store huge
number of bits
• => Memory
– Semiconductor memory
– Magnetic memory
– Optical memory

Digital Logic Design:Sequential Circuits.

 Related technology terms
• RAM – Random access memory
– Contrast: Sequential access memory
• ROM – Read only memory
– PROM
– EPROM
– EEPROM
• NVRAM

Digital Logic Design:Sequential Circuits.

 RAM
• Combinational or sequential design?
• Analog or digital?
• Input: Data and Address
• Control input: Read, write, chip-select
• Output: Data
• Operations: Read and write

Digital Logic Design:Sequential Circuits.

 Memory size terminology
• Bytes: 8 bits
• Size : in terms of bytes
– Kilo Bytes = 210 Bytes = ~1000 bytes = 1KB
– Mega Bytes = 220 Bytes = ~106 Bytes = 1MB
– Giga Byte (GB) = ~109 Bytes
– TeraBytes (1012B), PetaBytes (1015B), ExaBytes (1018B)
• Memory addressing
– Word addressable
– Byte addressable
Digital Logic Design:Sequential Circuits.
 RAM: Block diagram
N Data-In
No Clock!
K
Address Sometime handshake signals
Memory Unit Like ACK, REQ are there.
Read 2K words
Write N bit per Word

CE
N Data-out
N=8, K= 10; Size = 1KB
N=16, K= 22; Size = 8MB

N=5, K= 12; Size = 4096x5 bits = 2560 Bytes

Digital Logic Design:Sequential Circuits.

 RAM Implementation
• Memory cells
– Flip-flops
– SRAM: Custom design using 4-8 transistors
– DRAM: Custom design using 1 transistor
• Memory cell input/output
– Data in, Data out, select line, read-write
– Select lines, Data lines

Digital Logic Design:Sequential Circuits.

 2D-Memory organization
A5 A6 A7 A8 A9

5x32 Decoder

0 1 2 Y 31
0
1
A0 2
A1
5x32 X 32 Y + X
A2
Decoder
A3

A4
31

Digital Logic Design:Sequential Circuits.

Hierarchical Memory Organization
A[9:0] Data
Memory0
CE

Data
A[9:0]
Memory1

A[11:10] CE
2 to 4
decoder Data
A[9:0]
Memory2

CE
Data
A[9:0] Memory3

CE

Digital Logic Design:Sequential Circuits.

 Verilog Code
//Memory size is 64 words of 4 bits each
module Memory(Enable, ReadWrite, Address, DataIn, DataOut)
input Enable, ReadWrite;
input [5:0] Address;
input [3:0] DataIn;
output [3:0] DataOut;
reg [3:0] DataOut;
reg [3:0] Mem[63:0];
always @(Enable or ReadWrite or DataIn or Address)
if(Enable) begin
if(ReadWrite) DataOut = Mem[Address];
else Mem[Address] = DataIn;
else DataOut = 4’bz;
end
endmodule

Digital Logic Design:Sequential Circuits.

 Summary
• Memories are integral part of digital system
• Used to store data, control, configuration

Digital Logic Design:Sequential Circuits.