Logic Gates

o The logic gates are the main structural part of a digital system.
o Logic Gates are a block of hardware that produces signals of binary 1 or 0 when
input logic requirements are satisfied.
o Each gate has a distinct graphic symbol, and its operation can be described by
means of algebraic expressions.
o The seven basic logic gates include: AND, OR, XOR, NOT, NAND, NOR, and
XNOR.
o The relationship between the input-output binary variables for each gate can be
represented in tabular form by a truth table.
o Each gate has one or two binary input variables designated by A and B and one
binary output variable designated by x.

AND GATE:
The AND gate is an electronic circuit which gives a high output only if all its inputs are
high. The AND operation is represented by a dot (.) sign.

OR GATE:
The OR gate is an electronic circuit which gives a high output if one or more of its inputs
are high. The operation performed by an OR gate is represented by a plus (+) sign.

NOT GATE:
The NOT gate is an electronic circuit which produces an inverted version of the input at
its output. It is also known as an Inverter.

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NAND GATE:
The NOT-AND (NAND) gate which is equal to an AND gate followed by a NOT gate. The
NAND gate gives a high output if any of the inputs are low. The NAND gate is
represented by a AND gate with a small circle on the output. The small circle represents
inversion.

NOR GATE:
The NOT-OR (NOR) gate which is equal to an OR gate followed by a NOT gate. The NOR
gate gives a low output if any of the inputs are high. The NOR gate is represented by an
OR gate with a small circle on the output. The small circle represents inversion.

Exclusive-OR/ XOR GATE:

The 'Exclusive-OR' gate is a circuit which will give a high output if one of its inputs is
high but not both of them. The XOR operation is represented by an encircled plus sign.

EXCLUSIVE-NOR/Equivalence GATE:
The 'Exclusive-NOR' gate is a circuit that does the inverse operation to the XOR gate.
It will give a low output if one of its inputs is high but not both of them. The small circle
represents inversion.

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Universal Gates:

A universal gate is a gate which can implement any Boolean function without need to use
any other gate type. The NAND and NOR gates are universal gates. In practice, this is
advantageous since NAND and NOR gates are economical and easier to fabricate and are
the basic gates used in all IC digital logic families.

An AND gate is typically implemented as a NAND gate followed by an inverter, likewise,

an OR gate is typically implemented as a NOR gate followed by an inverter.

NAND Gate is a Universal Gate:

To prove that any Boolean function can be implemented using only NAND gates, we will
show that the AND, OR, and NOT operations can be performed using only these gates.

1. Implementing an Inverter Using only NAND Gate

The figure shows the way in which a NAND gate can be used as an inverter (NOT gate).
All NAND input pins connect to the input signal A gives an output A’.

2. Implementing AND using only NAND Gates

An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced
by a NAND gate with its output complemented by a NAND gate inverter).

3. Implementing OR using only NAND Gates

An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is
replaced by a NAND gate with all its inputs complemented by NAND gate inverters).

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Thus, the NAND gate is a universal gate since it can implement the AND, OR and NOT
functions.

NOR gate using NAND EX-OR gate using NAND

NOR Gate is a Universal Gate:

To prove that any Boolean function can be implemented using only NOR gates, we will
show that the AND, OR, and NOT operations can be performed using only these gates.

1. Implementing an Inverter Using only NOR Gate

The figure shows the way in which a NOR gate can be used as an inverter (NOT gate).
All NOR input pins connect to the input signal A gives an output A’.

2. Implementing OR Using only NOR Gates

An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by
a NOR gate with its output complemented by a NOR gate inverter)

3. Implementing AND Using only NOR Gates

An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is
replaced by a NOR gate with all its inputs complemented by NOR gate inverters)

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Thus, the NOR gate is a universal gate since it can implement the AND, OR and NOT
functions.

NAND gate using NOR EX-NOR gate using NOR

Exercise:

1. Implement Y = AB + A + (B+C) using NAND Gate only.

2. Realize Y = A + BCD using NAND Gate only.
3. Realize Y = (A+C) (A+D) (A+B+C) using NOR Gate only.

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Introduction to Combinational and Sequential Circuits:

Digital logic circuits can be classified into “combinational” and “sequential”. A

combinational logic circuit is one whose output solely depends on its current inputs.
Sequential circuits, on the other hand, are built using combinational circuits and memory
elements called “flip-flops”. These circuits generate output that depends on the current
and previous states. A Digital logic (or Switching) circuit has voltage levels to be switched
from one value to another but has a finite number of distinct values (generally 0 for false
and 1 for true). These circuits operate a definite set of logic rules so it is also known as
Logic circuits. These are basic circuits that are used in mobile phones, calculators,
computers, etc. Types of Logic Circuits: There are two types of Digital circuits depending
on their output and memory used:
(i) Combinational circuit, and
(ii) Sequential circuit

1. Combinational Circuits: These circuits are developed using AND, OR, NOT, NAND,
and NOR logic gates. These logic gates are building blocks of combinational
circuits. A combinational circuit consists of input variables and output variables.
Since these circuits are not dependent upon previous input to generate any output,
so are combinational logic circuits. A combinational circuit can have an n number
of inputs and m number of outputs. In combinational circuits, the output at any
time is a direct function of the applied external inputs.

2. Sequential circuits: A sequential circuit is specified by a time sequence of inputs,

outputs, and internal states. The output of a sequential circuit depends not only
on the combination of present inputs but also on the previous outputs. Unlike
combinational circuits, sequential circuits include memory elements with
combinational circuits. Some examples are counters and shift registers.

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1. Half Adder (HA):
Half adder is the simplest of all adder circuits. Half adder is a combinational arithmetic
circuit that adds two numbers and produces a sum bit (s) and carry bit (c) both as output.
The addition of 2 bits is done using a combination circuit called a Half adder. The input
variables are augend and addend bits and output variables are sum & carry bits. A and B
are the two input bits.

let us consider two input bits A and B, then sum bit (s) is the X-OR of A and B. it is
evident from the function of a half adder that it requires one X-OR gate and one AND
gate for its construction.

Block Diagram:

Truth Table:

Implementation:

Sum = A XOR B

Carry = A AND B

[Note: Half adder has only two inputs and there is no provision to add a carry coming
from the lower order bits when multi addition is performed.]

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 2. Full Adder (FA):
Full Adder is the adder that adds three inputs and produces two outputs. The first two
inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM. A full adder
logic is designed in such a manner that can take eight inputs together to create a byte-
wide adder and cascade the carry bit from one adder to another. We use a full adder
because when a carry-in bit is available, another 1-bit adder must be used since a 1-bit
half-adder does not take a carry-in bit. A 1-bit full adder adds three operands and
generates 2-bit results.

Block Diagram:

Truth Table:

Implementation:

Sum = A XOR B XOR Cin

Carryout = AB+BCin+CinA

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Implementation of Full Adder using NAND gates:

Implementation of Full Adder using NOR gates:

3. Half Subtractor (HS):

The half subtractor is also a building block for subtracting two binary numbers. It has
two inputs and two outputs. This circuit is used to subtract two single bit binary numbers
A and B. The 'diff' and 'borrow' are two output states of the half subtractor.

Block diagram:

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Truth Table:

Diff= A'B+AB' = A XOR B

Borrow = A'B

In the above table,

o 'A' and 'B' are the input variables whose values are going to be subtracted.
o The 'Diff' and 'Borrow' are the variables whose values define the subtraction
result, i.e., difference and borrow.
o The first two rows and the last row, the difference is 1, but the 'Borrow' variable
is 0.
o The third row is different from the remaining one. When we subtract the bit 1
from the bit 0, the borrow bit is produced.

Implementation:

The Half Subtractor is designed by combining the 'XOR', 'AND', and 'NOT' gates and
provide the Diff and Borrow.

The Boolean expression of the Half Adder circuit is given below:

Diff= A XOR B (A⊕B)
Borrow= not-A AND B (A'.B)
4. Full Subtractor:

The Half Subtractor is used to subtract only two numbers. To overcome this problem, a
full subtractor was designed. The full subtractor is used to subtract three 1-bit numbers
A, B, and C, which are minuend, subtrahend, and borrow, respectively. The full subtractor
has three input states and two output states i.e., diff and borrow.

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Block diagram

Truth Table

In the above table,

o 'A' and' B' are the input variables. These variables represent the two significant
bits that are going to be subtracted.
o 'Borrowin' is the third input which represents borrow.
o The 'Diff' and 'Borrow' are the output variables that define the output values.
o The eight rows under the input variable designate all possible combinations of 0
and 1 that can occur in these variables.

Implementation:
The full subtractor logic circuit can be constructed using the 'AND', 'XOR', and NOT
gate with an OR gate.

The actual logic circuit of the full subtractor is shown in the above diagram. The full
subtractor circuit construction can also be represented in a Boolean expression.

Diff:
o The difference is represented as: (A ⊕ B) ⊕ Borrowin

Borrow:
o The 'Borrow' can be represented as: A'.B + A'.Borrowin + B. Borrowin

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5. Decoder:
The combinational circuit that changes the binary information into 2N output lines is
known as Decoders. The binary information is passed in the form of N input lines. The
output lines define the 2N-bit code for the binary information. In simple words,
the Decoder performs the reverse operation of the Encoder. At a time, only one input
line is activated for simplicity. The produced 2N-bit output code is equivalent to the
binary information. Only for the specific input combination only one of the output will
be high.

2 to 4 line decoder:
In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E and four
outputs, i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is
set to 1, one of these four outputs will be 1. The block diagram and the truth table of
the 2 to 4 line decoder are given below.

Block Diagram:

Truth Table:

The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:

Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

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Logical circuit of the above expressions is given below:

6. Encoders

The combinational circuits that change the binary information into N output lines are
known as Encoders. The binary information is passed in the form of 2N input lines. The
output lines define the N-bit code for the binary information. In simple words,
the Encoder performs the reverse operation of the Decoder. At a time, only one input
line is activated for simplicity. The produced N-bit output code is equivalent to the binary
information. At a specific time only one of the input is high and depending on the
which input is high, we get the specific code at the output.

4 to 2 line Encoder:

In 4 to 2 line encoder, there are total of four inputs, i.e., Y0, Y1, Y2, and Y3, and two
outputs, i.e., A0 and A1. In 4-input lines, one input-line is set to true at a time to get the
respective binary code in the output side. Below are the block diagram and the truth
table of the 4 to 2 line encoder.

Block Diagram:

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Truth Table:

The logical expression of the term A0 and A1 is as follows:

A1=Y3+Y2
A0=Y3+Y1
Logical circuit of the above expressions is given below:

7. Multiplexer

A multiplexer is a combinational circuit that has 2n input lines and a single output line.
Simply, the multiplexer is a multi-input and single-output combinational circuit. The
binary information is received from the input lines and directed to the output line. On
the basis of the values of the selection lines, one of these data inputs will be connected
to the output.

Unlike encoder and decoder, there are n selection lines and 2n input lines. So, there is a
total of 2N possible combinations of inputs. A multiplexer is also treated as Mux.

2×1 Multiplexer:

In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e., S0 and
single outputs, i.e., Y. On the basis of the combination of inputs which are present at the
selection line S0, one of these 2 inputs will be connected to the output. The block diagram
and the truth table of the 2×1 multiplexer are given below.

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Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1
Logical circuit of the above expression is given below:

8. De-multiplexer:

A De-multiplexer is a combinational circuit that has only 1 input line and 2N output lines.
Simply, the multiplexer is a single-input and multi-output combinational circuit. The
information is received from the single input lines and directed to the output line. On
the basis of the values of the selection lines, the input will be connected to one of these
outputs. De-multiplexer is opposite to the multiplexer.

Unlike encoder and decoder, there are n selection lines and 2 n outputs. So, there is a
total of 2n possible combinations of inputs. De-multiplexer is also treated as De-mux.

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1×2 De-multiplexer:

In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y0, and Y1, 1 selection lines,
i.e., S0, and single input, i.e., A. On the basis of the selection value, the input will be
connected to one of the outputs. The block diagram and the truth table of the 1×2
multiplexer are given below.

Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A
Logical circuit of the above expressions is given below:

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Sequential circuits: A sequential circuit is specified by a time sequence of inputs,
outputs, and internal states. The output of a sequential circuit depends not only on the
combination of present inputs but also on the previous outputs. Unlike combinational
circuits, sequential circuits include memory elements with combinational circuits. Some
examples are counters and shift registers.

Difference between the combinational circuits and sequential circuits are given below:

Combinational Circuits Sequential Circuits

1) The outputs of the combinational The outputs of the sequential circuits

circuit depend only on the present depend on both present inputs and present
inputs. state (previous output).

2) The feedback path is not present in The feedback path is present in the
the combinational circuit. sequential circuits.

3) In combinational circuits, memory In the sequential circuit, memory elements

elements are not required. play an important role and require.

4) The clock signal is not required for The clock signal is required for sequential
combinational circuits. circuits.

5) The combinational circuit is simple It is not simple to design a sequential

to design. circuit.

Types of Sequential Circuits

Asynchronous sequential circuits - The clock signals are not used by the Asynchronous
sequential circuits. The asynchronous circuit is operated through the pulses. So, the
changes in the input can change the state of the circuit. The asynchronous circuits do
not use clock pulses. The internal state is changed when the input variable is changed.
The un-clocked flip-flops or time-delayed are the memory elements of asynchronous
sequential circuits. The asynchronous sequential circuit is similar to the combinational
circuits with feedback.

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Synchronous sequential circuits - In synchronous sequential circuits, synchronization
of the memory element's state is done by the clock signal. The output is stored in either
flip-flops or latches (memory devices). The synchronization of the outputs is done with
either only negative edges of the clock signal or only positive edges.

Clock Signal and Triggering

Clock signal

A clock signal is a periodic signal in which ON time and OFF time need not be the same.
When ON time and OFF time of the clock signal are the same, a square wave is used to
represent the clock signal. Below is a diagram which represents the clock signal:

A clock signal is considered as the square wave. Sometimes, the signal stays at logic,
either high 5V or low 0V, to an equal amount of time. It repeats with a certain time
period, which will be equal to twice the 'ON time' or 'OFF time'.

Types of Triggering

These are two types of triggering in sequential circuits:

i. Level triggering

The logic High and logic Low are the two levels in the clock signal. In level triggering,
when the clock pulse is at a particular level, only then the circuit is activated. There are
the following types of level triggering:

Positive level triggering

In a positive level triggering, the signal with Logic High occurs. So, in this triggering, the
circuit is operated with such type of clock signal. Below is the diagram of positive level
triggering:

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Negative level triggering

In negative level triggering, the signal with Logic Low occurs. So, in this triggering, the
circuit is operated with such type of clock signal. Below is the diagram of Negative level
triggering:

ii. Edge triggering

In clock signal of edge triggering, two types of transitions occur, i.e., transition either
from Logic Low to Logic High or Logic High to Logic Low.

Based on the transitions of the clock signal, there are the following types of edge
triggering:

Positive edge triggering

The transition from Logic Low to Logic High occurs in the clock signal of positive edge
triggering. So, in positive edge triggering, the circuit is operated with such type of clock
signal. The diagram of positive edge triggering is given below.

Negative edge triggering

The transition from Logic High to Logic low occurs in the clock signal of negative edge
triggering. So, in negative edge triggering, the circuit is operated with such type of clock
signal. The diagram of negative edge triggering is given below.

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There are two types of memory elements based on the type of triggering that is suitable
to operate it.
 Latches
 Flip-flops
Latches operate with enable signal, which is level sensitive. Whereas, flip-flops are edge
sensitive.

SR Latch:
SR Latch is also called as Set Reset Latch. This latch affects the outputs as long as the
enable, E is maintained at ‘1’. The circuit diagram of SR Latch is shown in the following
figure.

This circuit has two inputs S & R and two outputs Q(t) & Q(t’). The upper NOR gate has
two inputs R & complement of present state, Q(t’) and produces next state, Q(t+1) when
enable, E is ‘1’. Similarly, the lower NOR gate has two inputs S & present state, Q(t) and
produces complement of next state, Q(t+1)’ when enable, E is ‘1’. We know that a 2-input
NOR gate produces an output, which is the complement of another input when one of the
input is ‘0’. Similarly, it produces ‘0’ output, when one of the input is ‘1’.
 If S = 1, then next state Q(t+1) will be equal to ‘1’ irrespective of present state,
Q(t) values.
 If R = 1, then next state Q(t+1) will be equal to ‘0’ irrespective of present state,
Q(t) values.
At any time, only of those two inputs should be ‘1’. If both inputs are ‘1’, then the next
state Q(t+1) value is undefined.
The following table shows the state table of SR latch.

S R Q(t+1)

0 0 Q(t)

0 1 0

1 0 1

1 1 -

Therefore, SR Latch performs three types of functions such as Hold, Set & Reset based
on the input conditions.
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D Latch:

There is one drawback of SR Latch. That is the next state value can’t be predicted when
both the inputs S & R are one. So, we can overcome this difficulty by D Latch. It is also
called as Data Latch. The circuit diagram of D Latch is shown in the following figure.

This circuit has single input D and two outputs Q(t) & Q(t’). D Latch is obtained from SR
Latch by placing an inverter between S amp; & R inputs and connect D input to S. That
means we eliminated the combinations of S & R are of same value.
 If D = 0 → S = 0 & R = 1, then next state Q(t+1) will be equal to ‘0’ irrespective of
present state, Q(t) values. This is corresponding to the second row of SR Latch
state table.
 If D = 1 → S = 1 & R = 0, then next state Q(t+1) will be equal to ‘1’ irrespective of
present state, Q(t) values. This is corresponding to the third row of SR Latch
state table.
The following table shows the state table of D latch.

D Qt+1t+1

0 0

1 1

Therefore, D Latch Hold the information that is available on data input, D. That means
the output of D Latch is sensitive to the changes in the input, D as long as the enable is
High.

So far we implemented various Latches by providing the cross coupling between NOR
gates. Similarly, you can implement these Latches using NAND gates.

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Basics of Flip Flop

A circuit that has two stable states is treated as a flip flop. These stable states are
used to store binary data that can be changed by applying varying inputs. The flip flops
are the fundamental building blocks of the digital system. Flip flops and latches are
examples of data storage elements. In the sequential logical circuit, the flip flop is the
basic storage element. The latches and flip flops are the basic storage elements but
different in working. There are the following types of flip flops:

SR Flip Flop:

The S-R flip flop is the most common flip flop used in the digital system. In SR flip flop,
when the set input "S" is true, the output Y will be high, and Y' will be low. It is required
that the wiring of the circuit is maintained when the outputs are established. We
maintain the wiring until set or reset input goes high, or power is shutdown.

Truth Table

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J-K Flip-flop:

The JK flip flop is used to remove the drawback of the S-R flip flop, i.e., undefined states.
The JK flip flop is formed by doing modification in the SR flip flop. The S-R flip flop is
improved in order to construct the J-K flip flop. When S and R input is set to true, the
SR flip flop gives an inaccurate result. But in the case of JK flip flop, it gives the correct
output.

In J-K flip flop, if both of its inputs are different, the value of J at the next clock edge
is taken by the output Y. If both of its input is low, then no change occurs, and if high at
the clock edge, then from one state to the other, the output will be toggled. The JK Flip
Flop is a Set or Reset Flip flop in the digital system.

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Truth Table

D Flip Flop:

The D flip-flop is a clocked flip-flop with a single digital input ‘D’. Each time a D flip-flop
is clocked, its output follows the state of ‘D’. The D Flip Flop has only two inputs D and
CP. The D inputs go precisely to the S input and its complement is used to the R input.

Considering the pulse input is at 0, the outputs of gates 3 and 4 are at the 1 level and
the circuit cannot convert state regardless of the value of D. The D input is sampled
when CP = 1. If D is 1, the Q output goes to 1, locating the circuit in the set state. If D
is 0, output Q goes to 0, and the circuit switches to a clear state.

Truth Table

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T Flip Flop:

In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a single
input called "Toggle" or "Trigger" input to avoid an intermediate state occurrence. Now,
this flip-flop work as a Toggle switch. The next output state is changed with the
complement of the present state output. This process is known as "Toggling"'.

We can construct the "T Flip Flop" by making changes in the "JK Flip Flop". The "T Flip
Flop" has only one input, which is constructed by connecting the input of JK flip flop. This
single input is called T. In simple words, we can construct the "T Flip Flop" by converting
a "JK Flip Flop". Sometimes the "T Flip Flop" is referred to as single input "JK Flip Flop".

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Truth Table:

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