TIMING PATHS

Timing paths:-
 A timing path is a point – to – point path in a design which can propagate data from one flip – flop to
another.
 Each point has a start point & an end point.
 Start point:- Input ports or clock pin of flip – flops
 End points:- Output ports or data input pin of flip – flops.

COMBO COMBO COMBO

RReg

RReg
IN OUT
LOGIC LOGIC LOGIC

COMBO
IN OUT
LOGIC
 Timing paths grouped into 4 paths i.e,
1. IN – REG.
2. REG – REG.
3. REG – OUT. I
Q D
4. IN – OUT. N
Clk

IN – REG Timing analysis:-

Setup Slack (ss) = RT – AT
 (Tclk + Tcapture_clk – Tsetup – Tuncertainty) –
( Tlaunch_clk + Tclk-q + Tcomb)
 Rearranging the eq:

 SS = (Tclk + Tcapture_clk – Tun – Tsu) – (Tlaunch_clk + Text + Tcomb_int)

Similarly Hold Eq:-
 HS = AT – RT
HS = (Tlaunch + Text + Tcomb_int ) – (Tcapture + Tun +Thold).

REG – OUT path :-

 SS = RT – AT O
Q U D
 (Tclk + Tcapture – Tsu – Tun ) –
T
(Tlaunch + Tclk-q + Tcomb_int + Tcomb_ext)
 (Tclk + Tcapture – Tsu – Tcomb_ext – Tun ) –
(Tlaunch + Tclk-q + Tcomb_int)
Rearrange the eq:-

SS = Tclk +Tcapture – Text – Tun – ( Tlaunch + Tclk-q + Tcomb_int)

HS = Tlaunch + Tclk-q + Tcomb_int – ( Tcapture – Text + Tun )
 Multi-Cycle Path:
 A timing path that takes more than one clock cycle for data propagation.
 You need to specify the launch and capture clock edges in the SDC (Synopsys Design Constraints) file.

 Half-Cycle Path:
 A half cycle path is a timing path where data is propagated during both the rising and falling edges
of the clock (half a cycle each).
 Tools can automatically detect it, so you don’t need to specify the launch or capture edge in SDC.

 False Path:
 A path that exists physically but doesn’t carry any functional data (it’s inactive).
 False paths are excluded from timing analysis because they don’t impact the circuit’s performance.
Clock Skew :-
 Clock skew is the difference in arrival time of the clock signal at two flip-flops in a design.

Tskew = Tlaunch – Tcapture.

• Here , Tlaunch = Arrival time of the clock at the launch flop.

• Tcapture = Arrival time of the clock at the capture flop.
Positive Skew :-
 If the capture clock comes late then the launch clock.
• it means Launch clock  Early & Capture clock  Late.

Tlaunch < Tcapture  good for setup violation.

Negative Skew :-
 If capture clock comes early then the launch clock.
Tlaunch > Tcapture  Hold for setup violation.
Equation for setup:-
• Tsetup with Skew
DAT < DRT  Tlaunch_clk + Tclk-q + Tcomb < Tcapture_clk – Tsetup + Skew

• Thold with Skew

DAT > DRT  Tlaunch_clk + Tclk-q + Tcomb > Tcapture_clk + Thold + Skew

 Here, Positive skew helps setup timing by effectively giving more time for data propagation(DAT
takes more time).
 Negative Skew helps hold timing by reducing the risk of data arriving too early.
DAT & DRT ? Means
DRT  Data Required Time
• The latest time by which data must arrive at the capture flop.

DRT = Tcapture_clk – Tsetup

DAT  Data Arrival Time
• The actual time taken by the data to arrive at the capture flop.
DAT = Tlaunch_clk + Tclk-q + Tcomb
• Tlaunch_clk = clock arrival time of the launch flop.
• Tclk-q = clock to Q delay of the flop.
• Tcomb = Delay through the combo logic.
Zero Skew :-
 When the capture clock & launch clock arrives at the same time is known as Zero Skew( ideally, it is
not possible).
Local Skew :-
 Difference in arrival time of clock at two consecutive pins of flops.
 It can either positive or negative.
Global Skew:-
 Difference between longest path delay & shortest path delay( min insertion delay & max insertion
delay).
Global skew = L2 –L1( L2  longest path & L1  shortest path)
Max insertion delay :-
• Delay of the clock signal takes to propagate to the farthest leaf cells in the design.
• Leaf cells  lowest level cell in the design(sequential cells).
Min insertion delay:-
• Delay of the clock signal takes to propagate to the nearest leaf cells in the design.
Useful Skew:-
 If clock is skewed intentionally to resolve violations.
Benefits of Useful Skew
• Timing Optimization: By adjusting the clock arrival times, designers can meet setup and hold time.
• Load Balancing: Useful skew can help balance the load across different parts of the circuit, reducing
the maximum current draw and improving power distribution.
• Clock Tree Synthesis (CTS): During CTS, useful skew can be used to minimize clock tree depth and
reduce clock distribution network complexity.
• Reducing Critical Path Delays: By skewing the clock, critical path delays can be minimized,
improving overall circuit performance.
Slack :-
 The difference between the required time & arrival time.
Slack = RT – AT
• Positive slack is good for setup. Setup  Data arrives too late at the capture flop.
• Negative slack is good for hold. Hold  Data arrives too early, so it overwriting
the previous data.
 For Setup timing equations:-
DRT > DAT ( slack = DRT – DAT >0 )
DRT = Tcapture_clk – Tsetup.
DAT = Tlaunch_clk + Tcomb + Tclk-q.
Tsetup_slack = DRT – DAT
 Tcapture_clk –Tsetup – ( Tlaunch_clk + Tcomb + Tclk-q)
 Tsetup_slack > 0  setup timing is met.
 For Hold timing equations:-
DRT < DAT (slack = DAT – DRT > 0)
DRT = Tcapture_clk + Thold.
Thold_slack = DAT – DRT > 0
 Tlaunch_clk + Tcomb + Tclk-q > Tcapture_clk + Thold
 Thold_slack > 0
Latency:-
 The delay difference from the clock generation point to the clock endpoints.
On – Chip Clock source :- clock is generated inside the chip, typically by a PLL (Phase-Locked Loop)
or an oscillator.
Clock Definition point
PLL

• Here, PLL to Clock Definition point  SOURCE LATENCY.

• Clock Definition Point to Clk pin of Flop  NETWORK LATENCY.
Off – Chip Clock Source :- clock is generated outside the chip, such as by an external crystal oscillator
or a system clock module.

Clock port
PLL

• PLL is external source

On – Chip Clock Source Off – Chip Clock Source

Clock source is inside the chip(PLL) Outside the chip.
Internal Clock tree delay only. Includes external + internal delays
Skew & Jitter controlled. High skew & jitter due to external factor.
Better synchronization & Efficiency. Higher latency may reduce the
performance
• Latency are 2 types.
1. Source latency.
2. Network latency.
Source latency :-
• The delay from clock generation point ( Clk source) to the Clk definition point.
• Ex:- PLL or External Clk Source.
• Command:- Set_clock_latency 1.9 –source ( i.e source latency = 1.9)
Network latency:-
• The delay from the Clk definition point to the Clk pin of flip-flop.
• Before CTS, these are estimated delay values.
• After CTS, Actual delay values come to picture
• Command:- Set_clock_latency 0.8
• Total Latency = Source latency + Network Latency.
• Source vs Network
Source Latency Network Latency
Fixed & stays the same after CTS. Used only before CTS as estimate.
Applied to both On-Chip & Off-Chip After CTS, it is replaced by the actual
Clock Sources. clock delay values.

• For Setup:- Total Clk latency impacts the calculation of DRT at the capture flop.
• For Hold:- Latency mismatches between the launch & capture Clk paths.
Equations:-

Tcomb ≤ Tclk – Tsetup + ( Capture Latency – Launch Latency)  Setup.

Tcomb > Thold + ( Capture Latency – Launch Latency)  Hold.
(Tclk is considered, because hold is within same clock edge or clock cycle).
Insertion Delay(ID):-
• Insertion delay is the clock latency, but it is after CTS.
• ID is physical delay & latency is virtual delay.

Clock Uncertainty:-
• Variations in clock arrival time due to multiple factors like as skew, jitter, OCV, cross talk & other
margins.
• It is a pessimism factor used in timing analysis to improve the design to meets timing requirements
even in the worst scenarios.
Types of uncertainty:
1. Static clock uncertainty:-
• Doesn’t vary or varies very slowly with time.
• Slow or fixed variations like skew or process mismatches.
Ex:- Uneven wire delays in the clock network.
Sources:-
1. Clock skew.
2. OCV(On Chip Variation).
3. Load variation.
Dynamic Clock Uncertainty:-
• Varies with time or Time varying issues like jitter or voltage changes.
Ex:- Small clock signal fluctuations caused by power noise.
Sources:-
1. Jitter.
2. Voltage drop.
3. Temperature Variations.
Pre CTS uncertainty Post CTS uncertainty
• Clock skew. • Clk jitter.
• Jitter. • Margins.
• Margins for PVT.
Usage of Uncertainty for setup & hold:-
 Setup timing:
• Clock uncertainty reduces the clock period or available time of data to propagate.
Ex:- Clock uncertainty is 0.2ns  it means the usable clock period is decreased by 0.2 ns.
 Effective clock period = Tclk – Uncertainty.
Command:- Set_clock_uncertainty –setup 0.2 [ get_clocks clk_name]
Reduces the clock period for setup timing analysis by 0.2 ns.

 Hold timing :
• Clock uncertainty is added as an additional margin that the design must met. (OR) Adds margin of
safety to prevent short path issues.
Ex:- Clock uncertainty is 0.05 ns,  it means the hold timing checks include these margin
Command:- Set_clock_uncertainty –hold 0.05 [ get_clocks clk_name]
Adds a margin of 0.05 ns for hold timing.
Equations for setup & hold :
 For setup  Tcomb +Tsetup ≤ Tclk – Tuncertainty
 For Hold  Tcomb ≥ Thold + Tuncertainty
 Why Clock Uncertainty is Important?
•It reserves some time in the clock period for unexpected variations.
•Ensures that setup and hold timing are met in worst-case conditions
 What is Margin?
 A margin is an extra buffer or safety time added in timing analysis to account for uncertainties and
variations in the design and environment.
 It ensures that the design is robust under worst-case conditions and operates reliably.
 Why Do We Need Margins?
•Timing analysis is based on simulations and estimations, but real-world conditions can introduce
unexpected variations.
•Margins help account for these differences, ensuring the design meets timing even in the worst scenarios.
SLEW(Transition):-
• A signal changes between two voltage levels like from 0 to 1 or 1 to 0.
• A fast change means  high slew rate.
• Slow change means  low slew rate.
 Transition is inversely proportional to slew rate.

Slew rate = V/ T ( Rate of change of the voltage w.r.to time).

 V  Change in voltage ( 0 to 1 or 1 to 0 ).
 T  Time it takes for the signal to transition between those voltages.
 Faster Transition = Higher Slew rate = Low Transition time.
 Slower Transition = Lower Slew rate = High Transition time.
Rise Time:-
 During rising edge, the time takes for the signal to Transition from 20 % to 80% of its maximum
value (VDD).
Rise time = T of 80% - T of 20%
Fall time:-
 During Falling edge, The time takes for the signal to transition from 80% to 20% of its maximum
VDD.

Fall time = T of 20% - T of 80%

Problems :
Problem 1: Setup Timing with High Clock Uncertainty
1. Scenario:
A design has a clock period of 2 ns. The setup uncertainty is 0.5 ns, and the combinational path delay
is 1.6 ns. The setup time of the flip-flop is 0.2 ns. Determine if the design meets setup time?
• Given that Tclk = 2ns.
• Tsetupuncertainty = 0.5ns.
• Tcomb = 1.6ns.
• Tsetup = 0.2ns.
For setup  Tcomb +Tsetup ≤ Tclk – Tuncertainty
1.6 + 0.2 ≤ 2 – 0.5
 1.8 ≤ 1.5 (fails setup timing because the available clock period after uncertainty (1.5 ns) is less
than the total delay 1.8ns).

Hold Timing with Skew-Induced Uncertainty

2. Scenario:
The hold time of a flip-flop is 0.1 ns. The data path delay is 0.15 ns. The hold uncertainty due to clock
skew is 0.08 ns. Does the design meet hold timing?
Equation for Hold: Tcomb ≥ Thold + Tuncertainty
• Given Thold = 0.1ns.
• Tcomb = 0.15ns.
• Tuncertainty = 0.08ns.
0.15 ≥ 0.1 + 0.08
 0.15 ≱ 0.18 (fails hold timing because the data path delay (0.15 ns) is less than the required minimum
delay 0.18ns).

Multi-Clock Domain Setup with Jitter.

3. Scenario:
Two flip-flops are in different clock domains with a 3 ns period each. The clock domains have a clock
skew of 0.3 ns and a jitter of 0.2 ns. The setup time is 0.3 ns, and the data path delay is 2.4 ns. Does it
meet timing?
Equation for Multi-Domain Setup:
• Pre CTS Clock uncertainty = Skew + jitter + Margin
• Post CTS Clock Uncertainty = Jitter + Margin
 Tcomb + Tsetup ≤ Tclk – Uncertainty
 Uncertainty = Skew + Jitter
Rearrange the eq = Tcomb + Tsetup ≤ Tclk – ( Skew + Jitter)
 2.4 + 0.3 ≤ 3− ( 0.3 + 0.2)
 2.7 ≤ 2.5 (fails setup timing due to excessive skew and jitter).

CTS Uncertainty Impact

4. Scenario
Before clock tree synthesis (CTS), the setup uncertainty is modelled as 0.4 ns due to skew, jitter, and
margins. After CTS, skew is reduced to 0.1 ns, but jitter remains 0.2 ns. How does the uncertainty
change, and what is its impact on timing?
• Pre CTS Clock uncertainty = Skew + jitter + Margin .
• Post CTS Clock Uncertainty = Jitter + Margin.
• After CTS, the uncertainty reduces by 0.1 ns, increasing the available clock period.
Clock Jitter:-
 Jitter refers short – term violation in the timing of a clock signal compared to its ideal timing.
Ex:- Imagine a clock pulse expected to arrive every 1ns.
• Due to jitter, the clock pulse might arrive slightly earlier or late (like 0.95ns or 1.05ns).
• This variations impacts the clock period, it causes synchronization issues in the circuits.
Source of jitter:
 Internal circuitry of PLL.
• Noise or imperfections in PLL circuits can introduce variations.
 Thermal noise in crystal oscillators.
• Heat can cause small fluctuations in the frequency of oscillators
 Transmitters & Receivers.
• Signal transmission paths can also introduce timing variations.
 When we are using clock signal, there are 2 phases in the design i.e
1. Ideal clock. 2. Propagated clock.
Ideal Clock:-
• In the first stage, during RTL design, Synthesis & placement  Clock is IDEAL.
• The ideal Clock has no distribution tree.
• It is directly connected at the same time to all flop clock pins.(so no delay or no violations)
Propagated Clock:-
• After CTS, the clock travels through a tree of buffers to reach the flip flop.
• Actual delays are introduced due to routing & buffers.
 Clock latency term using when the clock is in ideal mode.
 It is the delay that exists from the clock source to the clock pin of the flop.
 This delay is not real value  specified by the USER.
When comes to Propagated clock ,  After CTS
 Actual delay comes into the picture then it is called as insertion delay.
 Insertion Delay is a real & measured delay path through a tree of buffers.
How Jitter Affects the Design
 Setup Violations:
• If jitter reduces the effective clock period, data might not be ready in time.
 Hold Violations:
• If jitter causes the clock edge to arrive earlier, data might not have been held long enough.
 Signal Integrity Issues:
• Large jitter can disrupt timing relationships across flip-flops.

Types of Jitter (What They Are)

 Absolute Jitter → Signal arrives earlier or later than expected.

 Cycle-to-Cycle Jitter → One clock cycle length changes compared to the next.
 Periodic Jitter → Jitter happens at regular intervals due to interference.
 Random Jitter → Unpredictable, caused by thermal noise or power fluctuations.
 Deterministic Jitter → Caused by specific, known factors (like crosstalk or power noise).
Methods to Reduce Jitter (How to Fix It)
 Use low-jitter clock sources (for Absolute & Cycle-to-Cycle Jitter).
 Use jitter buffers (for Absolute & Periodic Jitter).
 Filter out power noise with capacitors (for Periodic & Random Jitter).
 Improve PCB design & shielding (for Deterministic Jitter).

Ex:-DDR RAM in a High-Speed Design

• Imagine designing a motherboard where DDR4 RAM communicates with the CPU.
• If jitter is too high:  Data errors → System crashes.
 Slow performance
 By applying the above methods (good clock, clean power, short traces, differential pairs), we reduce
jitter and ensure fast, error-free communication!
Why the Clock Doesn't Always Arrive Exactly After One Clock Cycle? or
Why does the clock not always arrive exactly after one clock period?
1. Insertion Delay and Skew
 Insertion Delay:
The time it takes for the clock signal to travel from the clock source to the flip-flop clock pin.
 Skew:
If the insertion delay to the launch clock (starting flip-flop) and the capture clock (destination flip-
flop) are different, the clock edges won't align.
• Example: If the capture clock arrives earlier than the launch clock, this difference is called
negative skew. If it arrives later, it is positive skew
2. Clock Jitter
 The clock period is not constant.
• Some cycles might be slightly longer or shorter due to variations in the clock source (like a PLL or
oscillator).
• This random fluctuation in clock period is called jitter.
• Effect: Jitter makes it hard to predict exactly when the next clock edge will occur.
3. On-Chip Variation (OCV)
 Different parts of the chip may behave differently due to changes in PVT ( process, voltage, or
temperature).
 This can make the clock slower or faster in some areas, increasing the difference in timing.

 Why MCMM (Multi-Corner Multi-Mode) is Important?

MCMM analysis ensures a chip works correctly under all conditions by considering:
1. Multi-Corner (PVT Variations)
• Process: Fabrication variations affect transistor performance.
• Voltage: Supply voltage fluctuations impact speed and power.
• Temperature: The chip must work from -40°C to 125°C (extreme conditions).
 Prevents failures due to process, voltage, and temperature variations.
2. Multi-Mode (Different Functional Scenarios)
• Functional Mode (normal operation)
• Test Mode (DFT scan & testing)
• Low-Power Mode (power-saving state)
 Why MCMM is NECESSARY?
 Ensures timing closure across all PVT conditions.
 Prevents setup & hold violations.
 Avoids chip failures in real-world applications.
 Improves yield, reliability, and silicon success.

 MCMM is Related to STA?

 STA checks timing across all MCMM scenarios to ensure the chip works under all conditions.
 Setup & Hold Timing Closure: Different corners and modes can affect timing margins, so STA ensures
no violations.
 Clock Skew & Uncertainty: STA considers worst-case delays across PVT variations to avoid timing
failures.
 Signoff Requirement: Modern chips must pass STA for all MCMM cases before tapeout.
 Why MCMM Essential in STA?
 Ensures chip works across all voltage, temperature, and process variations.
 Avoids failures in different operating conditions.
 Reduces ECOs (Engineering Change Orders) by catching violations early.
 Improves silicon yield and performance reliability.
 Without MCMM in STA, a chip might pass in one condition but fail in another!

Propagation delay :-
 Propagation delay is the time taken for a signal to travel through the combinational logic (gates and
interconnects) between the launching flip-flop and the capturing flip-flop.
 This delay depends on:
• The logic complexity in the path.
• Interconnect delays (RC delays).
• PVT variations (Process, Voltage, Temperature).
Setup :-
 Min time that the input (Data) must be stable before the clock edge ( Usually the Falling & Rising
edges, depending upon the design) in order to be correctly captured by the flip-flop.
 Data must be stable before the clock edge.
 If setup time violation occurs when the data input changes too close to the clock edge, it might
incorrect data capture.
Setup time = DRT ≥ DAT ( No setup violations)
Tclk ≥ Tsetup + Tclk-q + Tcomb
Hold :-
 Min time that the input (Data) must remain stable after the clock edge so it ensures the correct
operation of flip-flop.
 Data must be stable after the clock edge.
 If hold time violation occurs when the new data arrives too early, it might corrupt the currently
captured value.
Hold time = DRT ≤ DAT ( No hold violations)
Thold ≤ Tcomb + Tclk-q
Launch and Capture:
 Launch Flip-Flop: Flip-flop where the data is sent out (launched).
 Capture Flip-Flop: Flip-flop where the data is received (captured).
 Launch Edge: Clock edge that triggers data launch.
 Capture Edge: Clock edge that triggers data capture.

 Select the correct equation for setup time requirement ?

Tc2q – clock to Q FF delay, Tcomb – combinational delay, Tsetup – Setup time, Tclk – Clock Period,
Tskew – Clock skew
 a) Tc2q + Tcomb + Tsetup ≤ Tclk + Tskew
b) Tc2q + Tcomb + Tsetup > Tclk + Tskew
c) Tc2q + Tsetup ≤ Tclk + Tskew + Tcomb
d) None of the above.
Metastability :-
 Metastability occurs when a flip-flop receives an input signal too close to the clock edge, causing it to enter
an unstable state. This can result in unpredictable behavior, leading to timing failures in a design.
 How to Prevent Metastability?
 Use Two-Stage Synchronizers – Add extra flip-flops to allow enough settling time.
 Increase Setup & Hold Time Margins – Ensure signals arrive well before the clock edge.
 Use Proper Clock Domain Crossing (CDC) Techniques – Prevent data corruption when transferring
signals between different clock domains.
Clock Domain Crossing (CDC):-
 CDC happens when a signal moves from one clock domain to another with a different frequency or phase.
Problem:
 If not handled properly, CDC can cause data corruption or metastability, leading to design failures.
Solutions to CDC Issues:
 Two-Flip-Flop Synchronizer → Used for single-bit control signals like resets and enables.
 FIFO (First-In-First-Out Buffer) → Used for multi-bit data transfer between different clock domains.
 Handshake Protocols → Ensures safe data transfer using request/acknowledge signals.
 Gray Code Counters → Used in asynchronous FIFOs to avoid metastability in read/write pointers.
 During Placement Stage:
 Fixing Setup Violations (Data is too slow)
1.Timing Path Groups – Prioritize paths that need optimization.
2.Create Bounds – Restrict cell movement to improve timing.
3.Placement Optimization – Use high-effort placement to reduce delays.
4.Floorplan Changes – Adjust macro placement, spacing, and pin orientation.
After Placement Stage:
1.Increase Drive Strength – Use stronger gates to speed up data propagation.
2.Use Lower Vt Cells – Swap high-threshold cells with lower-threshold ones to reduce delay. ( LVT 
SVT & HVT)
3.Insert Buffers – Helps improve transition times and reduces wire delays.
4.Reduce Excess Buffers – Too many buffers can increase delay; optimize them.
5.Use Higher Metal Layers – Reduces wire resistance and delay.
6.Replace Buffers with Inverters – Improves signal transition time.
7.Play with Clock Skew – Intentionally delay the clock to help meet setup timing.
 Fixing Hold Violations (Data is too fast)
Use Higher Drive Strength Gates – Sometimes, stronger gates slow transitions by increasing
capacitance.
Use Higher Vt Cells – Slower threshold cells delay signal propagation.(HVT  LVT)
Insert or Remove Buffers – Adding buffers increases delay, while removing unnecessary buffers can
balance timing.
Use Higher Metal Layers – Helps optimize wire delay.
Increase Clock-to-Q Delay – Adjusting the launching flip-flop can slow down data arrival.
Clock push & pull  launch flop  pushing & capture flop  pulling.(here increasing &
decreasing the delays)
Crosstalk:-
 Cross talk is unwanted interference between two neighbouring wires or nets in a circuit.
 It happens because of coupling capacitance between them.
 It can effect the functionality or timing. AGGRESSOR
 A net can be VICTIM or AGGRESSOR.
 High Switching or Affecting signal AGGRESSOR.
 Experienced unwanted affects or Affected signal  VICTIM. VICTIM
 Why Does Coupling Capacitance Cause Crosstalk?
 Coupling capacitance (Cc) is the capacitance between two adjacent wires.
 When the signal (voltage) in one wire (aggressor) changes, it induces a voltage in the nearby wire
(victim) through this coupling capacitance.
 This results in:
• Crosstalk Noise or Glitch : Voltage spikes (glitches) on the victim wire.
• Crosstalk Delay : Delayed or accelerated signal transition on the victim wire.
Types of Crosstalk:-
 Crosstalk Noise Or Glitch.
 Crosstalk Delay.
Crosstalk Noise or Glitch:-
 It happens when the aggressor net switches, but the victim net remains constant.
 This causes a spike(glitch) in the victim net.
• Types of Glitches:-
1. Rise Glitch  Victim is low(0) , Aggressor rises.
2. Fall Glitch  Victim is high(1), Aggressor falls.
3. Overshoot  Victim is high(1), Aggressor rises further.
4. Undershoot  Victim is low(0), Aggressor falls further.
 Overshoot :- Signal voltage goes too HIGH, exceeding its expected max level(above VDD).
 Undershoot :- Signal voltage drops too LOW, below its expected min level(below VSS).
Crosstalk Delay:-
 It happens when both Aggressor & Victim nets are switching.
 It can either slow down or speed up the victim net transition based on the relative switching
direction.
 There are 2 types of crosstalk delays.
1 Positive cross talk delay.
2 Negative cross talk delay.
Positive cross talk delay:-
 Aggressor switches in the opposite direction of the victim  Victim slows down.
Negative cross talk delay:-
 Aggressor switches in the same direction as the victim  Victim speeds up.
Effects of Crosstalk
1. On Noise: It creates unexpected signal spikes, disrupting functionality.
2. On Timing: It can cause data to arrive too early or too late, affecting setup and hold timing checks.
Impacts on Timing Analysis:-
Crosstalk affects Setup & Hold timing:
1. Data path Crosstalk:
• Same Direction (Negative Crosstalk):
 Victim transition  Faster, Good for setup & Bad for Hold.
• Opposite Direction(Positive Crosstalk):
 Victim transition  Slower, Bad for setup & Good for Hold.

2. Clock path Crosstalk:

• Same Direction:
 Victim clock  Faster, Bad for Setup & Good for Hold.
• Opposite Direction:
 Victim clock is  Slower, Good for Setup & Bad for Hold.
Reduce the Crosstalk:
 Increase Wire Spacing(NDR rules):
 Reduces coupling capacitance between aggressor and victim nets.

 Use Higher Metal Layers:

 Higher layers have wider wires and lower coupling.

 Buffer Insertion:
 Splits long nets to minimize crosstalk.

 Shielding:
 Place power (VDD) or ground (VSS) lines between critical signals to absorb noise.

 Adjust Drive Strength:

 Increase the victim net's drive strength or reduce the aggressor net's drive strength.

 Use Multiple Vias:

 Reduces resistance and RC delay, minimizing interference
PBA & GBA  Pessimism = Worst-case assumptions (extra safety margin).
 PBA  Path Based Analysis.  GBA: Introduces pessimism to ensure no timing violations
are overlooked.
 GBA  Graph Based Analysis.  PBA: Removes pessimism for more accurate, realistic timing
Path Based Analysis(PBA) :- in critical paths
 Analyses individual paths one by one.
 Measures signal delay on each path & checks if it meets the Required Time(RT).
 High Accurate, But Slower because it checks every possible path.
Graph Based Analysis:-
 Analyses the entire design as Graph.
Calculation:
 Arrival Time (AT): When the signal arrives.
 Required Arrival Time (RAT): When the signal is needed.
 Slack: RAT - AT (to check timing margin).
 Faster, but less accurate because it doesn’t examine every path in detail.
Do We Prefer PBA in Real-Time STA?
 Yes, PBA (Path-Based STA) is preferred for sign-off in real-time chip design.
 But GBA (Graph-Based STA) is preferred for faster timing closure during early stages.
 Real-Time Industry Ex:
• Scenario:
1. Tape-Out of a Processor Chip (Intel, AMD, Qualcomm, etc.)
 During initial timing closure (Pre-layout STA):
 Engineers run GBA because it's fast and helps find timing violations quickly.
 If violations exist, they fix them with margin to be safe (even if pessimistic).
 Before sign-off (Final STA using Primetime STA, Cadence Tempus, or ICC2):
 Engineers run PBA to remove unnecessary pessimism and find actual delays.
 If GBA showed a violation, PBA might clear it, reducing unnecessary fixes.
 Final Validation: (PBA is final decision – maker before the design is sent for fabrication)
 Before tape-out, only PBA results are considered to ensure accuracy.
 This prevents false timing violations and unnecessary design modifications.
 Multi-cut Vias :-
 It is like adding extra support to make connections more Reliability & Durable.
 After the layout design, when ever possible single via replaced with multi-cut vias to improve better
performance & Yield..
 Handle more current & improve functionality on wide metal.
 When to Use Multi-Cut Vias?
 High-current paths (Power & Ground Nets).
 Critical signal paths (Clock & High-speed data signals).
 Advanced nodes (e.g., 7nm, 5nm, 3nm) where single vias are unreliable.
 Chip corners & high-stress areas where via failure risk is higher.
 When NOT to Use Multi-Cut Vias?
 Non-critical paths where single vias are sufficient.
 Tight routing areas where space is limited
 Redundant Vias:-
 It is like safety backup to ensure the connections stay strong & chip work reliability.
• Improve yield.
• Lower resistance  making signal faster.
• Avoid timing issues from Partial failures.
 Why Use Redundant Vias?
 Prevents Failure  If the main via fails, the extra one keeps the connection.
 Improves Reliability  Reduces the chance of open circuits.
 Better for Manufacturing  Helps avoid defects caused by process variations.
 When to Use Redundant Vias?
 Critical signal paths (Clock, Power, Ground).
 Areas with manufacturing variation risks.
 Smaller technology nodes (7nm, 5nm, 3nm) where via failures are more common.
Multi-cut Vias (Vs) Redundant vias ?
Multi-cut Vias Redundant vias

Uses multiple vias in one place for a stronger Adds extra vias next to the main via as a backup
connection
Reduces resistance & improves performance Prevents via failure and improves reliability
High-current paths (power, ground, clock signals) Areas where single vias might fail due to defects
Load spread across all vias If the main via fails, backup via takes over

 Imagine you are designing a mobile processor chip (like in smartphones)

 Why Use Redundant Vias
 If one via fails, the extra via keeps the connection working.
 Prevents chip failure and improves reliability.
 Used in modern processors (5nm, 3nm) for better performance.
 In a smartphone chip, redundant vias help prevent power loss and improve battery efficiency.
 PVT (Process, Voltage & Temperature):-
 A chip should work in all conditions—from freezing cold (-40°C ) to extreme heat.
 To ensure this, we simulate the chip under different PVT corners to check timing.
1. Process Variation (P) – Changes During Manufacturing
 Transistor properties change due to manufacturing imperfections.
Ex: Some chips on a wafer may be fast, some slow due to variations in materials.
 Affects delay: Slow process → Higher delay.
Fast process → Lower delay.
2. Voltage Variation(V) – Power Supply Instability
 Voltage is not always constant (e.g., 1V can fluctuate to 1.1V or 0.9V).
Causes:
 IR drop: Resistance in power lines reduces voltage.
 Supply noise: Inductance effects cause voltage spikes.
Affects delay: Higher voltage → Faster circuit (lower delay).
Lower voltage → Slower circuit (higher delay).
3. Temperature Variation (T) – Heat Effects on Chip
 High temperature → Slower transistors (higher delay).
 Low temperature → Faster transistors (lower delay).
 BUT in very small transistors (<65nm), delay increases at lower temperatures, This is called
Temperature Inversion.
 Worst-Case PVT Corners in Timing Analysis:-

Check Worst Case Condition Why?

Slow Process (SS),

Maximizes delay (data may arrive
Setup Timing Low Voltage,
too late)
& High Temperature.

Fast Process (FF),

Minimizes delay (data may arrive
Hold Timing High Voltage,
too early)
&Low Temperature.
 PVT Impact on Timing: Cell Delay vs. Net Delay
 In chip design, timing analysis is important to ensure the circuit works at the desired speed.
 Timing is affected by cell delay and net delay, both of which change due to PVT variations.
• Cell Delay (Gate Delay)
 What is it?
 The time taken by a logic cell (e.g., AND, OR, Flip-Flop) to process an input and produce an output.
 It depends on transistor switching speed inside the cell.
• PVT Impact:
 Process Variation: Slower transistors increase cell delay.
 Voltage Drop: Lower voltage reduces transistor speed, increasing cell delay.
 High Temperature: Slows down transistors, increasing cell delay (except in sub-65nm nodes due to
temperature inversion).
Ex:
 A NAND gate may normally take 100ps to switch, but under slow process, low voltage, and high
temperature, it may take 120ps.
2. Net Delay (Wire Delay / Interconnect Delay)
What is it?
 The time taken for a signal to travel through the wires (interconnects) connecting different cells.
 It depends on wire resistance (R) and capacitance (C) → RC Delay.
PVT Impact:
 Process Variation: Metal width variations change wire resistance (R), increasing RC delay.
 Voltage: Has minimal impact on net delay.
 Temperature:
 High temperature increases wire resistance, increasing net delay.
 Low temperature reduces wire resistance, decreasing net delay.
Ex:
 A long interconnect between two flip-flops might have a net delay of 50ps, but under high
temperature, resistance increases, making it 60ps.
3 Timing Paths & PVT Corners
 A timing path consists of:
Launch Flop → Combinational Logic (Cell Delay) → Interconnect (Net Delay) → Capture Flop
 Setup Timing (Data must arrive before clock edge):
 Worst case: Slow Process, Low Voltage, High Temperature (increases delay).
 Affected by cell delay (major impact) + net delay.
 Hold Timing (Data must not arrive too early):
 Worst case: Fast Process, High Voltage, Low Temperature (reduces delay).
 Affected by cell delay (major impact) + net delay.

 Cell delay is mainly affected by transistor behavior (PVT variations).

 Net delay is mainly affected by RC properties of wires.
 Both delays impact setup and hold timing, which must be checked at worst PVT corners.
Ex: Fixing Setup and Hold Violations in a Real Design
Let's consider a timing path in a digital circuit:
 Launch Flip-Flop (FF1) → Logic (Gates + Wires) → Capture Flip-Flop (FF2)
Timing analysis shows:
 Clock Period: 1ns (1GHz frequency)
 Setup Time Violation: Data arrives at 1.05ns (> 1ns)
 Hold Time Violation: Data arrives at 0.05ns (< Hold time)
 Fixing Setup Violation: Data arrive too Late
 Why it happens?
1. Slow process  Transistors switch slower.
2. Long net delay  Wire resistance / capacitance too high.
3. High Temperature  Increase delay of logic gates.
 Fixing Steps:-
 Use stronger cells ( Reduce logic delay(Drive strength Increases)):
 Like replace AND2_X2 ( weak , slower)  AND2_X4 ( Faster, Stronger).
 Insert buffers (Reduce net delay):
 Insert a buffer to break a long wire into two shorter ones.
 Clock skewing (Borrow time for data arrival):
 Delay the clock at FF2 slightly, giving more time for data to arrive.
 New Data Arrival Time: 0.95ns (Now it meets the 1ns requirement).

2. Fixing Hold Violation (Data Arrives Too Early)

Why It Happens?
Fast process: Transistors switch too quickly.
Short net delay: Signal reaches too soon.
Low temperature: Reduces wire resistance, speeding up data.
Fixing Steps:
 Use weaker cells (Increase logic delay or drive strength decreases):
 Replace INV_X4 → INV_X1 (slows down switching).
 Insert delay buffers (Increase net delay):
 Add extra buffer(s) in the data path.
 Clock skewing (Reduce available time for data to arrive early):
 Speed up the clock at FF2 slightly to reduce extra time.
 New Data Arrival Time: 0.10ns (Now it meets the hold requirement).
 RC Variations:
 What is RC Variation?
 RC variation refers to changes in resistance (R) and capacitance (C) due to fabrication process
deviations.
 It impacts interconnect delay, affecting setup and hold timing.
 Worst-Case Corners for Setup & Hold
Timing Check Process Voltage Temperature Impact

Setup Violation Slow Low High Data too slow (Max delay)
Hold Violation Fast High Low Data too fast (Min delay)
 Fixes for Setup & Hold Violations

 Fix Setup Violation (Data Too Slow)

 Increase drive strength (X2 → X4 → X8).
 Use higher metal layers (low resistance).
 Add repeaters (buffers) to reduce delay.

 Fix Hold Violation (Data Too Fast)

 Add delay buffers to slow data.
 Route on lower metal layers (higher resistance).
 Increase wire length (detour routing) to add delay.
 Critical corners for Setup & Hold
Check Process (P) Voltage (V) Temperature (T) Why?
Max T (or Min T for Ensures max delay
Setup (Worst Case) Slow (SS) Min (Vmin)
temp inversion) (slowest path)
Ensures min delay
Hold (Worst Case) Fast (FF) Max (Vmax) Min T
(fastest path)
Used for power
Power Analysis Typical (TT) Nominal (Vnom) Room Temp (~25°C)
estimation