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VLSI 4

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6 views

VLSI 4

Uploaded by

sampritihaldar77
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© © All Rights Reserved
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INSTITUTE OF ENGINEERING & MANAGEMENT SALT LAKE

CAMPUS

DEPARTMENT OF ELECTRONICS AND COMMUNICATION


ENGINEERING

ADVANCED VLSI LAB

DESIGN A N BIT MOD DOWN COUNTER USING


STRUCTURAL MODELLING IN XILINX VIVADO

NAME LAB GROUP YEAR SEC ROLL ENROLLMENT NO

SAMPRITI HALDAR E2 3rd A 51 12022002003073


● THEORY: A Mod-N counter is a digital counter that cycles through N unique states, counting from 0
to (N-1) before resetting to zero. It is often called a divide-by-N counter since its output frequency
equals the input clock frequency divided by N. The number of flip-flops required to build a Mod-N
counter is log2N. For instance, a Mod-8 counter requires 3 flip-flops as 23=8. Mod-N counters are
widely used in digital systems for applications such as frequency division, digital clocks, and sequence
generation due to their reliable and predictable counting behavior.

● RTL SCHEMATIC:

● SOFTWARE USED: Xilinx Vivado


● LANGUAGE: Verilog ● VERILOG CODE:
I. D Flip Flop:
module diff(input d, input clk, input rst, output reg
q); always @ (negedge clk) begin if (rst == 1'b1)
q<=1'b0; else q<=d; end endmodule

II. Counter:
module counter( input rst, input clk, output
[2:0]q); wire a0,a1,a2; wire
b2; assign
a0=~q[0]; assign
a1=q[1]^q[0];
assign
b2=q[1]&q[0];
assign
a2=q[2]^b2;
assign
b3=q[2]&b2; diff
inst0(a0,clk,rst,q[0])
; diff
inst1(a1,clk,rst,q[1])
; diff
inst2(a2,clk,rst,q[2])
; endmodule

III. Comparator:
module comp(input [2:0]n, input [2:0]q, output
x); wire l1,l2,l3; assign l1=~(q[2]^n[2]);
assign
l2=~(q[1]^n[1]); assign l3=~(q[0]^n[0]); assign
x=(l1&l2)&l3; endmodule

IV. Top Module:


module top_module( input init, input [2:0] N, input clk, output[2:0]
q); wire p,x; assign p=init|x; counter uut0(p,clk,q); comp
uut1(N,q,x); endmodule

V. Testbench for Simulation:


a) Testbench for Counter:
module tb(); reg
clk,rst; wire [2:0] q;
counter
uut(rst,clk,q);
initial begin
clk=1'b0; rst=1'b1;
#15
rst=1'b0; #200
$finish; end always
#5 clk=~clk; endmodule

b) Testbench for Top Module:


module
tb_top(); reg
clk,init; reg
[2:0]N; wire
[2:0] q;
top_module uut(init,N,clk,q);
initial begin N=3'b101;
clk=1'b0; init =1'b1; #15
init=1'b0; #200 $finish;
end always #5
clk=~clk; endmodule

● RESULT:

Simulated Output Waveform


● DISCUSSION FROM SAMPRITI HALDAR: A Mod-N counter is a digital
circuit that counts from 0 to (N-1) before resetting. It is widely used in frequency division,
digital clocks, event counting, and sequence generation. Common applications include
traffic controllers, timers, and data sampling systems, making it vital in digital electronics.

● REFERENCE:
1. https://link.springer.com/article/10.1007/bf01384074
2. https://www.researchgate.net/profile/Zhenar-
Faeq/publication/280564747_EXPLOITING_DESIGN_OF_SYNCHRONOUS_COUNTERS_METHOD
_TO_DESIGN_AND_IMPLEMENT_MOD_6_DIRECT_DOWN_COUNTER/links/55b9fdb808ae092e9
65c1282/EXPLOITING-DESIGN-OF-SYNCHRONOUS-COUNTERS-METHOD-TO-DESIGN-
ANDIMPLEMENT-MOD-6-DIRECT-DOWN-COUNTER.pdf
3. https://link.springer.com/article/10.1007/s00037-008-0248-y

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