Vidarbha Youth Welfare Society’s

Prof Ram Meghe College of Engineering & Management, Badnera.

Third Semester B.E. (Electronics & Telecommunication Engineering)
Digital System Design
FAQ(All 6 units)

Unit 1
1

2
3

4 Convert the following binary numbers to octal and then to decimal

5 Convert the following numbers from decimal to octal and then to binary

6 Convert the following numbers from decimal to hexadecimal and then to binary
7 Convert the following binary numbers to hexadecimal and then to decimal

8 Represent the decimal number 46 in binary form using

a. Binary code b. Gray code c. BCD code d. Excess 3 code e. Octal Code f. Hexadecimal code
9
10
11

Unit 2
1 Minimize the following logical expression by Boolean Algebra
i) ABC + ABC’ + AB’C + A’BC = AB + AC + BC

i) ABC + ABC' + AB'C + A'BC = AB + AC + BC

We know that X + X = X
Also We can write X = X + X + X
Hence ABC can be written as ABC+ABC+ABC
Y=ABC+ABC+ABC+ABC′+AB′C+A′BC
=(ABC+ABC′)+(ABC+AB′C)+(ABC+A′BC)
=(ABC+ABC′)+(ABC+AB′C)+(ABC+A′BC)
=(AB(C+C′))+(AC(B+B′))+(BC(A+A′))
=(AB(1))+(AC(1))+(BC(1))
=AB+AC+BC
2
3
4
5
6 Simplify using k-map obtain sop equation and realize using NAND Gate only
F(A,B,C,D)=ΠM(1,2,3,8,9,10,11,14)+d(7,15)
F(A,B,C,D)=∑m(0,4,5,6,12,13)+d(7,15)

7
8
9 Minimize the boolean function F(A, B, C, D) = Σm(0, 1, 2, 3, 5, 7, 8, 9, 11, 14) using K map
and implement using NAND gate only.
10
Minimize the boolean function F(A, B, C, D) = πM( 2, 6, 8, 9, 10,11,14) using K map and
implement using NOR gate only.
 Unit 3
1

2
3 Design 32:1 Mux using 16:1 Mux
4
5 Design 5 line to 32 line decoder using 4 line to 16 line decoder
6 Design 8 line to 256 line decoder using 4 line to 16 line decoder

7 Implement the following Boolean functions using PROM.

A(X,Y,Z)=∑m(5,6,7)
B(X,Y,Z)=∑m(3,5,6,7)
The given two functions are in sum of min terms form and each function is having three variables X, Y & Z.
So, we require a 3 to 8 decoder and two programmable OR gates for producing these two functions. The
corresponding PROM is shown in the following figure.

Here, 3 to 8 decoder generates eight min terms. The two programmable OR gates have the access of all
these min terms. But, only the required min terms are programmed in order to produce the respective
Boolean functions by each OR gate. The symbol ‘X’ is used for programmable connections.
8 implement the following Boolean functions using PAL.
A =XY+XZ′
B =XY′+YZ′
The given two functions are in sum of products form. There are two product terms present in each
Boolean function. So, we require four programmable AND gates & two fixed OR gates for producing those
two functions. The corresponding PAL is shown in the following figur

9 implement the following Boolean functions using PLA.

A=XY+XZ′
B=XY′+YZ+XZ′
The given two functions are in sum of products form. The number of product terms present in the given
Boolean functions A & B are two and three respectively. One product term, XZ′ is common in each
function.
So, we require four programmable AND gates & two programmable OR gates for producing those two
functions. The corresponding PLA is shown in the following figure.

The programmable AND gates have the access of both normal and complemented inputs of variables. In
the figure, the inputs X, X′, Y, Y′, Z &′ Z′, are available at the inputs of each AND gate. So, program only the
required literals in order to generate one product term by each AND gate.
All these product terms are available at the inputs of each programmable OR gate. But, only program the
required product terms in order to produce the respective Boolean functions by each OR gate. The
symbol ‘X’ is used for programmable connections.
10 Design half and full adder circuit using logic gates
11 Design half and full subtractor circuit using logic gates
12 Design BCD to Excess-3 code converter circuit using basic gates.

13 Design binary to gray code converter circuit using suitable gates.

14 Implement the following logical expression using 8:l MUX
F = Ʃm (0,1,2,3,4,10,11,14,15)
 Unit 4
1. What is Shift Registers. Explain any one of shift register
Flip flops can be used to store a single bit of binary data (1or 0). However, in order to store
multiple bits of data, we need multiple flip flops. N flip flops are to be connected in an order to
store n bits of data. A Register is a device which is used to store such information. It is a group
of flip flops connected in series used to store multiple bits of data.

The information stored within these registers can be transferred with the help of shift
registers. Shift Register is a group of flip flops used to store multiple bits of data. The bits
stored in such registers can be made to move within the registers and in/out of the registers by
applying clock pulses. An n-bit shift register can be formed by connecting n flip-flops where
each flip flop stores a single bit of data.
The registers which will shift the bits to left are called “Shift left registers”.
The registers which will shift the bits to right are called “Shift right registers”.
Shift registers are basically of 4 types. These are:
1. Serial In Serial Out shift register
2. Serial In parallel Out shift register
3. Parallel In Serial Out shift register
4. Parallel In parallel Out shift register

Serial-In Serial-Out Shift Register (SISO) –

The shift register, which allows serial input (one bit after the other through a single data line)
and produces a serial output is known as Serial-In Serial-Out shift register. Since there is only
one output, the data leaves the shift register one bit at a time in a serial pattern, thus the name
Serial-In Serial-Out Shift Register.
The logic circuit given below shows a serial-in serial-out shift register. The circuit consists of
four D flip-flops which are connected in a serial manner. All these flip-flops are synchronous
with each other since the same clock signal is applied to each flip flop.

The above circuit is an example of shift right register, taking the serial data input from the left
side of the flip flop. The main use of a SISO is to act as a delay element.
Serial-In Parallel-Out shift Register (SIPO) –

The shift register, which allows serial input (one bit after the other through a single data line)
and produces a parallel output is known as Serial-In Parallel-Out shift register.
The logic circuit given below shows a serial-in-parallel-out shift register. The circuit consists
of four D flip-flops which are connected. The clear (CLR) signal is connected in addition to the
clock signal to all the 4 flip flops in order to RESET them. The output of the first flip flop is
connected to the input of the next flip flop and so on. All these flip-flops are synchronous with
each other since the same clock signal is applied to each flip flop.

The above circuit is an example of shift right register, taking the serial data input from the left
side of the flip flop and producing a parallel output. They are used in communication lines
where demultiplexing of a data line into several parallel lines is required because the main use
of the SIPO register is to convert serial data into parallel data.

Parallel-In Serial-Out Shift Register (PISO) –

The shift register, which allows parallel input (data is given separately to each flip flop and in a
simultaneous manner) and produces a serial output is known as Parallel-In Serial-Out shift
register.
The logic circuit given below shows a parallel-in-serial-out shift register. The circuit consists
of four D flip-flops which are connected. The clock input is directly connected to all the flip
flops but the input data is connected individually to each flip flop through a multiplexer at the
input of every flip flop. The output of the previous flip flop and parallel data input are
connected to the input of the MUX and the output of MUX is connected to the next flip flop.
All these flip-flops are synchronous with each other since the same clock signal is applied to
each flip flop.
A Parallel in Serial out (PISO) shift register us used to convert parallel data to serial data.

Parallel-In Parallel-Out Shift Register (PIPO) –

The shift register, which allows parallel input (data is given separately to each flip flop and in a
simultaneous manner) and also produces a parallel output is known as Parallel-In parallel-Out
shift register.
The logic circuit given below shows a parallel-in-parallel-out shift register. The circuit consists
of four D flip-flops which are connected. The clear (CLR) signal and clock signals are
connected to all the 4 flip flops. In this type of register, there are no interconnections between
the individual flip-flops since no serial shifting of the data is required. Data is given as input
separately for each flip flop and in the same way, output also collected individually from each
flip flop.

A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and like
SISO Shift register it acts as a delay element.
Bidirectional Shift Register –

If we shift a binary number to the left by one position, it is equivalent to multiplying the
number by 2 and if we shift a binary number to the right by one position, it is equivalent to
dividing the number by 2.To perform these operations we need a register which can shift the
data in either direction.
Bidirectional shift registers are the registers which are capable of shifting the data either right
or left depending on the mode selected. If the mode selected is 1(high), the data will be shifted
towards the right direction and if the mode selected is 0(low), the data will be shifted towards
the left direction.
The logic circuit given below shows a Bidirectional shift register. The circuit consists of four
D flip-flops which are connected. The input data is connected at two ends of the circuit and
depending on the mode selected only one and gate is in the active state.
2. Draw and explain Universal shift register
A Universal shift register is a register which has both the right shift and left shift with parallel
load capabilities. Universal shift registers are used as memory elements in computers. A
Unidirectional shift register is capable of shifting in only one direction. A bidirectional shift
register is capable of shifting in both the directions. The Universal shift register is a
combination design of bidirectional shift register and a unidirectional shift register with
parallel load provision.
n-bit universal shift register –
A n-bit universal shift register consists of n flip-flops and n 4×1 multiplexers. All the n
multiplexers share the same select lines(S1 and S0)to select the mode in which the shift
register operates. The select inputs select the suitable input for the flip-flops.

Ring Counter –
A ring counter is basically a shift register counter in which the output of the first flip flop is
connected to the next flip flop and so on and the output of the last flip flop is again fed
back to the input of the first flip flop, thus the name ring counter. The data pattern within
the shift register will circulate as long as clock pulses are applied.
 The logic circuit given below shows a Ring Counter. The circuit consists of four D flip-
flops which are connected. Since the circuit consists of four flip flops the data pattern will
repeat after every four clock pulses as shown in the truth table below:

A Ring counter is generally used because it is self-decoding. No extra decoding circuit is

needed to determine what state the counter is in.
3. Draw and explain Johnson Counter
A Johnson counter is basically a shift register counter in which the output of the first flip flop
is connected to the next flip flop and so on and the inverted output of the last flip flop is again
fed back to the input of the first flip flop. They are also known as twisted ring counters.
The logic circuit given below shows a Johnson Counter. The circuit consists of four D flip-
flops which are connected. An n-stage Johnson counter yields a count sequence of 2n
different states, thus also known as a mod-2n counter. Since the circuit consists of four flip
flops the data pattern will repeat every eight clock pulses as shown in the truth table below:
 The main advantage of Johnson counter is that it only needs n number of flip-flops
compared to the ring counter to circulate a given data to generate a sequence of 2n states.
4. What is Race around condition? How it is overcome? Explain master-slave J-K flip
flop with proper table.
Race around condition occurs in JK Flip Flop when both its inputs J=K=1 and also the
clock =1 for a long period.
J-K Flip Flop
The truth table is shown below with its circuit diagram.

Race Around Condition in JK Flip-flop

For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then output Q will toggle
as long as CLK remains high which makes the output unstable or uncertain.
This is called a race around condition in J-K flip-flop.We can overcome this problem by
making the clock =1 for very less duration.The circuit used to overcome race around
conditions is called the Master Slave JK flip flop.
Master Slave JK flip flop
Here two JK flip flops are connected in series.The first JK flip flop is called
the “master” and the other is a “slave”.The output from the master is connected to the two
inputs of the slave whose output is fed back to inputs of the master. The circuit also has an
inverter other than the two flip flops.The Clock Pulse and inverter are connected because of
which the flip flops get an inverted clock pulse. In other words, if CP=0 for a master flip-
flop, then CP=1 for a slave flip-flop and vice versa.

Working of a Master Slave flip flop

When the clock pulse goes high, the slave is isolated; J and K inputs can affect the state of
the system. The slave flip-flop is isolated when the CP goes low.
When the CP goes back to 0, information is transmitted from the master flip-flop to the
slave flip-flop and output is obtained.
As the master flip flop is positive triggered it responds first and the slave later (it is
negative edge triggered).
The master goes to the K input of the slave when both inputs J=0 and K=1, and also Q’ = 1.
In this case the slave copies the master as the clock forces the slave to reset.
The master goes to the J input of the slave when both J=1 and K=0, Q = 1. The clock is set
due to the negative transition of the clock.
There is a state of toggle when both J=1 and K=1. On the negative transition of clock slave
toggles and the master toggles on the positive transition of the clock.
Both the flip flops are disabled when both J=0 and K=0 and Q is unchanged.
5. Give the difference between Synchronous and Asynchronous Counters

The following table highlights the major differences between Synchronous and
Asynchronous Counters.

Key Synchronous Counter Asynchronous Counter

In case of Synchronous In case of Asynchronous Counters,

Counters, all the constituent there is triggering of different flip-
Trigger
flip-flops are triggered with flops with different clock.
same clock simultaneously.

Operation speed of a The operation speed of an

Operation synchronous counter is faster as asynchronous counter is
Speed compared to that of an comparatively slower than a
asynchronous counter. synchronous counter.

Synchronous Counters are less Asynchronous Counters are more

error-prone; they hardly error-prone and produce decoding
Error Prone produce any decoding errors errors in the system.
because each flip-flop is
individually clocked.

All the flip-flops in a In an asynchronous counter, the

synchronous counter coordinate output of one flip-flop acts as the
with the clock, hence its design input of the next flip-flop, hence its
Complexity
and implementation is complex design and implementation is quite
as compared to that of an simple.
asynchronous counter.

A Synchronous counter can be An Asynchronous counter can

operated in any desired count operate only in a fixed count
Sequence sequence, as it could get sequence, i.e., UP and DOWN.
manipulated by changing the
clock sequence.

There is no propagation delay In case of asynchronous counters,

Delay observed in case of there is a subsequent propagation
Synchronous Counters. delay from one flip-flop to another.
6. Design Mod-10/Decade/BCD counter using T flip flop
Step 1 : Decision for number of flip-flops –
Example : If we are designing mod N counter and n number of flip-flops are required then n can
be found out by this equation.
N <= 2n
Here we are designing Mod-10 counter Therefore, N= 10 and number of Flip flops(n) required is
For n=3, 10<=8, which is false.
For n= 4, 10<=16, which is true.

Therefore number of FF required is 4 for Mod-10 counter.

Step 2 : Write excitation table of Flip flops –
Here T FF is used

Excitation table of T FF.

Step 3 : Draw state diagram and circuit excitation table –

Counting Sequence of Decade counter

A decade counter is called as mod -10 or divide by 10 counter. It counts from 0 to 9 and again
reset to 0. It counts in natural binary sequence. Here 4 T Flip flops are used. It resets after
Q3 Q2 Q1 Q0 = 1001.

Circuit excitation table –

Here Q3 Q2 Q1 Q0 are present states of four flip-flops and Q*3 Q*2 Q*1 Q*0 are next counting
state of 4 Flip flops. If there is a transition in current state i.e if Q3 value changes from 0 to 1 or
1 to 0 then there’s corresponding T(toggle) bit is written as 1 otherwise 0.
 Circuit excitation table

Step 4 : Create Karnaugh map for each FF input in terms of flip-flop outputs as the input
variable –
Simplify the K map –
 K map for finding minimal expressions.

Step 5 : Create circuit diagram –

Here negative edge triggered clock is used for toggling purpose.
 The clock is provided to every Flip flop at same instant of time.
 The toggle(T) input is provided to every Flip flop according to the simplified equation of K
map.
7. Conversion of Flip Flops

 SR Flip Flop to JK Flip Flop

As told earlier, J and K will be given as external inputs to S and R. As shown in the
logic diagram below, S and R will be the outputs of the combinational circuit.
The truth tables for the flip flop conversion are given below. The present state is represented by
Qp and Qp+1 is the next state to be obtained when the J and K inputs are applied.
For two inputs J and K, there will be eight possible combinations. For each
combination of J, K and Qp, the corresponding Qp+1 states are found. Qp+1
simply suggests the future values to be obtained by the JK flip flop after the value
of Qp. The table is then completed by writing the values of S and R required to get
each Qp+1 from the corresponding Qp. That is, the values of S and R that are
required to change the state of the flip flop from Qp to Qp+1 are written.

SR
JK Flip Flop to SR Flip Flop
This will be the reverse process of the above explained conversion. S and R will be
the external inputs to J and K. As shown in the logic diagram below, J and K will be
the outputs of the combinational circuit. Thus, the values of J and K have to be
obtained in terms of S, R and Qp. The logic diagram is shown below.

A conversion table is to be written using S, R, Qp, Qp+1, J and K. For two inputs, S
and R, eight combinations are made. For each combination, the corresponding
Qp+1 outputs are found ut. The outputs for the combinations of S=1 and R=1 are
not permitted for an SR flip flop. Thus the outputs are considered invalid and the J
and K values are taken as “don’t cares”.
 SR Flip Flop to D Flip Flop
As shown in the figure, S and R are the actual inputs of the flip flop and D is the
external input of the flip flop. The four combinations, the logic diagram, conversion
table, and the K-map for S and R in terms of D and Qp are shown below.

D Flip Flop to SR Flip Flop

D is the actual input of the flip flop and S and R are the external inputs. Eight possible
combinations are achieved from the external inputs S, R and Qp. But, since the combination of
S=1 and R=1 are invalid, the values of Qp+1 and D are considered as “don’t cares”. The logic
diagram showing the conversion from D to SR, and the K-map for D in terms of S, R and Qp are
shown below.
JK Flip Flop to T Flip Flop
J and K are the actual inputs of the flip flop and T is taken as the external input for
conversion. Four combinations are produced with T and Qp. J and K are expressed
in terms of T and Qp. The conversion table, K-maps, and the logic diagram are
given below.

JK Flip Flop to D Flip Flop

D is the external input and J and K are the actual inputs of the flip flop. D and Qp
make four combinations. J and K are expressed in terms of D and Qp. The four
combination conversion table, the K-maps for J and K in terms of D and Qp, and
the logic diagram showing the conversion from JK to D are given below.
 D Flip Flop to JK Flip Flop
In this conversion, D is the actual input to the flip flop and J and K are the external
inputs. J, K and Qp make eight possible combinations, as shown in the conversion
table below. D is expressed in terms of J, K and Qp.

The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram
showing the conversion from D to JK are given in the figure below.
 Unit 5
1. Explain the characteristics of the digital logic family
Propagation delay
It is the time interval between the application of the input pulse and the occurrence of the output.
It is an important characteristic of the digital logic family. If the propagation delay is less, then
the speed at which the IC operates will be faster.

Let THL is the propagation delay when the output changes from logic 0 to 1 and TLH is the delay
when the output changes from logic 1 to 0. The maximum value of THL and TLH is considered as
the propagation delay for that logic gate.

Fan in and Fan out

Fan-in refers to the number of inputs in a digital logic gate family. For the example given in the
figure below, the EX-OR gate has three inputs. So fan-in for the given EX-OR gate is 3.

Fan-out refers to the number of inputs that is driven by the output of another logic gates. For
example, the following circuit has an EX-OR gate, which drives 4 NOT gates. So fan-out of EX-
OR gate is 4.

Both fan-in and fan-out values are given by the manufacturer at the time of designing and the data
is specified in the datasheet. When the number of inputs or outputs are changed, it may cause some
malfunction to the device.

Power dissipation
It is the amount of power that the digital circuit dissipates. The power dissipated is determined by
the average current, that is drawn from the supply voltage.

The average current is the average value of the current at LOW gate output(logic ‘o’) and the
current at HIGH gate output (logic ‘1’).

Noise Immunity and Noise margin

In digital logic circuits, the binary values 0 and 1 represent the LOW and HIGH voltage levels.
Due to the interference of the noises, the voltage levels may increase or decrease. This may lead
to the wrong operation of the device.

The noise immunity is the ability of the logic device to tolerate the noise without causing spurious
change to the output voltage. Noise margin allows the logic device to function properly within the
specified limits.

Figure of merit
The figure of merit or Speed Power Product is a common means of measuring the performance of
circuits in the digital logic family.
2. What is tri state logic. Explain trisatate TTL inverter
3. Draw and explain CMOS as an Inverter
The term “CMOS” stands for “complementary-symmetry metal–oxide–semiconductor. CMOS is
a type of MOSFET, where its fabrication process uses complementary & symmetrical P-type &
N-type MOSFET pairs for logic functions.

A basic inverter circuit is used to accomplish a logic variable by complementing from A to A’.
So, a CMOS inverter is a very simple circuit, designed with two opposite-polarity MOSFETs
within a complementary way.

CMOS Inverter Symbol & Truth Table

The CMOS inverter truth table is shown above. If the input logic is zero (0) then the output will
be high (1) whereas, if the input logic is one (1), then the output will be low (0).

CMOS Inverter Circuit

CMOS inverter structure is the combination of both the PMOS & NMOS transistors where the
pMOS is arranged at the top & nMOS is arranged at the bottom. The NMOS transistor is
connected at the drain (D) & gate (G) terminals, a voltage supply (VDD) is connected at the
source terminal of PMOS & a GND terminal is connected at the source terminal of NMOS. Input
voltage (Vin) is connected to both the gate terminals of transistors & output voltage (Vout) is
connected to the drain (D) terminals of the transistor.
The working of CMOS inverter is the same as other types of FETs except depends on an oxygen
layer to divide electrons within the gate & semiconductor. They are designed with a power
supply, input voltage terminal, output voltage, gate, drain, and PMOS & NMOS transistors
which are connected to the gate & the drain terminals.
When the low input voltage is given to the CMOS inverter, then the PMOS transistor is switched
ON whereas the NMOS transistor will switch OFF by allowing the flow of electrons throughout
the gate terminal & generating high logic output voltage.
Similarly, when the high input voltage is given to the CMOS inverter then, the PMOS transistor
is switched OFF whereas the NMOS transistor will be switched ON avoiding as many electrons
from attaining the output voltage & generating low logic output voltage.
Thus, direct current supplies from the supply voltage (VDD) to the output voltage (Vout) & the
load capacitor (CL) can be charged and shows that Vout = VDD. As a result, the above circuit
works like an inverter

4. What are the differences between SRAM and DRAM? Explain in details.

SRAM DRAM

It stores information as long as the power

It stores information as long as the power is is supplied or a few milliseconds when
supplied. power is switched off.

Transistors are used to store information in Capacitors are used to store data in
SRAM. DRAM.

To store information for a longer time,

Capacitors are not used hence no refreshing is contents of the capacitor need to be
required. refreshed periodically.

SRAM is faster compared to DRAM. DRAM provides slow access speeds.

It does not have a refreshing unit. It has a refreshing unit.

 SRAM DRAM

These are expensive. These are cheaper.

SRAMs are low-density devices. DRAMs are high-density devices.

In this bits are stored in the form of

In this bits are stored in voltage form. electric energy.

These are used in cache memories. These are used in main memories.

Uses more power and generates more

Consumes less power and generates less heat. heat.

5. Explain ROM and its types

ROM, which stands for Read Only Memory, stores the instructions required to start a
computer. It is a nonvolatile memory. Therefore, the data remains even when there is no
continuous power flow. In other words, the data is permanent. PROM, EPROM and EEPROM
are some types of ROM.

The main difference between PROM EPROM and EEPROM is that PROM is
programmable only once while EPROM is reprogrammable using ultraviolet light and
EPROM is reprogrammable using an electric charge.

PROM stands for Programmable Read Only Memory. It is a computer memory chip, and it
is possible to program it once after creation. After programming the PROM, the information
we write to it becomes permanent. Therefore, we cannot erase or delete that written data. The
PROM chip was commonly used in earlier computers’ BIOS systems. After creating PROM,
all the bits are ‘1’. If a certain bit should be 0, we can make that 0 by burning. One major
drawback of PROM is that it is not possible to update it. In other words, we cannot reprogram
it. Instead, we have to discard that and replace it with a new chip.

EPROM stands for Erasable Programmable Read Only Memory. We can erase and
reprogram an EPROM without replacing it. It is possible to erase and write to it by exposing
the memory chip to ultraviolet light. Moreover, it is easier to recognize EPROM via
transparent fused quartz window in the top of the package.

EPROM is used more commonly than PROM because it allows the manufacturers to modify or
reprogram the chip.
EEPROM stands for Electrically Erasable Programmable Read-Only Memory. It is a
memory chip that we can erase and reprogram using electrical charge. It consists of a
collection of floating gate transistors. The flash memory is a type of EEPROM which has a
higher density and lower number of write cycles.

EEPROM is a replacement of both PROM and EPROM. It is used in many applications

including computers, microcontrollers, smart cards, etc. to store data, erase and to reprogram.

PROM is a Read Only Memory (ROM) that can be modified only once by a user while
EPROM is a programmable ROM that can be erased and reused. EEPROM, on the other hand,
is a user-modifiable ROM that can be erased and reprogrammed repeatedly through a normal
electrical voltage. Thus, this is the main difference between PROM EPROM and EEPROM.

6. Give the comparison of TTL CMOS and ECL logic family

7. Explain the operation of ECL NOR GATE:

If one of the input or all the input are high then the output is low because one or more transistor
conducts. Output is high when all input is low
ECL is the fastest among all logic families.The basic component is current switch or difference
amplifier with out-of phase output . This reason ECL is known as Current Mode Logic(CML).
Transistor operates on Non- saturated at limited collector current, so the emitter coupling is used,
it doesn't allow transistor to saturate.
Advantages
[1] So switching speed is high,
[2] Propagation delay is >3ns and
[3] High Fan – in & out.

Disadvanteges
[1] Highest power dissipation
[2] additional reference voltage source. so it is used in Superfast computing.
 Unit 6
State diagram
The state diagram is the pictorial representation of the behavior of sequential circuits. It
clearly shows the transition of states from the present state to the next state and output for a
corresponding input.

 In this diagram, each present state is represented inside a circle.

 The transition from the present state to the next state is represented by a directed line
connecting the circles.
 If the directed line connects the circle itself, which indicates that there is no change in the
state(the next state is the same as the present state).
 For mealy model, the directed line is labeled with binary numbers separated with ‘/’, as
shown in the below diagram.
 The input value, which causes the transition to occur is labeled first ‘1/’. The output
produced for the corresponding input is labeled second ‘/0’.

 For Moore circuit, the directed lines are labeled with only one binary number. It is
nothing but the input value which causes the transition.
 The output value is indicated inside the circle below the present state. It is because, in
Moore model, the output depends on the present state but not on the input.

State table

The information contained in the state diagram is transformed into a table called a state
table or state synthesis table. Although the state diagram describes the behavior of the sequential
circuit, in order to implement it in the circuit, it has to be transformed into the tabular form.

The below table shows the state table for Mealy state machine model. As you can see, it has the
present state, next state and output. The present state is the state before the occurrence of the clock
pulse.
After the application of the clock pulse, depending on the input(X = 0 or 1), the state changes. It
is indicated in the ‘next state’ column. The output produced for each input is represented in the
last column.

State reduction

While designing a sequential circuit, it is very important to remove the redundant states. The
removal of redundant states will reduce the number of flip flops and logic gates, thereby reducing
the cost and size of the sequential circuit.

When two states are said to be redundant?

The two states are said to be redundant if the output and the next state produced for each and every
input are the same. In that case, one of the redundant states can be removed without altering the
input-output relationship. This method is called the state elimination method
Example Problem #1
Determine the reduced state table for the given state table.

The given table contains the present state, next state and output produced for inputs X = 0 and 1.
To find the reduced state table, the first step is to find the redundant/equivalent states from the
given state table.

As explained above, any two states are said to be equivalent, if their next state and output are the
same. In order to check that, compare each present state with the other.

First, consider the present state ‘a’, compare its next state and output with the other present states
one by one. In this comparison, none of the present states is the same as the present state ‘a’.

Now, consider the next present state ‘b’ and compare it with other present states. While doing so,
you can find the next state and the output of the present state ‘e’ is the same as that of ‘b’. They
are marked as equivalent states as shown below.

Similarly, consider the other present states and compare them with other states for redundancy.

The next step is to replace the redundant states with the equivalent state. Here we have found,
states b and e are redundant. Replace e by b and remove the state e.
Example Problem #2
Determine the reduced state diagram for the given state diagram.

To construct the reduced state diagram, first, build the state table for the given state diagram, find
the equivalent states, remove the redundant state, draw the reduced state table and finally construct
the state diagram.

First, the information in the state diagram is transferred into the state table as shown below.
Thus ‘a’ and ‘d’ are found as equivalent states. So, replace ‘d’ by ‘a’ and remove ‘d’. Now, the
reduced state table will become as below.

The state diagram is constructed for the reduced state table as shown below.