Embedded Systems VOL. 3: Real-Time Operating Systems for ARM Cortex-M Microcontrollers Jonathan Valvano download
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3: Real-Time Operating
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EM BED D ED SY STEM S:
REAL-TIME OPERATING SYSTEMS FOR
ARM CORTEX-M MICROCONTROLLERS
Volume 3
Fourth Edition,
January 2017
Jonathan W. Valvano
Fourth edition
January 2017
ARM and uVision are registered trademarks of ARM Limited.
Cortex and Keil are trademarks of ARM Limited.
Stellaris and Tiva are registered trademarks Texas Instruments.
Code Composer Studio is a trademark of Texas Instruments.
All other product or service names mentioned herein are the trademarks of their respective
owners.
In order to reduce costs, this college textbook has been self-published. For more
information about my classes, my research, and my books, see
http://users.ece.utexas.edu/~valvano/
The overall objective of this book is to teach the design of real-time operating
systems for embedded systems. We define a system as real time if there is a
small and bounded delay between the time when a task should be completed
and when it is actually completed. We will present both fundamental principles
and practical solutions. Interfacing to the microcontroller was presented in
detail in Volume 2 and reviewed in the first two chapters of this book. The
overlap allows this book to stand alone as a text to teach embedded real time
operating systems. This first chapter will review the architecture of the Texas
Instruments MSP432/TM4C family of microcontrollers. When designing
operating systems, we need to understand the details of the architecture. In
particular, we must perform many functions in assembly language. Furthermore,
managing memory will require an intimate understanding of how the processor
accesses memory at the most basic level.
1.1. Introduction to Real-Time Operating Systems
The RTOS must manage resources like memory, processor and I/O. The RTOS will
guarantee strict timing constraints and provide reliable operation. The RTOS will
support synchronization and communication between tasks. As complex systems are
built the RTOS manages the integration of components. Evolution is the notion of a
system changing to improve performance, features and reliability. The RTOS must
manage change. When designing a new system, it is good design practice to build a
new system by changing an existing system. The notion of portability is the ease at
which one system can be changed or adapted to create another system.
The response time or latency is the delay from a request to the beginning of the
service of that request. There are many definitions of bandwidth. In this book we
define bandwidth as the number of information bytes/sec that can be transferred or
processed. We can compare and contrast regular operating systems with real-time
operating systems.
Regular OS Real-time OS
Complex Simple
Best effort Guaranteed response
Fairness Strict timing constraints
Average bandwidth Minimum and maximum
limits
Unknown components Known components
Unpredictable behavior Predictable behavior
Plug and play Upgradable
Table 1.1. Comparison of regular and real-time operating systems.
From Table 1.1 we see that real-time operating systems have to be simple so they may be
predictable. While traditional operating systems gauge their performance in terms of
response time and fairness, real-time operating systems target strict timing constraints and
upper, lower bounds on bandwidth. One can expect to know all the components of the
system at design time and component changes happen much more infrequently.
Checkpoint 1.1: What does real time mean?
1.2.2. Memory
One kibibyte (KiB) equals 1024 bytes of memory. The TM4C123 has 256 kibibytes
(218 bytes) of flash ROM and 32 kibibytes (215 bytes) of RAM. The MSP432 also has
256 kibibytes (218 bytes) of flash ROM but has 64 kibibytes (216 bytes) of RAM. We
view the memory as continuous virtual address space with the RAM beginning at
0x2000.0000, and the flash ROM beginning at 0x0000.0000.
The microcontrollers in the Cortex-M family differ by the amount of memory and by
the types of I/O modules. There are hundreds of members in this family; some of them
are listed in Table 1.2. The memory maps of TM4C123 and MSP432 are shown in
Figure 1.7. Although this course focuses on two microcontrollers from Texas
Instruments, all ARM Cortex-M microcontrollers have similar memory maps. In
general, Flash ROM begins at address 0x0000.0000, RAM begins at 0x2000.0000,
the peripheral I/O space is from 0x4000.0000 to 0x5FFF.FFFF, and I/O modules on
the private peripheral bus exist from 0xE000.0000 to 0xE00F.FFFF. In particular, the
only differences in the memory map for the various members of the Cortex-M family
are the ending addresses of the flash and RAM.
Part number RAM Flash I/O I/O modules
MSP432P401RIPZ 64 256 84 floating point, DMA
TM4C123GH6PM 32 256 43 floating point, CAN, DMA,
USB, PWM
TM4C1294NCPDT 256 1024 90 floating point, CAN, DMA,
USB, PWM, Ethernet
STM32F051R8T6 8 64 55 DAC, Touch sensor, DMA,
I2S, HDMI, PWM
MKE02Z64VQH2 4 64 53 PWM
KiB KiB pins
Table 1.2. Memory and I/O modules (all have SysTick, RTC, timers, UART, I2C, SSI, and
ADC).
Having multiple buses means the processor can perform multiple tasks in parallel.
On the TM4C123, general purpose input/output (GPIO) ports can be accessed using
either the PPB or AHPB. The following is some of the tasks that can occur in parallel
ICode bus Fetch opcode from ROM
DCode bus Read constant data from ROM
System bus Read/write data from RAM or I/O, fetch opcode from RAM
PPB Read/write data from internal peripherals like the NVIC
AHPB Read/write data from internal peripherals like the USB
Instructions and data are accessed using a common bus on a von Neumann machine.
The Cortex-M processor is a Harvard architecture because instructions are fetched
on the ICode bus and data accessed on the system bus. The address signals on the
ARM Cortex-M processor include 32 lines, which together specify the memory
address (0x0000.0000 to 0xFFFF.FFFF) that is currently being accessed. The
address specifies both which module (input, output, RAM, or ROM) as well as
which cell within the module will communicate with the processor. The data signals
contain the information that is being transferred and also include 32 bits. However,
on the system bus it can also transfer 8-bit or 16-bit data. The control signals specify
the timing, the size, and the direction of the transfer.
Figure 1.7. Memory map of the TM4C123 with 256k ROM and 32k RAM and
the MSP432 with 256k ROM and 64k RAM.
Checkpoint 1.6: What do we put in RAM and what do we put in ROM?
Checkpoint 1.7: Can software write into the ROM of our microcontroller?
The ARM Cortex-M processor uses bit-banding to allow read/write access to
individual bits in RAM and some bits in the I/O space. There are two parameters that
define bit-banding: the address and the bit you wish to access. Assume you wish to
access bit b of RAM address 0x2000.0000+n, where b is a number 0 to 7. The
aliased address for this bit will be
0x2200.0000 + 32*n + 4*b
Reading this address will return a 0 or a 1. Writing a 0 or 1 to this address will
perform an atomic read-modify-write modification to the bit.
If we consider 32-bit word-aligned data in RAM, the same bit-banding formula still
applies. Let the word address be 0x2000.0000+n. n starts at 0 and increments by 4.
In this case, we define b as the bit from 0 to 31. In little-endian format, bit 1 of the
byte at 0x2000.0001 is the same as bit 9 of the word at 0x2000.0000.The aliased
address for this bit will still be
0x2200.0000 + 32*n + 4*b
Examples of bit-banded addressing are listed in Table 1.3. Writing a 1 to location
0x2200.0018 will set bit 6 of RAM location 0x2000.0000. Reading location
0x2200.0024 will return a 0 or 1 depending on the value of bit 1 of RAM location
0x2000.0001.
RAM Offset Bit b Bit-banded
address n alias
0x2000.0000 0 0 0x2200.0000
0x2000.0000 0 1 0x2200.0004
0x2000.0000 0 2 0x2200.0008
0x2000.0000 0 3 0x2200.000C
0x2000.0000 0 4 0x2200.0010
0x2000.0000 0 5 0x2200.0014
0x2000.0000 0 6 0x2200.0018
0x2000.0000 0 7 0x2200.001C
0x2000.0001 1 0 0x2200.0020
0x2000.0001 1 1 0x2200.0024
Table 1.3. Examples of bit-banded addressing.
Checkpoint 1.8: What address do you use to access bit 3 of the byte at
0x2000.1010?
Checkpoint 1.9: What address do you use to access bit 22 of the word at
0x2001.0000?
The other bit-banding region is the I/O space from 0x4000.0000 through
0x400F.FFFF. In this region, let the I/O address be 0x4000.0000+n, and let b
represent the bit 0 to 7. The aliased address for this bit will be 0x4200.0000 + 32*n
+ 4*b
Checkpoint 1.10: What address do you use to access bit 7 of the byte at
0x4000.0030?
1.3. Cortex-M Processor Architecture
1.3.1. Registers
The registers on an ARM Cortex-M processor are depicted in Figure 1.8. R0 to R12
are general purpose registers and contain either data or addresses. Register R13
(also called the stack pointer, SP) points to the top element of the stack. Actually,
there are two stack pointers: the main stack pointer (MSP) and the process stack
pointer (PSP). Only one stack pointer is active at a time. In a high-reliability
operating system, we could activate the PSP for user software and the MSP for
operating system software. This way the user program could crash without disturbing
the operating system. Most of the commercially available real-time operating systems
available on the Cortex M will use the PSP for user code and MSP for OS code.
Register R14 (also called the link register, LR) is used to store the return location for
functions. The LR is also used in a special way during exceptions, such as interrupts.
Register R15 (also called the program counter, PC) points to the next instruction to
be fetched from memory. The processor fetches an instruction using the PC and then
increments the PC by the length (in bytes) of the instruction fetched.
Checkpoint 1.11: How are registers R13 R14 and R15 special?
Figure 1.9. The program status register of the ARM Cortex-M processor.
The N, Z, V, C, and Q bits signify the status of the previous ALU operation. Many
instructions set these bits to signify the result of the operation. In general, the N bit is
set after an arithmetical or logical operation signifying whether or not the result is
negative. Similarly, the Z bit is set if the result is zero. The C bit means carry and is
set on an unsigned overflow, and the V bit signifies signed overflow. The Q bit is the
sticky saturation flag, indicating that “saturation” has occurred, and is set by
the SSAT and USAT instructions.
The T bit will always be 1, indicating the ARM Cortex-M processor is executing
Thumb instructions. The ICI/IT bits are used by interrupts and by IF-THEN
instructions. The ISR_NUMBER indicates which interrupt if any the processor is
handling. Bit 0 of the special register PRIMASK is the interrupt mask bit, or I bit. If
this bit is 1 most interrupts and exceptions are not allowed. If the bit is 0, then
interrupts are allowed. Bit 0 of the special register FAULTMASK is the fault mask
bit. If this bit is 1 all interrupts and faults are disallowed. If the bit is 0, then
interrupts and faults are allowed. The nonmaskable interrupt (NMI) is not affected by
these mask bits. The BASEPRI register defines the priority of the executing
software. It prevents interrupts with lower or equal priority from interrupting the
current execution but allows higher priority interrupts. For example if BASEPRI
equals 3, then requests with level 0, 1, and 2 can interrupt, while requests at levels 3
and higher will be postponed. The details of interrupt processing will be presented in
detail, later in the book.
Checkpoint 1.12: Where is the I bit and what does it mean?
1.3.2. Stack
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