Module-2

Syllabus: Addressing Modes: Introduction, Instruction syntax, Data types, Subroutines,

Addressing modes, 8051 instructions: Data transfer instructions, Arithmetic instructions,
Logical instructions, Branch instructions, Bit manipulation instruction. Simple assembly
language programming

2.1 The general structure of an 8051 instruction

The general structure of the instruction of 8051 is as follows:

Label: mnemonic operand/s ; comments

• The label allows the program to access a line of code by a name. All labels must
start with an alphabetic character and end with a colon.
Example
BACK: add A, B ; the word BACK is a label.

• The mnemonic specifies the actual instruction to the microcontroller.

Example
MOV A, B ; the keyword MOV is the mnemonic.

• The operand/s indicates the parameters on which the mnemonic operates.

Example
mov A, B ;A and B are the operands.

• The comment field is used to describe the program. With the help of the comment
lines the programmer can easily interpret what each instruction does. Comment field
begins with a semicolon. Comments can be written at the end of a line or on a new
line. Comments are ignored by the assembler and are not executed.

Example
ADD A, R5 ; add contents of register R5 to accumulator.

Note: The label and the comment fields are optional.

Length of an instruction:

The instructions written in assembly language are translated into a machine code known as
opcode (operational code) to be executed by the CPU. Depending upon the number of
bytes present in each instruction in the machine language, the instructions are classified
into three categories: is translated to, we have

1-byte instruction
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2-byte instruction
3-byte instruction

• 1-byte instruction: An instruction which has only the mnemonic and the operands
will result in a 1-byte instruction.
Example: mov A, B

• 2-byte instruction: An instruction which has a mnemonic along with an 8 bit

data/address explicitly specified will result in a 2-byte instruction.
Example: mov A, #05H
mov A, 50H
• 3-byte instruction: An instruction which has a mnemonic along with a 16 bit
data/address explicitly specified
Example: mov DPTR, #8000H
LJMP 2AB5H

2.2 8051 Addressing Modes

Any instruction will contain an opcode that specifies the nature of operation to be performed
and a set of operands on which the required operation is performed. The instruction can
have two operands called destination operand and a source operand.

The various ways by which the destination and source operand/s of an instruction
are specified are called addressing modes.

The 8051 has following addressing modes.

1. Immediate addressing mode.
2. Register addressing mode/ Bank addressing mode.
3. Direct addressing mode.
4. Indirect addressing mode.
5. Indexed addressing mode.
6. Relative addressing mode.
7. Absolute addressing mode.
8. Long addressing mode.
9. Bit direct addressing mode.
10. Bit inherent addressing mode.

1. Immediate addressing mode:

In this addressing mode, the source operand is a constant. As the name implies, in this
addressing mode, the data is immediately available after the opcode in the instruction. The
symbol ‘#’ is used to specify immediate addressing mode.
Example:
• MOV A, #56H
• ADD A, #15
• MOV DPTR, #8000H

2. Register addressing/ Bank addressing mode:

In this addressing mode, the names of registers are used as a part of instruction to access
the data stored in them. Registers A, DPH, DPL and R0-R7 (of current register bank) may be
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used as a part of the instruction. The selection of a register bank is decided by two bits
(RS1 and RS0) of the Program Status Word (PSW) register.
Example:
• MOV A, R1

3. Direct addressing mode:

In this addressing mode, the address of a memory location is explicitly specified in the
instruction. All 128 bytes of internal RAM and SFR’s can be addressed directly using the byte
addresses assigned to each.
Example:
• MOV A, 40H
• MOV R0, 80H

4. Indirect addressing mode:

In this addressing mode, a memory Pointer register (either R0 OR R1) is used to hold the 8
bit address of an Internal RAM memory location that is used to access data. The mnemonic
symbol ‘@’ is used to specify indirect addressing mode.
Example:
• MOV A, @R0
• MOV @R1, A

Note: In case of external data memory access, either R0 OR R1(256 bytes)/ DPTR(64KB) is
used as memory pointer register.
Example:
• MOVX A, @R0
• MOVX A, @DPTR

5. Indexed addressing mode:

This addressing mode is used to access data elements of ‘look-up table’ located in the
Program memory (ROM). In this addressing mode either the program counter(PC) register
or the data pointer (DPTR) register is used to hold the base address of the table and the
accumulator is used to hold the table entry number(Index). The 16-bit address of the table
entry in program memory is then formed by adding the accumulator data to the base
address in either PC or DPTR.
Example:
• MOVC A, @A+DPTR
• MOVC A, @A+PC

6. Relative addressing mode:

This addressing mode is used with certain jump instructions. The relative address, often
referred to as an offset, is an 8 bit signed number, which is automatically added to the
Program counter (PC) register to make the address of the next instruction. The 8 bit signed
offset value gives an address range of +127 to -128 locations.

Example:
• SJMP 50H
• JC 20H

7. Absolute addressing mode:

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In this addressing mode a jump or a call can be made only within 2KB memory space
This addressing mode is used only by the AJMP and ACALL instructions.
The program memory of 64KB is divided into 32 pages and the size of each page is 2KB.
For any page the address boundary is such that the most significant 5 bits of the address
will be the same and the least significant 11 bits of the address will change. Therefore, the
absolute addressing will determine only the least significant 11 bits of the program counter.
Example:
• AJMP 5789H
• ACALL 5789H

8. Long addressing mode:

The long addressing within the 8051 is used only with the instructions LJMP and LCALL. The
address specifies a full 16 bit destination address so that a jump or a call can be made to a
location within a 64KB code memory space.
Example:
• LJMP 1234H
• LCALL 1234H

9. Bit direct addressing mode:

Some of the 8051 instructions accesses one bit of data of a register instead of the entire 8
bit data of the register. Such instructions are said to have bit addressing mode.
In bit direct addressing, the address of the bit is directly specified in the instruction.
Example:
• CLR b
• CPL b
• SETB b

10. Bit inherent addressing mode

In bit inherent addressing mode it is implied that the specified bit is a carry bit.
Example:
• CLR C
• SETB C
• CPL C

2. 3 INSTRUCTION SET

Instruction set of the 8051 microcontroller can be classified, based on the function they
perform into the following 5 categories.

1. Data Transfer Instructions

2. Arithmetic Instructions
3. Logical Instructions
4. Boolean Variable manipulation Instructions
5. Program Branching Instructions

1) Data Transfer Instructions:

These instructions deal with transferring (copying) the data from source to destination.

The general form of Move instruction is:

MOV destination, source

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Where the destination and the source can either be a register or a memory location.
The various forms of Move instruction are:

MOV Rn, A MOV addr, A MOV @RP, A

MOV A, Rn MOV addr, Rn
MOV A, addr MOV Rn, addr MOV addr, addr MOV @RP, addr
MOV A, #D8 MOV Rn, #D8 MOV addr, #D8 MOV @RP,#D8
MOV A, @RP MOV addr, @RP

a) MOV A ,Rn

Operation Addressing mode Memory space

Copy the contents of Register addressing mode. 1 byte
register Rn (of the current
register bank) into the
accumulator.

(A) (Rn)

Example: MOV A , R2 ; copy the contents of register R2 into the accumulator.

Before execution After execution

A 20H A 45H

R2 45H R2 45H

b) MOV A ,addr

Operation Addressing mode Memory space

Copy the contents of the Direct addressing mode. 2 bytes
internal RAM address
(addr) into the destination
register.

(A) (addr)

Example: MOV A , 30H ; copy the contents of RAM location with address 30H into the
accumulator.
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Before execution After execution

A 20H A 45H

30H 45H 30H 45H

Internal
Internal
RAM
RAM
c) MOV A ,#D8

Operation Addressing mode Memory space

Copy the immediate 8-bit Immediate addressing 2 bytes
data into the destination. mode.

(A) D8

Example: MOV A , #45H ; copy the 8 bit data (45H) into the accumulator

Example: MOV A , #45H

20H 45H

d) MOV A ,@Rp

Operation Addressing mode Memory space

Copy the contents of the Indirect addressing mode. 1 byte
internal RAM location into
the Accumulator. The
address of RAM location
is present in register Rp.
Rp can be either R1 or R0.

(A) ((Rp))
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Example: MOV A ,@R0 ;

Before execution After execution

A 20H A 45H

R0 40H R0 40H

40H 40H
45H 45H

Internal
Internal
RAM
RAM

Additional type of MOV instructions:

MOVX A, @R0 1 6-BIT data transfer

MOVX A, @R1 MOV DPTR, #NN
MOVX A, @ DPTR MOV DPTR,#NN
MOVX @R0, A
MOVX @R1, A
MOVX @ DPTR, A

➢ External Data Moves:

RAM and ROM can be expanded by adding external memory chips to the 8051
microcontroller. The external memory can be as large as 64KB for each of the RAM and
ROM memory areas. Instructions that access this external memory always use indirect
addressing mode.
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NOTE: All external data moves must use the accumulator.

The various instructions are

a) MOVX A ,@Rp b) MOVX A ,@DPTR c) MOVX @Rp ,A d) MOVX @DPTR, A

a) MOVX A ,@Rp

Operation Addressing mode Memory space

Copy the contents of Indirect addressing mode. 1 byte
external RAM location into
the accumulator. The
address of RAM location is
present in register Rp. Rp
can be either R1 or R0.

(A) ((Rp)

Example: MOVX A ,@R1

Before execution After execution

A 20H A 45H

60H R1
60H

R1 45H 45H
60H R1 60H

External External
RAM RAM

b) MOVX A ,@DPTR

Operation Addressing mode Memory space

Copy the contents of Indirect addressing mode. 1 byte
external RAM address stored
in register DPTR into the
accumulator.

(A) ((DPTR))
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Example: MOVX A ,@DPTR ;
Before execution After execution

A A
20H 45H

DPTR 80 00H DPTR 8000H

8000H 45H DPTR 8000H 45H

External RAM External RAM

➢ Code Memory (Read-Only) Data Moves:

MOVC A, @A+PC
MOVC A, @A+DPTR

The data can also be stored in the program ROM. Access to this data is made possible by
using indirect addressing and the accumulator in conjunction with the PC or the DPTR as
shown.

a) MOVC A , @A+DPTR

Operation Addressing mode Memory space

Copy the code byte, found at Indexed addressing mode. 1 byte
the ROM into accumulator.
The address is formed by
adding contents of
accumulator and the DPTR

Example: MOVC A ,@A+DPTR

Before execution After execution

A 20H A 45H

DPTR 80 00H DPTR 80 00H

8020H 45H 8020H 45H

ROM ROM
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b) MOVC A ,@A+PC

Operation Addressing mode Memory space

Copy the code byte, found at Indexed addressing mode. 1 byte
the ROM into accumulator.
The address formed by
adding the content of PC and
accumulator.

Example: MOVC A, @A+PC

Before execution After execution

A A 45H
20H

PC PC 5000H
5000H

5020H 45H 5020H 45H

ROM ROM
➢ Data Exchanges:
Various forms of MOV, PUSH and POP instructions transfer the data in a single direction i,e.
from source to destination, leaving the source unaltered. Exchange instructions move the
data in two directions i,e. from source to destination and vice-versa.

The various forms of exchange instructions are:

a) XCH A ,Rn
b) XCH A ,addr
c) XCH A ,@Rp
d) XCHD A ,@Rp (exchange digits)

Flags affected: none

a) XCH A ,Rn
Operation Addressing mode Memory space
Exchange data bytes Register addressing mode 1 byte
between the accumulator
and the register Rn(of
current register bank)
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Example: XCH A , R4 ; exchange bytes between register R4 and the Accumulator.

Before execution After execution

A 0BH
20H A 06H
45H

R4 R4
45H 20H

b) XCH A , addr
Operation Addressing mode Memory space
Exchange data bytes Direct addressing mode 2 bytes
between the accumulator
and the direct memory
address(addr)

Example: XCH A, 30H; exchange the contents of the Accumulator and the memory
location(70H).

Before execution After execution

A 20H A 45H

Int RAM Int RAM

30H 45H 30H 20H

c) XCH A ,@Rp
Operation Addressing mode Memory space
Exchange data bytes Indirect addressing mode 1 byte
between the accumulator
and the memory location
whose address is in register
Rp. Rp can be either R0 or
R1.
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Example: XCH A , @R0 ; exchange the contents of the accumulator and the memory
location whose address is in register R0.

Before execution After execution

A 20H A 45H

R0 40H R0 40H

40H 45H R0 40H 20H

Internal RAM Internal RAM

d) XCHD A ,@Rp
Operation Addressing mode Memory space
Exchange the lower nibble in Indirect addressing mode 1 byte
the accumulator along with
the lower nibble of the RAM
memory location pointed by
Rp. Rp can be either R0 or
R1. Upper nibbles are
unaltered

Example: XCHD A , @R0

Before execution After execution

A 6 2H A 6 5H

R0 40H R0 40H

40H 7 5H 40H 7 2H

Internal RAM Internal RAM

Note:

▪ All exchanges are internal to the 8051.

▪ All exchanges use the accumulator.
▪ In XCHD, only the lower nibbles are exchanged and the upper nibbles does not change.
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Arithmetic Instructions:

These instructions perform mathematical calculations on data as per the requirement.

The various arithmetic operations performed in 8051 are:

➢ Incrementing and Decrementing operations:

These instructions increment or decrement the contents of the destination by one.

The general form of the instruction is:

INC destination

DEC destination

Where the destination can be either a register or a memory location.

The various forms of increment and decrement instructions are:

Increment Instructions Decrement Instructions

INC A DEC A
INC Rn DEC Rn
INC addr DEC addr
INC @Rp DEC @Rp
INC DPTR

Flags affected: none

a) INC A
Operation Addressing mode Memory space
Increment the contents of Register addressing mode 1 byte
the accumulator by one.

(A) (A)+ 1

Example: INC A ; add one to the content of the accumulator.

Before execution After execution

A= 29H 0010 1001
+01H 0000 0001
A 29H A 2AH 2AH 0010 1010
2 A
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b) INC Rn
Operation Addressing mode Memory space
Increment the contents of Register addressing mode 1 byte
the register Rn ,of the
current register bank by one.

(Rn) (Rn)+ 1

Example: INC R3 ; add one to the contents of the register R3.

Before execution After execution R3=29H 0010 1001

+01H 0000 0001
29H 2AH 2AH 0010 1010
R3 R3
2 A

c) INC addr
Operation Addressing mode Memory space
Increment the contents of Direct addressing mode 2 bytes
the direct address(addr) by
one.

(addr) (addr)+ 1

Example: INC 30H ; add one to the contents of the address 30H.

Before execution After execution

(30H)= 29H 0010 1001

+ 01H 0000 0001
30H 29H 30H 2AH 2AH 0010 1010
2 A
Internal RAM

d) INC @Rp
Operation Addressing mode Memory space
Increment the contents of Indirect addressing mode 1 byte
the memory location whose
address is in Rp by one. Rp
can be either R0 or R1.

(( Rp )) ((Rp))+ 1
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Example: INC @R0 ;add one to the contents of the memory location whose address is in
R0.
Before execution After execution
R0 40H R0 40H
((R0))= 29H 0010 1001
+ 01H 0000 0001
40H 29H 40H 2AH 2AH 0010 1010
2 A

e) INC DPTR
Operation Addressing mode Memory space
Increment the contents of Register addressing mode 1 byte
the data pointer register by
one.

(DPTR) (DPTR) + 1

Example: INC DPTR ;add one to the contents of the DPTR register.

Before execution After execution

DPTR 0520H DPTR 0521H

Decrement instructions

a) DEC A
Operation Addressing mode Memory space
Decrement the contents of Register addressing mode 1 byte
the accumulator by one.

(A) (A) -1

Example: DEC A ; subtract one from the contents of the accumulator.

Before execution After execution A=20H 0010 0000

+(2’s p f 01H) 1111 1111
A 20H A 1FH 1FH 0001 1111
1 F
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b) DEC Rn
Operation Addressing mode Memory space
Decrement the contents of Register addressing mode 1 byte
the register Rn ,of the
current register bank by one.

(Rn) (Rn) - 1

Ex: DEC R2

Before execution After execution

R2 20H R2 1FH

c) DEC addr
Operation Addressing mode Memory space
Decrement the contents of Direct addressing mode 2 bytes
the direct address(addr) by
one.

(addr) (addr) - 1

Ex: DEC 50H

Before execution After execution

50H 20H 50H 1FH

Internal RAM Internal RAM

d) DEC @Rp
Operation Addressing mode Memory space
Decrement the contents of Indirect addressing mode 1 byte
the memory location whose
address is in register Rp by
one. Rp can be either R0 or
R1.

((Rp)) ((Rp)) - 1
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Ex: DEC @ R1

Before execution After execution

R1 30H R1 30H

30H 20H 30H 1FH

Internal RAM Internal RAM

Note:

• There is no instruction for decrementing DPTR.

• No Math flags (CY,AC , OV) are affected for increment and decrement instructions.

➢ Addition and Subtraction operations:

Addition is performed using the accumulator as the destination.
The various addition instructions are:
ADD A, Rn ADDC A, Rn
ADD A, addr ADDC A, addr
ADD A, #D8 ADDC A, #D8
ADD A, @Rp ADDC A, @Rp

NOTE: All math flags are affected.

a) ADD A , Rn
Operation Addressing mode Memory space
Add the contents of the Register addressing mode
register, Rn, of the current
register bank to the contents 1 byte
of the accumulator ; store
the result in the
accumulator.

(Rn) (Rn)+ 1

Example: ADD A , R5
Before execution After execution A=2AH 0010 1010
R5=05H + 0000 0101
A 2AH A 2FH 2FH 0 0010 1111
CY 2 F

R5 05H R5 05H

Flags affected: CY=0 ;AC=0; OV=0; P=1

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b) ADD A , addr
Operation Addressing mode Memory space
Add the contents of the Direct addressing mode 2 bytes
internal RAM address (addr)
to the contents of the
accumulator and store the
result in the accumulator.

(addr) (addr)+ 1

Example: ADD A , 30H

Before execution After execution

A 2AH A 2FH A=2AH 0010 1010

(30H)=05H + 0000 0101
2FH 0 0010 1111
CY 2 F

05H 05H
30H 30H

Internal RAM Internal RAM

Flags affected: CY=0;AC=0;OV=0;P=1.

C) ADD A , @Rp ; ((Rp)) ( (Rp))+ 1

Operation Addressing mode Memory space

Add the contents of the Indirect addressing mode 1 byte
internal RAM location
,whose address is in
register Rp to the contents
of the accumulator and
store the result in the
accumulator.

((Rp)) ( (Rp))+ 1
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Example: ADD A , @R1
Before execution After execution

2AH 2FH A=2AH 0010 1010

A A ((R1))=05H + 0000 0101
2FH 0 0010 1111
CY 2 F
40H 40H
R1 R1

05H 05H
40H R1 40H

Internal RAM Internal RAM

Flags affected: CY=0;AC=0;OV=0;P=1.

d) ADD A , #D8 ;

Operation Addressing mode Memory space

Add the immediate data, D8 Immediate addressing mode 2 bytes
to the contents of the
accumulator and store the
result in the accumulator.

Example: ADD A , #05H

Before execution After execution

2AH 2FH
A A

Flags affected: CY=0; AC=0; OV=0; P=1.

e) ADDC A , Rn; (A) (A) + (addr) + CY

Operation Addressing mode Memory space

Add the contents of the Register addressing mode 1 byte
register Rn, of the current
register bank and the
contents of the carry flag to
the contents of the
accumulator and store the
result in accumulator.
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Before execution After execution CY AC

0 1
A 2AH A 30H A= 23H = 0010 0011

(R1) = 05H = 0000 0110

R1 05H R1 05H CY = 1
0000
0011 0000

Flags affected: CY=0; AC=1; OV=0; P=0.

f) ADDC A , addr

Operation Addressing mode Memory space

Add the contents of the Direct addressing mode 2 bytes
internal RAM and the
contents of the carry flag to
the contents of the
accumulator and store the
result in accumulator.
(A) (A) + (addr) + CY

Ex: ADDC A, 35H

Before execution Before execution

CY AC
0 1
A 2AH A 30H A= 23H = 0010 0011

05H = 0000 0110

CY = 1
0000
0011 0000

Flags affected: CY=0; AC=1; OV=0; P=0.

g) ADDC A , #D8

The given data along with the carry is added with data present in A register and the
result is placed in the register A.
This instruction has immediate mode of addressing.
This is a two byte instruction. The first byte represents the opcode and the second
byte represents the given data
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Ex: ADC A, #05H

Before execution Before execution

CY AC
0 1
A 2AH A 30H A= 2AH = 0010 1010

05H = 0000 0110

CY = 1
0000 0010 0000

Flags affected: CY=0; AC=1; OV=0; P=1.

h) ADDC A , @Rp;

Operation: add the contents of the interanal RAM along with the CARRY flag to the contents of the
accumulator and store the result in the accumumlactor. The address of the RAM is in the register
Rp. The register Rp can be either R0 or R1.

This instruction has indirect mode of addressing and the length of the instruction is one byte.

(A) ( (RP)) + (A) + CY

Ex: ADDC A, @R1

Before execution Before execution

CY AC
0 1
A 2AH A 30H A= 2AH = 0010 1010

((R1)) = 05H = 0000 0110

R1 35H R1 35H CY = 1
0000 0010 0000
0011 0000

05H 35 05H
35

Internal RAM Internal RAM

Flags affected: CY=0; AC=1; OV=0; P=0.

NOTE: SUBTRACTION is performed by taking the two’s complement of the number to

be subtracted, the subtrahend and adding it to the other number, the minuend. The
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Accumulator is used as destination. The commands treat the carry flag as the borrow flag
and always subtracts the carry flag as a part of the operation.
The various subtraction instructions are:
SUBB A ,Rn
SUBB A ,addr
SUBB A ,#D8
SUBB A ,@Rp

a) SUBB A ,Rn; (A) (A) – (Rn) – (CY)

Operation Addressing mode Memory space
Subtract the contents of Register addressing mode 1 byte
the register Rn and the
contents of the carry flag
from the contents of
accumulator and store the
result in accumulator.
Example: SUBB A , R4

Before execution After execution A= 05H 0000 0101

D8 =- 15H + 1110 1011 (2’s p f D8)
A 05H A F0H 1 1111 0000
CY F 0

R4 15H R4 15H

Flags affected: CY=1 ; AC=1 ; OV=0 ; P=0

b) SUBB A ,addr ; (A) (A) – (addr) – (CY)

Operation Addressing mode Memory space
Subtract the contents of Direct addressing mode 2 bytes
the internal RAM and the
contents of the carry flag
from the contents of
accumulator and store the
result in accumulator.
EX: SUBB A, 35H

Before execution After execution

A= 05H 0000 0101
A 05H A F0H
D8 =- 15H + 1110 1011 (2’s p f D8)
15H F0H 1 1111 0000
35H 15H 35H
CY F 0
Flags affected: CY=1 ; AC=1 ; OV=0 ; P=0
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c) SUBB A ,#D8 ; (A) (A) - (CY) – D8

Operation Addressing mode Memory space

Subtract immediate data Immediate addressing 2 bytes
,D8 and the contents of mode
the carry(borrow) flag
from the contents of
accumulator and store the
result in accumulator.

Example: SUBB A ,#05H ;

Before execution After execution A= 15H 0001 0101
D8 =- 05H + 1111 1011 (2’s p f D8)
A 15H A 10H 10H 1 0001 0000
CY

Flags affected: CY=0 ; AC=1 ; OV=0 ; P=1

d) SUBB A ,@Rp ; (A) (A) – ((Rp)) – (CY)

Operation Addressing Memory space
mode
subtract the contents of the internal Indirect 1 byte
RAM location whose address is in addressing
register Rp and also the contents of mode
the carry flag from the accumulator
and store the result in accumulator.

i) Multiplication and Division operations:

❖ 8051 supports only 8 bit-by-8 bit multiplication. Multiplication operation uses

registers A (accumulator) and B as both source and destination operands for the
operation. One of the operands must be in A register and the other operand must be
in B register. The result of operation is stored in both A and B registers, the low
order byte is stored in A register and the high order byte is stored in B register.

MUL AB

Operation Addressing mode Memory space

Multiply the contents of A Register addressing mode 1 byte
and B registers and store
the low order byte of the
product in register A and
the high order byte of the
product in register B.
Flags affected: CY,OV
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NOTE:
• The carry flag is always cleared to 0.
• The overflow flag is set whenever the product A*B is greater than FFh

Example: MUL AB

Before execution After execution

A FFH A 5FH (lower order byte)

B A1H B A0H (higher order byte)

A= FF
B= A1
A0 5FH

❖ 8051 supports only byte –over- byte division. Division operation uses registers
A(accumulator) and B as both source and destination operands for the operation.
DIV AB
Operation Addressing mode Memory space
Divide the contents of the Register addressing mode 1 byte
register A by the contents
of the register B. Store the
integer part of the
quotient in register A and
the remainder in register
B. Flags affected: CY,OV

NOTE:
• The carry flag is always cleared.
• The overflow flag is cleared to 0 unless register B holds 00H before division,
indicating that division by zero is undefined.
• Note: REMAINDER =(DIVIDEND – QUOTIENT *DIVISOR).

Example: DIV AB
Before execution After execution

A A
DBH 0AH
B B A=DBH 0A(quotient)
15H 09H B=15H 09(remainder)
 SAI VIDYA INSTITUTE OF TECHNOLOGY 24

BCD ADDITION

NOTE:BCD (Binary Coded Decimal): the numbers 0 to 9 represent the BCD

numbers. There are two kinds of BCD numbers namely :
a) Unpacked BCD numbers
b) Packed BCD numbers
In an Unpacked BCD number, the lower 4 bits of the number represent the BCD
number and the rest higher 4 bits are zeros. Example:”0000 1001” is the
representation of unpacked BCD number ‘9’.
In a Packed BCD number, a single byte has two BCD numbers, one in the lower
4 bits and one in upper 4 bits. Eg: “0110 0101” is the representation of packed
BCD ‘65’.

j) DA A ( decimal adjust for addition)

The addition is done in ‘binary’ by the microcontroller. The result of this addition
may not be correct when the data is BCD. Therefore, while BCD numbers are added,
the result after the addition needs to be corrected to represent the correct BCD
value.

DA A is the instruction that should be used immediately after performing addition

of BCD numbers. The result after DA A will represent the answer in correct BCD
format.

Working of DA A instruction:
• The microcontroller checks the contents of accumulator. If the lower 4bits of
accumulator is greater than ‘9’ or if auxiliary carry is set then ‘06’ is added to
accumulator and then the auxiliary carry is set.
(A) (A)+06
(AC) 1
• After the above modification, if the higher 4 bits of accumulator is greater
than ‘9’ or carry flag is set, then ‘60’ is added to accumulator and carry flag
is set.
(A) (A) +60
(CY) 1
DA instruction works only after the ADD or ADDC instruction and not after the INC instruction.

3) Logical instructions:
The various logical operations performed by the 8051 microcontroller are the OR, AND, XOR
and the NOT operation .

AND operation:

The general form of AND instruction is: ANL destination, source

The contents of the destination and the source are ANDed and the result is stored in the
destination.
The destination is normally the accumulator; the source operand can be memory, a
Register or an immediate data.
 SAI VIDYA INSTITUTE OF TECHNOLOGY 25
The various forms of AND instructions are:
ANL A, Rn ANL addr, A
ANL A, addr ANL addr, #D8
ANL A, #D8
ANL A, @Rp

a) ANL A, Rn
Operation Addressing mode Memory space
Logically AND each bit of Register addressing mode 1 Byte
the accumulator with the
corresponding bit of
register Rn, of the current
register bank and store
the result in accumulator.

Example: ANL A, R3

Before execution After execution (A) = 75H 0111 0101

(R3)=0BH AND 0000 1011
75H 01H 01H 0000 0001
A A

0BH 0BH
R3 R3

b) ANL A, addr
Operation Addressing mode Memory space
Logically AND each bit of Direct addressing mode 2 Bytes
the accumulator with the
corresponding bit of the
contents of the internal
RAM address(addr) and
store the result in
accumulator.

c) ANL A, #D8

Operation Addressing mode Memory space

Logically AND each bit of Immediate addressing 2 bytes
the accumulator with the mode
corresponding bit of the
immediate data and store
the result in accumulator.
 SAI VIDYA INSTITUTE OF TECHNOLOGY 26
d) ANL A, @Rp
Operation Addressing mode Memory space
Logically AND each bit of Indirect addressing mode 1 Byte
the accumulator with the
corresponding bit of the
immediate data and store
the result in accumulator.

e) ANL addr,A
Operation Addressing mode Memory space
Logically AND each bit of Direct addressing mode 2 Bytes
the accumulator with the
corresponding bit of the
contents of the internal
RAM address (addr) and
store the result in internal
RAM address (addr).

f) ANL addr, #D8

Operation Addressing mode Memory space
Logically AND each bit of Direct addressing mode 3 bytes
immediate data, D8 with
the corresponding bit of
the contents of the
internal RAM address
(addr) and store the result
in internal RAM address
(addr).

1) OR operation:
The general form of OR instruction is: ORL destination, source
The contents of the destination and the source are ORed and the result is stored in the
destination. The destination is normally the accumulator; the source operand can be in
memory, Register or an immediate data.

a) ORL A, Rn
Operation Addressing mode Memory space
Logically OR each bit of Register addressing mode 1 byte
accumulator with the
corresponding bit of
register Rn, of the current
register bank and store
the result in accumulator.
 SAI VIDYA INSTITUTE OF TECHNOLOGY 27
Example: ORL A, R3 ; Logically OR each bit of accumulator with corresponding bit of
data in register R3, of current register bank and store the result in accumulator.

Before execution After execution A=27H 0010 0111

R3=35H OR 0011 0101
A 27H A 37H 37H 0011 0111
3 7

R3 R3
35H 37H

b) ORL A, addr
Operation Addressing mode Memory space
Logically OR each bit of Direct addressing mode 2 bytes
accumulator with the
corresponding bit of the
contents of the internal
RAM address(addr) and
store the result in
accumulator.

c) ORL A,#D8
Operation Addressing mode Memory space
Logically OR each bit of Immediate addressing 2 bytes
accumulator with the mode
corresponding bit of
immediate data, D8 and
store the result in
accumulator.

d) ORL A, @Rp
Operation Addressing mode Memory space
Logically OR each bit of Indirect addressing mode 1 byte
accumulator with the
corresponding bit of the
contents of the internal
RAM address contained in
register Rp and store the
result in accumulator.
 SAI VIDYA INSTITUTE OF TECHNOLOGY 28
e) ORL addr,A
Operation Addressing mode Memory space
Logically OR each bit of Direct 2 bytes
accumulator with the addressing
corresponding bit of the mode
contents of the internal
RAM address (addr) and
store the result in internal
RAM address (addr).

f) ORL addr, #D8

Operation Addressing mode Memory space
Logically OR each bit of Direct addressing mode 3 bytes
the contents of the
internal RAM address
(addr) with the
corresponding bit of the
immediate data, D8 and
store the result in internal
RAM address(addr).

2) XOR operation:

The general form of XOR instruction is: XRL destination, source

The contents of the destination and the source are XORed and the result is stored in
destination. The destination is normally the accumulator, the source operand can be in
memory, a Register or an immediate data.

a) XRL A, Rn
Operation Addressing mode Memory space
Logically XOR each bit of Register addressing mode 1 byte
accumulator with the
corresponding bit of
register Rn, of the current
register bank and store
the result in accumulator.

Example: XRL A, R3

Before execution After execution A=33H 0011 0011

R3=44H XOR 0100 0100
A 33H A 77H 77H 0111 0111
7 7

R3 44H R3 44H
 SAI VIDYA INSTITUTE OF TECHNOLOGY 29
XRL A, addr

Operation Addressing mode Memory space

Logically XOR each bit of Direct addressing mode 2 bytes
accumulator with the
corresponding bit of the
contents of the internal
RAM address(addr) and
store the result in
accumulator.

Before execution Before execution

A 15H A EEH
A= 15H = 0001 0101
((R1)) = -05H = 1111 1011
35 05H
35 05H 1110 1110

Internal RAM Internal RAM

b) XRL A, #D8
Operation Addressing mode Memory space
Logically XOR each bit of Immediate addressing 2 bytes
accumulator with the mode
corresponding bit of
immediate data, D8 and
store the result in
accumulator.

c) XRL A, @Rp
Operation Addressing mode Memory space
Logically XOR each bit of Indirect addressing mode 1 byte
accumulator with the
corresponding bit of
contents of the internal
RAM address contained in
register Rp and store the
result in accumulator.
 SAI VIDYA INSTITUTE OF TECHNOLOGY 30
d) XRL addr,A
Operation Addressing mode Memory space
Logically XOR each bit of Direct addressing mode 2 bytes
accumulator with the
corresponding bit of the
contents of the internal
RAM address (addr) and
store the result in internal
RAM address (addr).

e) XRL addr, #D8

Operation Addressing mode Memory space
Logically XOR each bit of Direct addressing mode 3 bytes
the contents of the
internal RAM address
(addr) with the
corresponding bit of the
immediate data, D8 and
store the result in internal
RAM address(addr).

Clear instruction:

CLR A

Operation Addressing mode Memory space

Clear the contents of Register addressing mode 1 byte
accumulator.

Example: CLR A

Before execution After execution

A 33H A 00H

Complement instruction:

CPL A
Operation Addressing mode Memory space
Complement each bit of Register addressing mode 1 byte
the accumulator, i.e. every
1 becomes a 0 and vice-
versa.
 SAI VIDYA INSTITUTE OF TECHNOLOGY 31
Example: CPL A

Before execution After execution A= A3H 1010 0011

CPL 0101 1100
5C 5 C
A3H 5CH
A A

Rotate and Swap instruction:

There are rotate opcodes that operate only on a byte, or a byte and the carry flag to
allow 8 bit(only a byte) and 9 bit(a byte and a carry flag) shift register operations.
Swap instructions are used to exchange the lower and higher nibbles in a byte.
NOTE: The rotate and the swap instructions are limited to the Accumulator.
The various rotate instructions are:
a) RL A
b) RLC A
c) RR A
d) RRC A
e) SWAP A

a) RL A
Operation Addressing mode Memory space
Rotate the contents of the Register addressing mode 1 byte
accumulator 1 bit position
to the left. The Most
Significant Bit (MSB)
becomes the Least
Significant Bit (LSB).

Before execution

A D7 D6 D5 D4 D3 D2 D1 D0

After execution

A D6 D5 D4 D3 D2 D1 D0 D7

Example: RL A

Before execution: A= D5H 1 1 0 1 0 1 0 1

-----------------------------------------------------------------------------------------------------

After execution: A= ABH 1 0 1 0 1 0 1 1

 SAI VIDYA INSTITUTE OF TECHNOLOGY 32
b) RLC A
Operation Addressing mode Memory space
Rotate the contents of the Register addressing mode 1 byte
accumulator and the carry
bit 1 bit position to the
left. The Most Significant
Bit (MSB) becomes the
carry bit and the carry bit
becomes the Least
Significant Bit (LSB).

Before execution

CY D7 D6 D5 D4 D3 D2 D1 D0

After execution

D7 D6 D5 D4 D3 D2 D1 D0 CY

Example: RLC A

CY
Before execution: A= B5H 1 0 1 1 0 1 0 1
1

-------------------------------------------------------------------------------------------------------
CY
After execution: A= 6BH 0 1 1 0 1 0 1 1
1

c) RR A
Operation Addressing mode Memory space
Rotate the contents of the Register addressing mode 1 byte
accumulator 1 bit position
to the right. The Least
Significant Bit (LSB)
becomes the Most
Significant Bit (MSB).
 SAI VIDYA INSTITUTE OF TECHNOLOGY 33
Before execution

A D7 D6 D5 D4 D3 D2 D1 D0

After execution

A D0 D7 D6 D5 D4 D3 D2 D1

Example: RR A

Before execution: A= 5CH 0 1 0 1 1 1 0 0

-------------------------------------------------------------------------------------------------------

After execution: A= 2EH 0 0 1 0 1 1 1 0

d) RRC A
Operation Addressing mode Memory space
Rotate the contents of the Register addressing mode 1 byte
accumulator and the carry bit
1 bit position to the right. The
Least Significant Bit (LSB)
becomes the carry bit and the
carry bit becomes the Most
Significant Bit (MSB).

Before execution

D7 D6 D5 D4 D3 D2 D1 D0 C

After execution CY

C D7 D6 D5 D4 D3 D2 D1 D0

Example: RRC A

CY
Before execution: A= 7AH 0 1 1 1 1 0 1 0
0

-------------------------------------------------------------------------------------------------------
CY
After execution: A= 3DH 0 0 0 1 1 1 1 0 1
 SAI VIDYA INSTITUTE OF TECHNOLOGY 34
e) SWAP A
Operation Addressing mode Memory space
Exchange the lower and Register addressing mode 1 byte
higher nibbles of the
accumulator.

Before execution

D7 D6 D5 D4 D3 D2 D1 D0
higher nibble lower nibble

After execution

D3 D2 D1 D0 D7 D6 D5 D4
higher nibble lower nibble

3) Boolean variable manipulation instructions:

These instructions affect a single bit of a byte. The bit level Boolean logical opcodes
operate on any bit addressable RAM or SFR bit. The carry flag (CY) in the program
status word (PSW) is the destination for most of the opcodes.
The various Boolean bit level operations are:
a) ANL C, b g) CLR C
b) ANL C, /b h) CLR b
c) ORL C, b i) MOV C, b
d) ORL C, /b j) MOV b, C
e) CPL C k) SETB C
f) CPL b l) SETB b

a) ANL C, b
Operation Addressing mode Memory space
Logically AND the contents Bit addressing mode 2 byte
of the carry flag, C and
the addressed bit, b and
store the result in carry
flag ,C.
 SAI VIDYA INSTITUTE OF TECHNOLOGY 35
Example: ANL C , P2.3
Before execution after execution
CY= (CY) AND (P2.3)
CY 1 CY 0 1 AND 0
CY = 0

Port 2 Port 2

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

0 0

P2.3 P2.3

b) ANL C, /b
Operation Addressing mode Memory space
Logically AND the contents Bit addressing mode 2 byte
of the carry flag, C and
the complement of the
addressed bit, b and store
the result in carry flag ,C.

Example: ANL C, /05H

Before execution After execution

CY= (CY) AND (തതതതതതതതതതതതതതതത

𝑏𝑖𝑡 5 𝑜𝑓20𝐻 )
CY 1 CY 0 1 AND 0
CY = 0

Int RAM Int RAM

7 6 54 3 2 10 7 6 5 4 3 210

20H 1 20H 1
 SAI VIDYA INSTITUTE OF TECHNOLOGY 36
c) ORL C, b
Operation Addressing mode Memory space
Logically OR the contents Bit addressing mode 2 byte
of the carry flag, C and
the addressed bit, b and
store the result in carry
flag ,C.

Example: ORL C , P3.3

Before execution After execution

CY= (CY) OR (P3.3)
CY 1 CY 1 1 OR 0
CY = 1

Port 3 Port 3

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0

P3.3 P3.3
d) ORL C, /b

Operation Addressing mode Memory space

Logically OR the contents of Bit addressing mode 2 byte
the carry flag, C and the
complement of the addressed
bit, b and store the result in
carry flag ,C.

Example: ORL C, /05H

Before execution After execution

CY= (CY) OR (തതതതതതതതതതതതതതതത
𝑏𝑖𝑡 5 𝑜𝑓20𝐻 )
CY 0 CY 0 0 OR 0
CY = 0

Int RAM Int RAM

7 6 54 3 2 10 7 6 5 4 3 210

20H 1 20H 1
 SAI VIDYA INSTITUTE OF TECHNOLOGY 37

e) CPL C
Operation Addressing mode Memory space
Complement the contents Bit inherent addressing 1 byte
of the carry flag, C ,i.e. mode
change 1 to 0 and vice
versa.

Example: CPL C

Before execution After execution

Case(1)

CY 1 CY 0

--------------------------------------------------------

Case(2)

0 1
CY CY

f) CPL b

Operation Addressing mode Memory space

Complement the contents Bit direct addressing mode 2 bytes
of the addressed bit, b
,i.e. change 1 to 0 and
vice versa.
 SAI VIDYA INSTITUTE OF TECHNOLOGY 38

Example: CPL P1.2

Before execution After execution

Case(1)
Port 1 Port 1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1 0

P1.2 P1.2

---------------------------------------------------------------------------

Case(2)
Port 1 Port 1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 1

P1.2 P1.2

g) CLR C

Operation Addressing mode Memory space

Clear the contents of the Bit inherent addressing 1 byte
carry flag to 0. mode

Example: CLR C

Before execution After execution

CY x CY 0

h) CLR b

Operation Addressing mode Memory space

Clear the contents of the Bit direct addressing mode 2 bytes
addressed bit, b to 0.
 SAI VIDYA INSTITUTE OF TECHNOLOGY 39
Example: CLR P0.2 ; clear the contents of the bit 2 of Port0 (P0.2) to 0.

Before execution After execution

Port 0 Port 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
x 0

P0.2 P0.2

i) SETB C

Operation Addressing mode Memory space

Set the contents of the Bit inherent addressing 1 byte
carry flag to 1. mode

Example: SETB C

Before execution After execution

CY x CY 1

j) SETB b

Operation Addressing mode Memory space

Set the contents of the Bit direct addressing mode 2 bytes
addressed bit, b to 1.

Example: SETB P1.5 ; set the contents of the bit 5 of Port1 (P1.5) to 1.

Before execution After execution

Port 1 Port 1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
x 1

P1.5 P1.5
 SAI VIDYA INSTITUTE OF TECHNOLOGY 40
k) MOV C, b
Operation Addressing mode Memory space
Copy the contents of the Bit addressing mode 2 bytes
addressed bit(b), to the
carry flag,C.

Example: MOV C, P2.4 ; copy the contents of bit 4 of port 2(P2.4) to the carry flag, C.

Before execution After execution

CY 1 CY 0

Port 2 Port 2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0

P2.4 P2.4

l) MOV b, C

Operation Addressing mode Memory space

Copy the contents of the Bit addressing mode 2 bytes
carry flag, C to the
addressed bit(b).

Example: MOV P0.4, C ; copy the contents of the carry flag,C to bit 4 of Port 0(P0.4).

Before execution After execution

CY 1 CY 1

Port 0 Port 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 1

P0.4 P0.4

Note:

• No flags , other than the carry flag are affected unless the flag is an addressed bit .
• If the destination is a port bit ,the SFR latch bit is affected , not the pin.
• ANL C, /b and ORL C,/b do not alter the addressed bit b.
 SAI VIDYA INSTITUTE OF TECHNOLOGY 41

JUMP and CALL Instructions

Introduction
The 8051 executes the program sequentially by fetching the instructions from the memory.
The contents of the program counter PC are used as the memory address from where the
instruction is to be fetched. While fetching the instruction from the memory, the PC contents
are automatically incremented so that the PC always contains the memory address of
the next instruction to be fetched. Thus, the microcontroller executes the instructions
sequentially. This concept is demonstrated as shown in the adjacent diagram. The program
is executed from top to bottom of the program memory.

The jump instructions are used to change this sequence of program execution. Since the
microcontroller fetches the instruction from the memory location whose address is present
in the register PC, to change this sequence of program execution the contents of PC must
be altered. Therefore, any jump instruction primarily does only one operation of
changing the contents of PC.

As shown in the adjacent diagram any part of the program or a set of instructions can be
omitted in the execution by using jump instructions which makes the control of program
execution to be diverted to any part of the program.

To realize the jump operation the programmer has to write the JMP instruction in the
program at a point where deviation from the normal sequence of program execution is
required.

Normal execution Jump operation

execution
Program

sequence
JMP Program execution
Instructions not
executed

Program
Program
memory
memory
 SAI VIDYA INSTITUTE OF TECHNOLOGY 42
The various jump instructions are as follows:

Byte level
Conditional
Jump instructions Bit level

Un Conditional Short jump

Absolute jump

Long jump

Unconditional SHORT JUMP instruction

Syntax: SJMP rel_addr

Here the rel_addr is an 8-bit signed number. When the above instruction is executed, the
given 8-bit rel_addr is added to the contents of PC

(PC) (PC) +rel_addr

• Since the PC contents are changed,

the microcontroller is said to perform -128
the jump operation.
• Since the relative address is added to Current location
the PC, the actual contents of PC after
the execution of the instruction 127
depend on the present contents of the
PC. Hence it is called relative mode of
addressing.
• Since the relative address is only 8-bit signed number, the range of the relative
address is -128 to +127. That is from the current location the microcontroller can
jump by 127 locations in the forward direction and 128 locations in the reverse
direction. Therefore, the range of jump is very limited and hence it is called SHORT
jump operation. This is described in the adjacent diagram.

Ex: SJMP 15H

Before execution After execution

PC 2312H PC 2327H

+
 SAI VIDYA INSTITUTE OF TECHNOLOGY 43

ABSOLUTE JUMP OERATION

The program memory of 64KB is divided into 32 parts and each part is called a PAGE. The
64𝐾𝐵
size of the each page is = 2KB. The instruction that performs the jump operation
32
within the same page is called absolute jump operation. The various pages along with the
page addresses are as shown in the following figure.

07FFH 0FFFH FFFFH

. . .
. .

PAGE 31
.
. .
PAGE 0

PAGE 1
.
. . .
. . .
. . .
. . .
0000H 0800H F800H

The absolute jump operation performs the branch operation within the same page. For any
page the address boundary is such that the most significant 5-bits of the address will be the
same and the least significant 11-bits of the address will change. Therefore, the absolute
jump operation will alter only the least significant 11-bits of the program counter PC.

Ex: AJMP abs_addr

11-bit address
The given 11-bits of address will be transferred to the PC and the most significant 5-bits will
remain the same.

Ex: AJMP 5789H

Before After 1235H= 0001 0010 0011 0101

5789H= 0101 0111 1000 1001
PC 1235H PC 1789H
1789H 0001 0111 1000 1001

LONG JUMP OPERATION

This jump instruction is used to jump from any part of the memory to any other part of the
memory. That is, all the 16-bits of the PC are changed by the instruction.
 SAI VIDYA INSTITUTE OF TECHNOLOGY 44
Ex: LJMP addr

The jump operation is performed by loading the PC with the given address.

(PC) Addr

Ex: LJMP 1235H

16-bit address
Before After
PC = 5678H PC=1235H

EX: JMP @A+DPTR

This instruction performs long jump operation by loading the PC with a 16-bit address. The
address is computed by adding the contents of A and DPTR.

(PC) (A) + (DPTR)

Before After
(PC) = 5678H (PC) = 2188H
(A) =65H (A) = 65H
(DPTR) = 2123H (DPTR) = 2123H

CONDITIONAL JUMP INSTRUCTIONS

Conditional jump instructions are used to perform jump operation based on a user specified
condition. Every conditional jump instruction specifies a condition.

The operation of conditional instruction:

• Microcontroller checks the condition specified in the instruction. If the condition is

true, then the microcontroller performs the jump operation by adding the rel_addr
given in the instruction to the program counter PC.

(PC) (PC) +rel_addr

• If the condition is false, the PC contents are not modified and the microcontroller will
execute the next instruction in the sequence as usual or the microcontroller will not
perform the jump operation.
 SAI VIDYA INSTITUTE OF TECHNOLOGY 45

The various conditional jump instructions are as follows:

Conditional jump instructions

Based on the bit status Based on Based on decrement Based on comparison

accumulator
Conditional jump instructions operation
based on bits (BIT JUMP)
Contents
JC rel_addr

Description: JC instruction will branch to the address indicated by rel_addr if the Carry bit is
set.
The jump operation is performed by adding the rel_addr to the contents of PC.

(PC) (PC)+rel_addr
If the Carry bit is not set program execution continues with the instruction following the JC
instruction. This is a short jump instruction.

Ex: JC 20H

Before After

PC 3000H PC 3020H If CY =1

PC 3000H If CY =0

JNC rel_addr

Description: JNC instruction will branch to the address indicated by rel_addr if the Carry bit
is reset.
The jump operation is performed by adding the rel_addr to the contents of PC.

(PC) (PC)+rel_addr

If the Carry bit is set program execution continues with the instruction following the JNC
instruction. This is a short jump instruction.
 SAI VIDYA INSTITUTE OF TECHNOLOGY 46

Ex: JNC 20H

Before After

PC 3000H PC 3020H If CY =0

PC 3000H If CY =1

JB b, rel_addr

Description: JB instruction will branch to the address indicated by rel_addr if the specified
bit is set. In the above instruction the b is the bit address.

The jump operation is performed by adding the rel_addr to the contents of PC.

(PC) (PC)+rel_addr

If the specified bit is reset program execution continues with the instruction following the JB
instruction. This is a short jump instruction.

Ex: JB P2.0, 20H

Before After

PC 3000H

Case1 1 PC
P2.0 3020H

Case2 P2.0 0 PC 3000H

JNB b, rel_addr

Description: JNB instruction will branch to the address indicated by rel_addr if the specified
bit is reset. In the above instruction the b is the bit address.

The jump operation is performed by adding the rel_addr to the contents of PC.

(PC) (PC)+rel_addr
 SAI VIDYA INSTITUTE OF TECHNOLOGY 47

If the specified bit is set program execution continues with the instruction following the JNB
instruction. This is a short jump instruction.

Ex: JNB P2.0, 20H

Before After

PC 3000H

Case1 PC
P2.0 1 3000H

Case2 P2.0 0 PC 3020H

JBC b, rel_addr

Description: JBC instruction will branch to the address indicated by rel_addr if the specified
bit is set. After performing the jump operation, the specified bit is reset. In the above
instruction the b is the bit address.

The jump operation is performed by adding the rel_addr to the contents of PC.

(PC) (PC)+rel_addr

If the specified bit is reset program execution continues with the instruction following the
JBC instruction. This is a short jump instruction.

Ex: JBC P2.0, 20H

Before After

PC 3000H

Case1 PC P2.0 0
P2.0 1 3020H

Case2 P2.0 0 PC P2.0 0

3000H
 SAI VIDYA INSTITUTE OF TECHNOLOGY 48

CONDITIONAL JUMP INSTRUCTIONS BASED ON ACCUMULATOR CONTENTS (BYTE

JUMP)

Syntax: JZ rel_addr

Description: JZ instruction will branch to the address indicated by rel_addr if the

accumulator contents are zero. The jump operation is performed by adding the rel_addr to
the contents of PC. (PC) (PC)+rel_addr
If the accumulator contents are not zero, program execution continues with the instruction
following the JZ instruction. This is a short jump instruction.
Ex: JZ 20H Before After

PC 3000H

Case1 PC
A 00H 3020H

Case2 A PC
05H 3000H

Syntax: JNZ rel_addr

Description: JNZ instruction will branch to the address indicated by rel_addr if the
accumulator contents are not zero.
The jump operation is performed by adding the rel_addr to the contents of PC.

(PC) (PC)+rel_addr

If the accumulator contents are zero, program execution continues with the instruction
following the JNZ instruction. This is a short jump instruction.

Ex: JNZ 20H

Before After

PC 3000H

Case1 PC
A 00H 3000H

Case2 A 05H PC 3020H

 SAI VIDYA INSTITUTE OF TECHNOLOGY 49

Conditional jump instruction based on decrement operation

General form of the instruction: DJNZ opr , rel_addr

Description: The contents of the specified operand are decremented by 1 and the result is
placed in the same operand. Ex1 : DJNZ R7, 50H

(opr) (opr)-1

Before After
PC=3000H

Case1: R7 = 36H R7= 35H; PC= 3050H ( jump operation)

Case2: R7 = 01H R7= 00H; PC= 3000H (no jump operation)

After decrementing the contents of the operand the microcontroller performs the jump
operation if the contents of the operand are not zero.

Ex2 : DJNZ 35H, 50H

In the above instruction, 35h is

Before After
the address of the RAM location
whose contents are PC=3000H
decremented. That is, the RAM Case1:35H 36H 35h 35H; PC= 3050H ( jump operation)
location 35H is the operand of
the instruction. Case2: 35H 01H 35H 00H; PC= 3000H (no jump operation)

Conditional Jump Instructions Based on Compare Operation

Syntax: CJNE A , #N , rel_addr

The first operand is compared with the second operand. The comparison is done by
subtracting the second operand from the first operand. But the result is not placed in any of
the two operands and only flags are affected.

If the two operands are not equal, then microcontroller performs jump operation by adding
the given relative address to the program counter.

(PC) (PC)+ rel_addr

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If the two operands are equal, then the PC contents are not affected and the microcontroller
executes the next instruction in the sequence without performing jump operation.

EX: CJNE A , #35H , 75H

Before After Remarks

Case1: The two operands
(A)=56H (A)=56H are not equal hence
(PC)=3000H (PC)=3075H microcontroller performs jump operation
Case2: The two operands are equal hence
(A)=35H (A)=35H microcontroller does not perform jump operation
(PC)=3000H (PC)=3000H
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The list of data transfer instructions with the internal data memory

MOV Rn, A MOV addr, A MOV @RP, A

MOV A, Rn MOV addr, Rn
MOV A, addr MOV Rn, addr MOV addr, addr MOV @RP , addr
MOV A, #D8 MOV Rn, #D8 MOV addr, #D8 MOV @RP , #D8
MOV A, @RP MOV addr, @RP

List of exchange Stack related

INSTRUCTIONS 1 6-BIT data transfer
MOV DPTR,#NN instructions
XCH A, Rn MOV DPTR,#NN
XCH A, addr PUSH addr
XCH A , @ RP POP addr
XCHD A, @RP

The list of data transfer instructions with the external memory

Data memory Program memory

MOVX A, @R0 MOVC A, @A+PC
MOV X A, @R1 MOVC A, @A+DPTR
MOV X A, @ DPTR
MOVX @R0, A
MOVX @R1, A
MOV X @ DPTR, A

ADDITION
Instructions

ADD A, Rn

ADD A, addr

ADD A, #D8

ADD A, @RP

ADDC A, Rn

ADDC A, addr

ADD A, #D8
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ADDC A, @RP List of arithmetic instructions:

DA A SUBTRACTION
DECREMENT
Instructions Increment
Instructions
SUBB A, Rn instructions
DEC A
SUBB A, addr INC A
DEC Rn
SUBB A, #D8 INC addr
DEC addr
SUBB A, @RP INC DPTR
DEC @RP
INC @RP
INC Rn

Multiplication
& Division
Instructions
MUL AB
DIV AB

List of logical instructions:

Byte level AND

instructions Clear/ complement
ANL A, Rn Of Accumulator ROTATE instructions
ANL A, addr CLR A RL A
ANL A, #D8 CPL A RLC A
ANL A, @RP RR A
ANL addr, A RRC A
ANL addr, #D8 SWAP A
Byte level OR
s s s
instructions
Byte level XOR ORL A, Rn
Instructions ORL A, addr
XRL A, Rn ORL A, #D8
XRL A, addr ORL A, @RP
XRL A, #D8 ORL addr, A
XRL A, @RP ORL addr, #D8
XRL addr, A
XRL addr, #D8
List of branch instructions:

Unconditional
Jump instructions
SJMP rel_addr
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AJMP abs_addr
L JMP addr_16 Decrement &
JMP @A+DPTR Jump instructions
DJNZ addr, rel_addr
DJNZ Rn, rel_addr

Conditional
Jump instructions Compare &
JC rel_addr Jump instructions
JNC rel_addr CJNE A, addr, rel_addr
JB b, rel_addr CJNE A, #D8, rel_addr
JNB b, rel_addr CJNE @RP, #D8, rel_addr
JBC b, rel_addr CJNE Rn, A, rel_addr
JZ rel_addr
JNZ rel_addr

Subroutine
Instructions
ACALL abs_addr
LCALL addr_16
RET
RETI

VTU QUESTIONS:

June-July 2008

1. Write a program to put the number 34H in register R4, R5, R6 using three different addressing
modes –(6 marks)
2. Write a program to swap the contents of R7 and R6 in register block 0in four different ways ---( 8
marks)
3. Write a program to find the address of first two internal RAM locations between 20h and 60h
that contains consecutive numbers. If so set the carry flag to 1 otherwise clear the carry flag,
using a subroutine.----(7 marks )
June- July 2009

1. Write an ALP to add w p d ’s f 16 s h dd ss g d s. (6 ks )

Dec 09/ jan 10
1. Write an ALP in 8051 to find the largest number among the twelve 8bit numbers stored in the
internal RAM.---- (7 marks )
May/Jun 2010
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1. Write an assembly program in 8051 to add two 16 bit numbers stored in external memory
after the addition the result must be stored in internal data memory.
1. Find the address of first two internal RAM locations between the addresses 20H and 40H which
contain the consecutive members. If so set the carry flag otherwise reset the carry flag - - (6)
2. write a program to convert the BCD number 29 in to ASCII value and display the result on port 1
and port 2 – (6)
Dec 2011

1. Write a program to find the sum of 20 bytes of data stored in an array of external RAM starting
with address 2000H. store the 16-bit result at the end of the array.
2. Write the main program to find the value of P = N! / R!. using a subroutine find the value of
factorial of given number. The values of N and R are stored in locations 30H and 31H. the result
P must be stored in location 32H.
June-July 2008

1. Explain the operations performed by the following instructions ---( 6 marks)

SWAP A MOV C, b DA A SUBB A, Rn
2. Explain the different ranges for JMP instruction available in 8051 microcontroller.--- ( 8
marks)
Dec 08/ Jan 09

1 Explain the instructions with examples (6 marks )

SWAP A , MOVX, XCHD, DA A
2.What is stack? Explain with examples PUSH and POP instructions (8 marks )

June –July 2009

1. What is addressing mode? Explain the different addressing modes with examples. (9 marks)
2. Show the specific memory area for bit level logical instructions used in 8051 and list bit level
logical instructions. –(5 marks )
3. Explain the following instruction with their functions, bytes and cycles used: (10 marks)
(i)CJNE dest, source target (ii) ACALL target (ii)DJNZ R1, target (iv) SWAP A(v) DA A

4. Explain the different types of JUMP instructions in 8051. ------- (6 marks)

Dec 09/ jan 10
1. Explain the addressing modes of 8051 with examples (8 marks )
2. Correct the instruction and explain the corrected instructions (5 marks )
MOV #C, 0A MOV A, RS1 MOV A,@R7 MOV 0346H, @R0 XCHG B, @R3
June / July 2011

1. Explain the addressing modes of 8051----(8 marks )

2. Explain the following instruction with examples
SUBB A, direct PUSH direct MOVC A, @A+DPTR
1. Examine the following code and analyze the result with flag register contents----(6 marks )
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MOV A, #+96
MOV R1, #+70
ADD A, R1
2. What are the steps executed by 8051 for the following instruction:
RET AJMP addr
May/Jun 2010

Name the addressing modes of the following instructions

(a) MOVC A,@A+DPTR, (b) MUL AB, (C) MOV B, #0FFH, (d) SUBB A, 45H

Explain any two data transfer and any one arithmetic instruction of 8051. Give an example for
each ----(6)

Dec 2010

1. Explain the addressing modes of 8051 and give an example for each – (7)
2. Explain the different conditional and unconditional JMP instruction of 8051 and specify the
range of each instruction. - - - (8)
3. Explain the following instructions of 8051
(a) XCHD A, @Ri, (b) MOV C, A , (c) SWAP A, (d) RL A, (e) MUL AB (f) DA A – (9)

Dec 2011

1. (i) What is the necessity of flag in microcontroller?

(ii) Which flags are affected in 8051 when the INC A instruction is executed?
(iii) For what condition the OV flag of 8051 is set after addition?
(iv) Can the result of logical AND instruction be stored in some destination other than
accumulator? If so indicate such instructions
(v) Give two examples of 9-bit rotate instructions ----(5 marks)
2. Explain the addressing modes with examples ----( 6 marks )